JPH07151872A - Semiconductor integrated circuit for timepiece - Google Patents

Abstract

PURPOSE:To make it possible to realize an IC for timepiece of a plurality of specifications with one IC for timepiece by using a semiconductor non-volatile memory as a switching means, and slecting the outputs of a plurality of motor- driving-pulse generating circuits. CONSTITUTION:When the output of a pulse-motor driving pulse generating circuit 103 is required, a semiconductor non-volatile memory 106 is turned on through a memory writing circuit for writing semiconductor non-volatile memory data, and a semiconductor non-volatile memory 107 is turned off. Only the output of the circuit 103 is transferred to a pulse-motor driving circuit 105. When the output of a pulse-motor driving pulse generating circuit 104 is required, the memory 107 is turned on, and the memory 106 is turned off so that only the output of the circuit 104 is transferred to the circuit 105. When these operations are performed, the pulse waveform as required is readily obtained. Therefore, the IC for timepiece having a plurality of specifications can be realized with one IC for timepiece, and the development time and the manufacturing time can be greatly shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit used for an analog timepiece.

[0002]

2. Description of the Related Art In recent years, various timepieces have been shipped to the market, and semiconductor integrated circuits used in the timepieces have been diversified.

FIG. 3 is a block diagram showing the structure of a conventional analog clock circuit. The analog clock circuit will be described with reference to FIG. The oscillation frequency of the crystal oscillator circuit 301 is
The frequency dividing circuit 302 divides the frequency to a frequency required to drive the second hand or minute hand of the clock and outputs a plurality of frequencies.

Further, the pulse motor driving pulse generating circuit 303 combines a plurality of frequencies output from the frequency dividing circuit 302 and outputs a pulse waveform required for driving the second hand or the minute hand.

The pulse motor drive circuit 304 is a low-impedance driver, which causes a current to flow through a drive coil (not shown), which causes a magnetic action to cause a rotor (not shown) to rotate. , Rotate the rotor to drive the second hand or minute hand.

[0006] There are various types of analog timepieces, such as a timepiece that drives the second hand every second and a timepiece that does not have the second hand and drives the minute hand every few seconds. If the specifications of the timepiece change, the second hand or the minute hand may change. A pulse generator circuit 303 for driving a pulse motor having various pulse waveforms is required to change the drive coil and the rotor for driving the motor and to drive the second hand or minute hand with certainty.

Therefore, by changing the design of the pulse motor driving pulse generation circuit 303 according to the specifications of the timepiece, the pulse motor driving pulse generation circuit 303 is designed.
We produce watches with various specifications by changing the pulse waveform that is the output of and producing a dedicated semiconductor integrated circuit that matches the specifications of the watch.

Further, in order to drive the rotor normally in consideration of variations in parts used in the timepiece, variations in the assembly process, and the stop position of the rotor in producing the timepiece, the pulse generation for driving the pulse motor is generated. Circuit 30
It is necessary to set the pulse waveform, which is the output of No. 3, to a large value. In this case, if the rotor can be driven with a shorter pulse waveform, there is a problem that wasteful current is consumed.

As means for solving the above problems, there is a circuit means called a load compensation circuit. The load compensation circuit will be briefly described below.

The load compensating circuit monitors the rotation state of the rotor and optimizes the pulse waveform output by the pulse generating circuit 303 for driving the pulse motor to the pulse waveform required for the rotor to rotate properly, thus reducing the power consumption of the watch. Is a means of realizing

In recent years, various methods have been considered for the load compensation circuit, and the pulse generation circuit 303 for driving the pulse motor is used.
Similarly, by changing the design of the load compensating circuit according to the specifications of the timepiece, a dedicated semiconductor integrated circuit according to the specifications of the timepiece is produced to manufacture timepieces of various specifications.

[0012]

As is clear from the above description, making a dedicated semiconductor integrated circuit according to the specifications of a timepiece requires a development period and a semiconductor manufacturing time spent for making a new semiconductor integrated circuit. Need time equal to.

As another means for solving the above-mentioned problems, a contact hole mask used in a post process of a semiconductor manufacturing process and polysilicon, aluminum as a means for supplementing a timepiece having a plurality of specifications with one semiconductor integrated circuit. There is a method to change the wiring mask depending on the specification.

Further, as means for solving the above problems,
An analog switch or a tri-state buffer is used as a switch for selecting outputs of a plurality of pulse motor driving pulse generation circuits and a plurality of load compensation circuits as a means for supplementing a plurality of specifications of a timepiece with one semiconductor integrated circuit. There is a means for providing a decoder circuit as a selection circuit for selecting the switch and pulling down all the inputs of the decoder circuit to the ground or the power supply.

However, the contact hole mask,
In the case of a semiconductor integrated circuit in which the wiring mask is changed, the pre-process of the semiconductor manufacturing process can be reduced, but the post-process, especially the development time and the semiconductor manufacturing time spent in the post-process still remain.

Further, in the case of a semiconductor integrated circuit using a decoder circuit, all the decoder inputs are wired to the power supply or the ground with a copper wire pattern on a substrate on which the semiconductor integrated circuit is mounted, and a drill is used to match the desired clock specifications. Or it is necessary to use a laser to cut the copper wire pattern on the substrate. Therefore, after mounting the semiconductor integrated circuit on the substrate, a new process is added.

An object of the present invention is to solve the above problems, to eliminate the addition of a new process by cutting a copper wire pattern with a drill or a laser, or to develop a contact hole mask and a wiring mask. It is an object of the present invention to provide a means capable of reducing time and stably supplying a semiconductor integrated circuit for a timepiece.

[0018]

To achieve the above object, the present invention provides a desired pulse motor from a plurality of pulse motor driving pulse generation circuits and outputs of the plurality of pulse motor driving pulse generation circuits. And a semiconductor non-volatile memory for selecting an output of the driving pulse generation circuit.

Further, the present invention is characterized by having a plurality of load compensating circuits and a semiconductor non-volatile memory for selecting a desired output of the load compensating circuit from outputs of the plurality of load compensating circuits.

[0020]

In the semiconductor integrated circuit for a timepiece, the desired pulse motor drive can be performed by writing the data in accordance with the specifications of the timepiece to the semiconductor non-volatile memory connected to the plurality of pulse motor drive pulse generation circuits or load compensation circuits. It is possible to obtain the output of the pulse generator circuit or load compensating circuit for use, and it is possible to provide a watch semiconductor integrated circuit having a plurality of specifications with one watch semiconductor integrated circuit.

[0021]

First Embodiment FIG. 1 is a block diagram showing the configuration of an analog timepiece according to the first embodiment of the present invention. Embodiment 1 of the present invention will be described below with reference to FIG.

In the semiconductor integrated circuit for a timepiece of the invention, the second hand is formed by combining the crystal oscillating circuit 101, the frequency dividing circuit 102 for dividing the oscillation frequency of the crystal oscillating circuit 101, and the plurality of frequencies output from the frequency dividing circuit 102. Alternatively, the first pulse motor driving pulse generation circuit 103 that outputs a pulse waveform required to drive the minute hand and the pulse waveform that is different from the pulse waveform that is output by the first pulse motor driving pulse generation circuit 103 are output. And a second pulse motor drive pulse generation circuit 104 for driving.

In addition, the pulse waveform output from the first pulse motor driving pulse generation circuit 103 or the second pulse motor driving pulse generation circuit 104 is input, a current is passed through a driving coil (not shown), and the second hand Alternatively, a pulse motor driving circuit 105 which is a low impedance driver for driving the minute hand is provided.

Further, the first pulse motor driving pulse generation circuit 1 to be inputted to the pulse motor driving circuit 105.
First semiconductor non-volatile memory 10 for opening and closing the output of 03.
6. A second semiconductor nonvolatile memory 107 that opens and closes the output of the second pulse motor driving pulse generation circuit 104 which is also input to the pulse motor driving circuit 105.

When the output of the first pulse motor driving pulse generation circuit 103 is required, the first pulse motor driving pulse generation circuit 103 outputs the first data via the memory writing circuit for writing the semiconductor nonvolatile memory data.
Of the semiconductor non-volatile memory 106 of “on” and the second semiconductor non-volatile memory 107 of “off”,
Only the output of the first pulse motor driving pulse generation circuit 103 is transmitted.

Further, when the output of the second pulse motor driving pulse generation circuit 104 is required, the second semiconductor non-volatile memory 107 is turned on via the memory writing circuit for writing the semiconductor non-volatile memory data. To turn off the first semiconductor non-volatile memory 106 and turn off the second pulse motor driving pulse generation circuit 1
Only the output of 04 is transmitted. By performing such an operation, it is possible to easily obtain the required pulse waveform.

Here, the first semiconductor nonvolatile memory 10
6 and the second semiconductor nonvolatile memory 107 are used as switch means. Of course, it is also possible to prepare a plurality of semiconductor non-volatile memories as the selection means of the outputs of the plurality of pulse motor driving pulse generation circuits to obtain the outputs of various pulse motor driving pulse generation circuits.

[0028]

Second Embodiment FIG. 2 is a block diagram showing the configuration of an analog timepiece according to the second embodiment of the present invention. Embodiment 2 of the present invention will be described below with reference to FIG.

Crystal oscillator circuit 201 and crystal oscillator circuit 20
A pulse motor driving pulse generation circuit 203 that outputs a pulse waveform sufficient for driving the second hand or the minute hand by combining a frequency dividing circuit 202 that divides the oscillation frequency of 1 and a plurality of frequencies that the frequency dividing circuit 202 outputs. To provide.

Pulse generation circuit 20 for driving the pulse motor
A pulse motor driving circuit 204, which is a low-impedance driver for driving the second hand or the minute hand, is provided by inputting the pulse waveform output by 3 and passing a current through a driving coil (not shown).

Further, a pulse motor drive circuit 204,
Between the pulse generation circuit 203 for driving the pulse motor,
This is a structure in which a first semiconductor non-volatile memory 206 is connected in series with the first load compensation circuit 205 and a second semiconductor non-volatile memory 208 is connected in series with the second load compensation circuit 207.

The first load compensating circuit 205 and the second load compensating circuit 207 transmit the rotation information of the rotor obtained from the pulse motor driving circuit 204 to the pulse motor driving pulse generating circuit 203 to generate the pulse motor driving pulse. The power consumption of the timepiece is reduced by optimizing the pulse waveform output from the generation circuit 203.

Also in this case, as in the first embodiment, the first semiconductor non-volatile memory 206 or the second semiconductor non-volatile memory 208 is used as the switch means. Of course, it is also possible to prepare a plurality of semiconductor non-volatile memories as a means for selecting the outputs of the plurality of load compensating circuits and obtain the desired output of the load compensating circuits.

As the semiconductor nonvolatile memory described above, various laser fuse melting type and junction destruction type PROMs in which information can be written only once, and EEPROMs in which information written electrically can be corrected can be considered. .

[0035]

According to the present invention, in the semiconductor integrated circuit for a timepiece, by using the semiconductor nonvolatile memory as the switch means, the outputs of the plurality of pulse motor driving pulse generation circuits and the plurality of load compensation circuits can be obtained. By selecting, a timepiece semiconductor integrated circuit having a plurality of specifications can be realized by one timepiece semiconductor integrated circuit, and development time and semiconductor manufacturing time can be significantly reduced.

Further, in the configuration using the semiconductor non-volatile memory as the switch means like the present invention, since the information has already been written in the semiconductor non-volatile memory at the time of shipment, it is different from the conventional one. Compared with the method of cutting a copper wire pattern on a board using a drill or a laser, the time spent in the post-process after shipping can be greatly reduced, and a stable supply of semiconductor integrated circuits for watches can be performed. Needless to say.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an analog clock circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an analog clock circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional analog clock circuit.

[Explanation of symbols]

 101 Crystal Oscillation Circuit 102 Frequency Dividing Circuit 103 First Pulse Motor Driving Pulse Generation Circuit 104 Second Pulse Motor Driving Pulse Generation Circuit 105 Pulse Motor Driving Circuit 106 First Semiconductor Nonvolatile Memory 107 Second Semiconductor Nonvolatile memory

Claims (2)

[Claims] 1. A semiconductor nonvolatile memory for selecting a desired pulse motor drive pulse generation circuit output from the outputs of the plurality of pulse motor drive pulse generation circuits. A semiconductor integrated circuit for a watch, comprising: 2. A semiconductor integrated device for a watch, comprising: a plurality of load compensating circuits; and a semiconductor nonvolatile memory for selecting a desired output of the load compensating circuit from outputs of the plurality of load compensating circuits. circuit.