JPH0714975A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0714975A JPH0714975A JP5154055A JP15405593A JPH0714975A JP H0714975 A JPH0714975 A JP H0714975A JP 5154055 A JP5154055 A JP 5154055A JP 15405593 A JP15405593 A JP 15405593A JP H0714975 A JPH0714975 A JP H0714975A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- semiconductor device
- buffer plate
- stress buffer
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂封止型半導体装置の半導体素子搭載部の構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a semiconductor element mounting portion of a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置は図４に示
すように、半導体素子１をリードフレームのタブ２上に
銀ペースト等のロー材により固着した後、半導体素子１
上の電極３とリードフレームのインナーリード４を金線
５等で結線し樹脂７で封止する。その後、アウターリー
ド６にメッキ処理、所定形状の加工等を施し半導体装置
を完成させる。リードフレームは鉄−ニッケル合金や銅
合金の薄板をエッチングやスタンピングにより加工した
ものが用いられる。2. Description of the Related Art In a conventional resin-sealed semiconductor device, as shown in FIG. 4, after a semiconductor element 1 is fixed on a tab 2 of a lead frame by a brazing material such as silver paste, the semiconductor element 1
The upper electrode 3 and the inner lead 4 of the lead frame are connected with a gold wire 5 or the like and sealed with a resin 7. After that, the outer leads 6 are plated, processed into a predetermined shape, etc. to complete the semiconductor device. As the lead frame, a thin plate of iron-nickel alloy or copper alloy processed by etching or stamping is used.
【０００３】しかし、このように構成された半導体装置
においては、鉄−ニッケル系リードフレームを使用する
ため、熱伝導率が小さく、半導体素子１から生ずる熱を
外部に逃がしにくい、すなわち熱抵抗が高いため半導体
装置の信頼性の低下を招いていた。また熱伝導率の大き
い銅系リードフレームを使用した場合は半導体素子のシ
リコン基板との熱膨張係数が大きく異なるため、外部環
境の温度変動で生ずるストレスにより半導体素子、もし
くは樹脂部が破壊するという問題点があった。特に半導
体素子が大型で、半導体装置の樹脂部の厚さが薄い場合
は顕者にこの現象が現れる。たとえば、半導体素子の大
きさが１００ｍｍ2 程度で半導体装置の厚さが１ｍｍで
ある場合、−６５℃〜１５０℃の温度サイクル試験を実
施すると１００サイクル程度で樹脂部にクラックを生じ
てしまう。However, in the semiconductor device having such a structure, since the iron-nickel lead frame is used, the thermal conductivity is small and the heat generated from the semiconductor element 1 is difficult to escape to the outside, that is, the thermal resistance is high. Therefore, the reliability of the semiconductor device is lowered. In addition, when a copper-based lead frame with high thermal conductivity is used, the coefficient of thermal expansion of the semiconductor element is significantly different from that of the silicon substrate, so the semiconductor element or the resin part is destroyed by stress caused by temperature fluctuations in the external environment. There was a point. In particular, when the semiconductor element is large and the resin portion of the semiconductor device is thin, this phenomenon appears to the observer. For example, when the size of the semiconductor element is about 100 mm 2 and the thickness of the semiconductor device is 1 mm, a temperature cycle test of −65 ° C. to 150 ° C. causes a crack in the resin portion in about 100 cycles.
【０００４】これらの欠点を解決するためにタブを鉄−
ニッケル合金でそしてリードを銅合金で形成し、タブと
半導体素子の熱膨張系数の差を小さくした半導体装置用
リードフレーム（特開昭６２−２１３２７０号公報）
や、タブを銅・インバー・銅からなる３層のクラッド材
で構成したリードフレーム（特開平０２−９０６６３号
公報）などが提案されている。In order to solve these drawbacks, iron tabs are used.
A lead frame for a semiconductor device in which a lead is formed of a nickel alloy and a lead is formed of a copper alloy to reduce the difference in coefficient of thermal expansion between the tab and the semiconductor element (Japanese Patent Laid-Open No. 62-213270).
Alternatively, there has been proposed a lead frame (Japanese Patent Laid-Open No. 02-90663) in which a tab is composed of a three-layer clad material made of copper, invar, and copper.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、これら
のリードフレームでは、タブ部を別に作りスポット溶接
等でリードフレームに接続しているため製造コストが割
高になるという問題点がある。更に、溶接部に突起が生
じるため、半導体装置の製造工程中のリードフレームの
搬送が非常に困難になり、作業性が悪化するという問題
点があった。However, these lead frames have a problem that the manufacturing cost becomes high because the tab portion is separately formed and connected to the lead frame by spot welding or the like. Further, since the protrusions are formed in the welded part, it becomes very difficult to convey the lead frame during the manufacturing process of the semiconductor device, which causes a problem that workability is deteriorated.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
耐熱性フィルムと、この耐熱性フィルム上に接着され開
口部を有し銅または銅合金からなるタブと、前記開口部
内で前記耐熱性フィルムに接着され前記タブと同じ厚さ
の応力緩衝板と、少なくともこの応力緩衝板に固着され
た半導体素子とを含むものである。The semiconductor device of the present invention comprises:
A heat-resistant film, a tab made of copper or a copper alloy having an opening bonded on the heat-resistant film, and a stress buffer plate having the same thickness as the tab bonded to the heat-resistant film in the opening, At least the semiconductor element fixed to the stress buffer plate is included.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は本発明の一実施例の平面図及
びＡ−Ａ線断面図である。The present invention will be described below with reference to the drawings. 1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA of an embodiment of the present invention.
【０００８】図１（ａ），（ｂ）において、銅合金のリ
ードフレームのタブ２に、半導体素子１の大きさより若
干大きめの開口部１２をリードフレームの製造時にエッ
チング法、またはプレス法などで形成する。その後、耐
熱性フィルム（例えばカプトン、ユーピレックスなど）
を熱硬化性、あるいは熱可塑性の接着剤１０によりタブ
２の裏面より接着する。次に銅又は銅合金より小さい熱
膨張係数を有する素材〔例えば鉄−４２％ニッケル合金
（熱膨張係数：４．０×１０-6／℃）、コバール（熱膨
張係数；５．３×１０-6／℃）など〕からなりタブ２と
同じ厚さの応力緩衝板８を開口部１２内のフィルムに接
着剤１０を介して熱圧着する。半導体素子１は銀ペース
ト９を応力緩衝板８上に塗布した後、載置して２００℃
程度で加熱し固着する。その後は図４に示した従来の半
導体装置の場合と同様にボンデング、樹脂封入、メッ
キ、リード加工等の工程を経て半導体装置を完成させ
る。1A and 1B, an opening 12 slightly larger than the size of the semiconductor element 1 is formed in the tab 2 of the copper alloy lead frame by an etching method or a pressing method when the lead frame is manufactured. Form. Then heat resistant film (eg Kapton, Upilex, etc.)
Are bonded from the back surface of the tab 2 with a thermosetting or thermoplastic adhesive 10. Then the material [e.g., iron -42% nickel alloy having a small thermal expansion coefficient of copper or a copper alloy (thermal expansion coefficient: 4.0 × 10 -6 / ℃) , Kovar (coefficient of thermal expansion; 5.3 × 10 - 6 / ° C.) etc.] and the stress buffer plate 8 having the same thickness as the tab 2 is thermocompression bonded to the film in the opening 12 via the adhesive 10. The semiconductor element 1 is applied with the silver paste 9 on the stress buffer plate 8 and then placed on the stress buffer plate 8 at 200 ° C.
It heats up to a certain degree and sticks. Thereafter, as in the case of the conventional semiconductor device shown in FIG. 4, the semiconductor device is completed through steps such as bonding, resin encapsulation, plating and lead processing.
【０００９】本実施例では半導体素子の大きさが２００
ｍｍ2 程度の面積以下で、かつ応力緩衝板８の熱膨張係
数がシリコン（熱膨張係数：３．０×１０-6／℃）の約
２倍以内あれば、半導体装置の樹脂部の厚さによらず外
部環境温度が、−６５℃〜１５０℃の温度サイクル試験
において、１０００サイクルまで半導体装置の樹脂部に
クラックが発生し信頼性の低下を招くことはなかった。
また、熱抵抗はタブ全体が銅合金からなる従来例よりも
１０％程度高くなるだけで、タブ全体が鉄−ニッケル合
金の場合と比較し約５％低くなる。したがって熱の問題
による半導体装置の信頼性低下の確率は低くなってい
る。In this embodiment, the size of the semiconductor device is 200
The thickness of the resin portion of the semiconductor device is equal to or less than about 2 mm 2 and the thermal expansion coefficient of the stress buffer plate 8 is within about twice that of silicon (coefficient of thermal expansion: 3.0 × 10 −6 / ° C.). Regardless of the above, in the temperature cycle test in which the external environment temperature is −65 ° C. to 150 ° C., cracks did not occur in the resin portion of the semiconductor device and the reliability was not lowered until 1000 cycles.
Further, the thermal resistance is only about 10% higher than that of the conventional example in which the entire tab is made of a copper alloy, and is about 5% lower than the case where the entire tab is made of an iron-nickel alloy. Therefore, the reliability of the semiconductor device is less likely to decrease due to the heat problem.
【００１０】図２および図３は本発明の実施例の半導体
装置に使用する他のリードフレームのタブ部の平面図で
ある。2 and 3 are plan views of a tab portion of another lead frame used in the semiconductor device according to the embodiment of the present invention.
【００１１】図２に示したものではタブ２を橋体部１３
により４分割し、それぞれの開口部に応力緩衝板８Ａを
挿入し耐熱性フィルムに接着するようにしたものであ
る。このタブを用いた場合、半導体素子の大きさが１５
０ｍｍ2 以下であれば−６５℃〜１５０℃の温度サイク
ル試験において１０００サイクルまでクラックの発生は
抑えることが可能であり、かつ熱抵抗は従来例の５％増
加程度に抑えることが可能である。In the structure shown in FIG. 2, the tab 2 is attached to the bridge body portion 13
The stress buffer plate 8A is inserted into the respective openings and is bonded to the heat resistant film. When this tab is used, the size of the semiconductor device is 15
When it is 0 mm 2 or less, the generation of cracks can be suppressed up to 1000 cycles in the temperature cycle test of -65 ° C to 150 ° C, and the thermal resistance can be suppressed to about 5% of the conventional example.
【００１２】図３に示したものは、タブ２に櫛形状の開
口部を設け、櫛形状の応力緩衝板８Ｂを挿入した構造を
持つ。このタブを用いた半導体装置では、図１，図２に
示したものよりさらに熱抵抗を低くできる。さらに応力
緩衝板８Ｂが一体となっているため、図２に示したもの
よりも製造時のコストを低く抑えることができる。The structure shown in FIG. 3 has a structure in which a comb-shaped opening is provided in the tab 2 and a comb-shaped stress buffer plate 8B is inserted. In the semiconductor device using this tab, the thermal resistance can be made lower than that shown in FIGS. Further, since the stress buffer plate 8B is integrated, the manufacturing cost can be kept lower than that shown in FIG.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、銅又は銅
合金からなるリードフレームのタブに開口部を設け、こ
の開口部内に熱膨張係数が銅又は銅合金よりも小さい素
材からなる応力緩衝板を挿入し、タブと応力緩衝板の裏
面を耐熱性フィルムに接着し、この応力緩衝板上に半導
体素子を固着することにより、タブ部をスポット溶接等
でリードフレームに接続する従来のリードフレームに比
べ作業性が改善される。更に−６５℃〜１５０℃の温度
サイクル試験においても半導体素子や樹脂部にもクラッ
クの発生が抑制されるため、半導体装置の信頼性が向上
する。As described above, according to the present invention, an opening is provided in a tab of a lead frame made of copper or a copper alloy, and a stress buffer made of a material having a thermal expansion coefficient smaller than that of copper or a copper alloy is provided in the opening. A conventional lead frame in which a tab is connected to a lead frame by spot welding etc. by inserting a plate, adhering the tab and the back surface of the stress buffer plate to a heat resistant film, and fixing the semiconductor element on this stress buffer plate. Workability is improved compared to. Furthermore, even in the temperature cycle test of -65 ° C to 150 ° C, the generation of cracks is suppressed in the semiconductor element and the resin portion, so that the reliability of the semiconductor device is improved.
【図１】本発明の一実施例の平面図および断面図。FIG. 1 is a plan view and a cross-sectional view of an embodiment of the present invention.
【図２】本発明の実施例の半導体装置に使用する他のリ
ードフレームのダブ部の平面図。FIG. 2 is a plan view of a dub portion of another lead frame used in the semiconductor device of the embodiment of the invention.
【図３】本発明の実施例の半導体装置に使用する他のリ
ードフレームのタブ部の平面図。FIG. 3 is a plan view of a tab portion of another lead frame used in the semiconductor device of the embodiment of the invention.
【図４】従来の半導体装置の一例の一部切り欠き斜視
図。FIG. 4 is a partially cutaway perspective view of an example of a conventional semiconductor device.
１ 半導体装置 ２ タブ ３ 電極 ４ インナーリード ５ 金線 ６ アウターリード ７ 樹脂 ８，８Ａ，８Ｂ 応力緩衝板 ９ 銀ペースト １０ 接着剤 １１ 耐熱性フィルム １２ 開口部 １３ 橋体部 1 Semiconductor Device 2 Tab 3 Electrode 4 Inner Lead 5 Gold Wire 6 Outer Lead 7 Resin 8, 8A, 8B Stress Buffer Plate 9 Silver Paste 10 Adhesive 11 Heat Resistant Film 12 Opening 13 Bridge
Claims (2)
上に接着され開口部を有し銅または銅合金からなるタブ
と、前記開口部内で前記耐熱性フィルムに接着され前記
タブと同じ厚さの応力緩衝板と、少なくともこの応力緩
衝板に固着された半導体素子とを含むことを特徴とする
半導体装置。1. A heat-resistant film, a tab adhered on the heat-resistant film and made of copper or a copper alloy, and a tab having the same thickness as the tab adhered to the heat-resistant film in the opening. A semiconductor device comprising a stress buffer plate and at least a semiconductor element fixed to the stress buffer plate.
係数の小さい材料から構成されている請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein the stress buffer plate is made of a material having a smaller thermal expansion coefficient than copper or a copper alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5154055A JP2531441B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5154055A JP2531441B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0714975A true JPH0714975A (en) | 1995-01-17 |
| JP2531441B2 JP2531441B2 (en) | 1996-09-04 |
Family
ID=15575930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5154055A Expired - Lifetime JP2531441B2 (en) | 1993-06-25 | 1993-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2531441B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136179A (en) * | 1978-04-13 | 1979-10-23 | Nec Corp | Semiconductor device |
| JPH03191560A (en) * | 1989-12-20 | 1991-08-21 | Nec Corp | Resin-sealed semiconductor device |
-
1993
- 1993-06-25 JP JP5154055A patent/JP2531441B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54136179A (en) * | 1978-04-13 | 1979-10-23 | Nec Corp | Semiconductor device |
| JPH03191560A (en) * | 1989-12-20 | 1991-08-21 | Nec Corp | Resin-sealed semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2531441B2 (en) | 1996-09-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960507 |