JPH0714930Y2 - Circuit inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to an inspection apparatus for an electronic circuit using a programmable read-on memory (PROM) in which data of a predetermined pattern is stored in advance. Given test data of a predetermined pattern to the inspection circuit, from the state of the signal pattern output from the circuit under test at that time,
The present invention relates to a circuit inspection device that determines the quality of a circuit under test.

(Prior Art) When inspecting whether or not the operation of a digital circuit is normal, it is possible to give test data of a predetermined pattern to a digital circuit (circuit to be inspected) and examine output data from the circuit to be inspected corresponding to the test data. Be seen.

As such a conventional inspection device, an inspection device using a dedicated random circuit or an inspection device in which a dedicated interface is connected to a personal computer has been used.

(Problems to be solved by the invention) However, the inspection device using the dedicated random circuit has a problem that the wiring connection must be changed if the specifications of the circuit to be inspected are changed even a little. Although the inspection device with a dedicated interface can flexibly respond to changes in specifications by changing the program,
There is a problem that the device becomes large in size and inconvenient to handle.

The present invention has been made in view of these problems, and an object thereof is to realize a circuit inspection device having a simple configuration and easy to handle.

(Means for Solving the Problems) The present invention for solving the above problems is a programmable read-on in which output data from a circuit under test is given as a part of address information and data of a predetermined pattern is stored in advance. Memory (PROM), counter for giving address information to a part of the address input of this PROM, data register that captures data output from PROM and outputs that data to the circuit under test, and data output from PROM A clock signal generation circuit that controls the sending / stopping of the clock signal to be supplied to the counter according to one of the signals, an address given to the PROM, and "0", "1" of the data output from the PROM. And a reset circuit that initializes the counter and the data register.

(Operation) When a digital signal of a predetermined pattern is given from the PROM to the device under test, if the circuit under test operates normally,
The corresponding digital output signal is given to the PROM as a part of the address signal. When the signal from the circuit under test has a predetermined correct pattern, the counter counts up the clock from the clock signal generation circuit and sequentially advances to the next test.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 is a circuit to be inspected, which is composed of, for example, a digital circuit. 2 is a PROM given by the output data from the circuit under test 1 as a part of the address information,
Data of a pattern corresponding to the inspection specifications of the circuit under test 1 is stored in advance here.

Reference numeral 3 is a counter for giving address information to a part of the address input of the PROM 2, and 4 is a data register for taking in the data output from the PROM 2 and outputting the data to the circuit under test 1. Reference numeral 5 is a clock signal generation circuit in which the sending / stopping of a clock signal given to the counter 1 is controlled according to one signal Do of the data output from the PROM2. The oscillator 51, the clock from the oscillator 51 and the PROM2
And a signal Do from the input terminal and outputs the output to the counter 3.

Reference numeral 6 is a display circuit for displaying an address given to the PROM 2 and "0" and "1" of data output from the PROM 2, and 7 is a reset circuit for initializing the counter 3 and the data register 4.

The PROM2 activates the output Do and generates the clock signal only when the signal (part of the address signal) given to the PROM2 from the circuit under test 1 is correctly obtained for the data output to the circuit under test 1. The clock signal from the circuit 5 is applied to the counter 3.

The operation of the device configured as described above will be described below.

FIG. 2 is a time chart showing an example of the operation.

(A) shows a clock output from the clock signal generation circuit 5. This clock is counted by the counter 3 and constitutes an address signal of the PROM 2 together with the output Co from the circuit under test 1. (C) shows the address signal C given to the PROM2.

The PROM2 is provided with such an address signal, and consists of a test pattern stored at the corresponding address (d).
The test data d as shown in is read. This test data is temporarily held in the data register 4 and output to the circuit under test 1 as shown in (e).

The circuit under test 1 inputs this test data and outputs a signal Co having a predetermined pattern in accordance with the internal signal processing. The pattern of the output signal Co is such that if the operation of the circuit under test 1 is normal, a signal of a fixed pattern is output for the input test data e, but if the operation is abnormal, it is predetermined. Different patterns will be output.

The output signal Co from the circuit under test 1 constitutes the address signal of the PROM 2 together with the signal from the counter 3 and is given to the PROM 2.

Here, the content of the address signal given to the PROM 2 appears at the input section of the data register 4.

In this signal, information for deciding whether to proceed to the next inspection step is defined depending on whether the operation of the circuit under test 1 judged by a part of the applied address signal is normal or abnormal. Then, this information is sent to the clock signal generation circuit 5 as the output signal Do.

(B) shows the signal Do read from the PROM2.

When an abnormality is detected in the device under test 1, the signal Do from the PROM 2 becomes inactive as shown in (b), and the application of the clock signal to the counter 3 is stopped.

The display circuit 6 displays the address signal C of the PROM 2 and the state of the read data, for example, in comparison, and the abnormal item in the circuit under test 1 can be known from this display.

When the operation of the circuit under test 1 is normal, the output signal Do of the PROM 2 is active, the count value of the counter 3 is counted up, and the test data for carrying out the next test item is read out.

Such an operation is sequentially advanced to the last inspection item while the operation corresponding to each inspection item of the circuit under test 1 is normal.

When the final inspection item is reached, the output signal Do of the PROM 2 becomes inactive and the application of the clock signal to the counter 3 is stopped.

Prior to the next inspection, the reset circuit 7 clears the contents of the counter 3 and the data register 4.

When the inspection item or inspection content of the circuit under inspection 1 is changed or the specification is changed, the content of the PROM 2 is rewritten.

In the above description, the circuit under test 1 is assumed to be a digital circuit, but it may be an analog circuit. In this case, an A / D converter and a D / A converter are added to the input / output side of PROM2. Will be done.

Also, depending on the type of the circuit under test and the inspection items, the clock frequency of the clock signal generation circuit 5 can be made variable or PR
A plurality of writing patterns for the OM2 may be prepared with the same content.

(Effect of the Invention) As described in detail above, according to the present invention, it is possible to easily cope with various specifications of the circuit to be inspected by the configuration in which a simple circuit is added to the PROM as a center. An inspection device can be realized.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, and FIG.
The figure is a time chart showing an example of the operation. 1 ... Inspected circuit 2 ... PROM 3 ... Counter 4 ... Data register 5 ... Clock signal generating circuit 6 ... Display circuit 7 ... Reset circuit

Claims (1)

[Scope of utility model registration request] 1. A programmable read only memory (PROM) in which output data from a circuit under test is given as a part of address information and data of a predetermined pattern is stored in advance, and a part of address input of this PROM. To provide address information to the PROM, a data register that captures the data output from the PROM and outputs that data to the circuit under test, and a clock that is given to the counter in response to one of the data outputs from the PROM. A clock signal generation circuit for controlling signal transmission / stop, a display circuit for displaying an address given to a PROM and "0" and "1" of data output from the PROM, and an initial stage of the counter and the data register. It has a reset circuit that activates the PROM, and one of the signals output from the PROM is the data output to the circuit under test. On the other hand, the clock signal from the clock signal generation circuit is applied to the counter only when the signal to be supplied to the PROM from the circuit under test is correctly obtained, and the next inspection is sequentially advanced. Circuit inspection device.