JPH0714391A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the maximum peak current flowing through a power source line at the time of retrieval operations. CONSTITUTION:A memory matrix to be used is divided in the direction of a bit string into four blocks in total of divided memory matrix blocks such as a first divided memory matrix block consisting of word memories MW1a TO MW128a. Timings for time periods of retrieval operations are shifted by corresponding enabling timing signals SEa to SEb respectively. Thus, the peak current at the times of retrieval operations is dispersed and then a muximum peak current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention applies a discharge to a match line which has been precharged by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N. By detecting whether or not the bit pattern search word data input to the bit line is matched with the bit pattern storage word data stored in the word row of the memory matrix, a semiconductor memory device is obtained. In particular, by reducing the power consumption during the search operation and reducing the peak maximum current that flows in the power supply line, the load on the power supply line due to large current is reduced and the intensity of power supply noise is reduced. The present invention relates to a semiconductor memory device that can be used.

[0002]

2. Description of the Related Art In recent years, digital circuit technology has come to be used in various fields due to various design technologies such as improvement in the degree of integration and design of logic circuits to be incorporated. In such digital circuit technology, CPU (centra
l processing unit) and other data processing, etc., as well as semiconductor memory devices such as RAM (random access memory) and external memory devices such as hard disk devices. Advances have been made and are being used in various fields.

For example, in data processing in a database, various signal processing and image processing, a large amount of data is often handled during the processing, and the number of accesses to the data being processed tends to increase. For example,
In the data processing in the database, the data stored in the semiconductor memory device is frequently searched for. Therefore, in a digital processing device that performs such processing, the configuration and performance of the storage device itself and the method of using the storage device have a great influence on the performance of the entire digital processing device.

For this reason, the semiconductor memory device itself, which is provided with a data search function that is frequently performed in data processing in a database, has been widely used in recent years. This semiconductor memory device detects whether or not a precharged match line has been discharged by a matching circuit provided for each memory cell forming a memory matrix that stores data of a word length M with a bit length N. Thus, the matching result of the search word data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix is obtained. Hereinafter, such a semiconductor memory device will be referred to as a semiconductor memory device with a search function.

FIG. 12 is a circuit diagram of a memory matrix of the semiconductor memory device with a search function which has been conventionally used.

The memory matrix of the semiconductor memory device with search function shown in FIG. 12 stores data of bit length N and word number M. Therefore, the memory cells M11 to MMN that store 1-bit bit data are
A total of (M × N) pieces are used. Each of the memory cells M11 to MMN has a bit line pair Bn and (B
n bar), word line Wm, search enable line ENm
And the match line MCHm is input or output.

Further, such memory cells M11 to MMN
Are arranged in a matrix as shown in the drawing, and the word lines Wm, the search enable lines ENm, and the match lines MCHm are common to the N word lines in total. Further, the bit line pairs Bn and (Bn bar) are common to all of the same M bit strings.

FIG. 13 is a circuit diagram of a memory cell used in the conventional semiconductor memory device with a search function.

The memory cell shown in FIG. 13 is one of the memory cells M11 to MMN (hereinafter referred to as memory cell M) used in the semiconductor memory device with a search function shown in FIG. The memory cell M is composed of a total of two inverter gates I1 and I2 and a total of six N-channel MOS transistors T1 to T6.

First, the inverter gates I1 and I2
Are connected to each other so that one output is connected to the other output to hold bit data. Also, the N
The gates of the channel MOS transistors T1 and T2 are connected to the word line Wm. The N
The gates of the channel MOS transistors T4 and T6 are connected to the search enable line ENm. The gate of the N-channel MOS transistor T3 is connected to the input side of the inverter gate I1. The gate of the N-channel MOS transistor T5 is connected to the output of the inverter gate I1.

In the memory cell M as described above, first, when writing bit data, the word line Wm is written.
To the H state. As a result, the N-channel MOS
Both the transistors T1 and T2 are turned on. At the same time, by inputting bit data to be written from the bit line pair Bn and (Bn bar), this can be held by the inverter gates I1 and I2.

When reading the bit data held in the memory cell M, the word line Wm is set to the H state. As a result, the N-channel MOS transistors T1 and T2 are both turned on, and the held bit data can be read from the bit line pair Bn and (Bn bar).

Regarding the inverter gates I1 and I2 of the memory cell as shown in FIG. 13, the bit line Bn side, that is, the input of the inverter gate I1 is held in the H state, and the bit line ( Bn bar)
When the side, that is, the output of the inverter gate I1 is held in the L state, such a state is hereinafter referred to as "the H state (" 1 ") is held in the inverter gates I1 and I2". . This is because the bit lines Bn side of the inverter gates I1 and I2 is in the H state. On the other hand, regarding the inverter gates I1 and I2, when the bit line Bn side is held in the L state and the bit line (Bn bar) side is held in the H state, such a state will be referred to as “the inverter The L state (“0”) is held in the gates I1 and I2. ”

The bit line pair Bn and (Bn bar)
With respect to the above, the state in which the bit line Bn is in the H state and the bit line (Bn bar) is in the L state is described below.
This is called "the bit line pair Bn and (Bn bar) is in the H state". This is because the bit line Bn is in the H state for the bit line pair Bn and (Bn bar). On the other hand, regarding the bit line pair Bn and (Bn bar), when the bit line Bn is in the L state and the bit line (Bn bar) is in the H state, such a state will be referred to as "the bit line pair Bn." And (Bn bar) is L
"State".

In FIG. 13, the search for the bit data in the memory cell M, that is, the bit data held by the inverter gates I1 and I2, and the bit line pair Bn and (Bn bar) are input. The collation with the bit data to be performed is performed as follows.

That is, in the matching, first, the word line Wm and the search enable line ENm are left in the L state, and the match line MCHm is precharged to the H state. This precharge is based on the match line MCH
After connecting m to the power supply line, it is put in a floating state. By such precharge,
The logical state of the match line MCHm is the match line MCHm.
It is held in the H state by the electric charge accumulated in.

Against such precharge, on the other hand,
Bit data to be collated is input to the bit line pair Bn and (Bn bar). Upon inputting such bit data, the word line Wm remains in the L state and the search enable line ENm also remains in the L state, so the input bit data is held in the inverter gates I1 and I2. It does not affect the bit data to be stored or the precharged match line MCHm.

After the precharge is completed and bit data is input to the bit line pair Bn and (Bn bar), the search enable line ENm is set to the H state. By setting the search enable line ENm to the H state,
Both the N-channel MOS transistors T4 and T6 are turned on. Further, either one of the N-channel MOS transistors T3 or T5 is turned on according to the bit data held in the inverter gates I1 and I2. That is, when the bit data in the H state (“1”) is held by the inverter gates I1 and I2, the N channel MOS transistor T3 is turned on. On the other hand, when bit data in the L state (“0”) is held by these inverter gates I1 and I2, the N-channel MOS transistor T5 is turned on.

Therefore, when the search enable line ENm is in the H state in this way, the bit data held by the inverter gates I1 and I2 and the bit input by the bit line pair Bn and (Bn bar) are input. When the data matches the data, the H state precharged to the match line MCHm remains the H state.

For example, the inverter gates I1 and I
If the H state (“1”) is held in 2 and the H state is input from the bit line pair Bn and (Bn bar),
Since both the N-channel MOS transistors T3 and T4 are turned on and the match line MCHm is connected to the bit line Bn in the H state, the match line MCHm
Remains in the H state. Meanwhile, the inverter gate I
When the L state (“0”) is held in 1 and I2 and the L state is input from the bit line pair Bn and (Bn bar), the N channel MOS transistors T5 and T6 are Is also turned on, the match line MCHm is connected to the bit line (Bn bar) in the H state, and the match line MCHm remains in the H state.

On the other hand, the inverter gates I1 and I2
The bit data held by the bit line pair B
When the bit data input from n and (Bn bar) do not match, the match line MCHm is discharged and becomes L state.

For example, the inverter gates I1 and I
2 is held in the L state and the H state is input from the bit line pair Bn and (Bn bar), the N state is input.
The channel MOS transistors T5 and T6 are both turned on, the match line MCHm is connected to the bit line (Bn bar) in the L state, and the match line MCHm is connected.
Is discharged to the L state. Further, when the inverter gates I1 and I2 are kept in the H state and the bit line pair Bn and (Bn bar) is inputted in the L state, the N-channel MOS transistors T3 and T3.
4 are turned on, the match line MCHm is connected to the bit line Bn in the L state, and the match line MC
Hm is discharged to the L state.

According to the semiconductor memory device with a search function as described above, the search word data of the bit pattern input to the bit line is collated with the storage word data of the bit pattern stored in the word row of the memory matrix. Can be matched in parallel for many words.

For example, in the semiconductor memory device with a search function shown in FIG. 12, the bit line pair (B1- (B1 bar))
To (Bn- (Bn bar)) while inputting the search word data to all the search enable lines EN1 to ENM.
Are simultaneously set to the H state, the word data stored in all of the M words in total can be collated with the input search word data all at once.
In addition, this matching result is the match lines MCH1 to MCHm.
Can be obtained from

[0025]

However, in the above-described conventional semiconductor memory device with a search function, the match lines of the word lines that do not match the input search word data are discharged all at once. Because
The current required for such discharge was concentrated on the power supply line for a period of time. For this reason, a large current would flow through the power supply line almost instantaneously.

If the current flowing through the power supply line is concentrated for a period of time as described above, a large current will burden the power supply line. For example, there is a risk that the power supply line will generate heat due to Joule heat due to the large current, and will be damaged by disconnection or the like. Further, in order to prevent such damage, the cross-sectional area of the power supply line has conventionally been increased, but if the power supply line is thickened in this way, the degree of integration of the semiconductor memory device will be reduced. There is a problem. Further, if the current concentrates on the power supply line for a period of time, there is a problem that the intensity of power supply noise increases.

The present invention has been made to solve the above-mentioned conventional problems, and reduces the power consumption during a search operation in a semiconductor memory device with a search function and further reduces the peak maximum current flowing through a power supply line. By doing so, it is an object of the present invention to provide a semiconductor memory device capable of reducing the load on the power supply line due to a large current and reducing the intensity of power supply noise.

[0028]

SUMMARY OF THE INVENTION According to the present invention, a match line that has been precharged by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N has been precharged. A semiconductor that obtains a matching result between the search word data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix by detecting whether or not In the memory device, a plurality of divided memory matrix blocks of a total of P blocks each including a memory cell having a matching circuit, in which a bit line is provided for each bit string, are arranged in the bit string direction, so that the bit length is N and the number of words is M. Input the search enable signal and the memory matrix that is supposed to store the data of A plurality of search enable lines of at least (M × (P−1) +1), which are independent for each divided memory matrix block and independent for each word row of the memory matrix, and are precharged before execution of the search. Regarding the word whose matching result is not matched during the search, it is discharged in the matching circuit of the mismatched memory cell independently for each divided memory matrix block, and the word row of the memory matrix is also used. At least a total of (M × P) match lines for transmitting the collation match auxiliary signals corresponding to the precharge states, which are independent for each, and the divided memory matrix to which the search enable signal is input p-th The search enable signal transmitted through the search enable line corresponding to the m-th word of the block And a matching match signal obtained by delaying a signal obtained by a logical product of these two signals with the matching match auxiliary signal output from the match line corresponding to the word is the (p + 1) th In order to solve the above problems, the search enable signal is input to the m-th word of the divided memory matrix block to which the search enable signal is input through the detection enable line, and a search enable timing circuit that is input as the search enable signal. It has been achieved.

In the semiconductor memory device, the search enable timing circuits are cascade-connected,
From the connection point and the output of the last stage, the second to Pth
A total of (P-1) block delay circuits from which a second enable timing signal to a Pth enable timing signal used for timing control of generating each of the search enable signals generated next are derived;
From the search enable signal transmitted through the search enable line corresponding to the m-th word of the divided memory matrix block to which the p-th search enable signal is input, and the match line corresponding to the word From the logical product of these three signals, the collation matching auxiliary signal that is output and the p-th connection point of the cascaded block-by-block delay circuits or the p-th enable timing signal that is extracted from the final stage output , The (p +
1) The search enable signal generation circuit for generating a collation coincidence signal, which is input as the search enable signal to the m-th word of the divided memory matrix block to which the search enable signal is input at the search enable line By providing the above, the above-mentioned object is achieved.

Further, in the semiconductor memory device, for the word of the m-th word of the divided memory matrix block to which the search enable signal is input first, the search enable signal generating circuit corresponds to the word. From the logical product of these two signals of the matching match auxiliary signal output from the match line and the first enable timing signal derived from the first connection point of the cascaded block delay circuits. By generating the collation matching signal, the above-mentioned problem is achieved and the number of elements used is reduced.

In the semiconductor memory device, the search enable timing circuit is connected to the search enable line corresponding to the m-th word of the divided memory matrix block to which the p-th search enable signal is input. And a delay circuit for outputting the enable delay signal obtained by delaying the search enable signal, the enable delay signal output by the delay circuit for each word, and the enable delay signal. From the logical product of these two signals with the matching match auxiliary signal corresponding to the word corresponding to
And a search enable signal generating circuit for generating a collation coincidence signal, which is input to the m-th word to which the search enable signal is input at the search enable line. Due to
The above object has been achieved.

[0032]

The memory matrix used in the semiconductor memory device with the search function of the present invention is a plurality of divided memory matrixes of P blocks in total, each memory cell having a matching circuit in which a bit line is provided for each bit string. By arranging blocks in the bit string direction, data of a word length M with a bit length N is stored.
Therefore, it can be said that the memory matrix of the present invention is divided into P blocks in the bit string direction, for example.

For example, in the case of a memory matrix having a bit length of 64 bits and a word number of 128 words, for example, as in the embodiment described later, a total of 2 blocks are provided, and the division is a bit length of 16 bits and a word number of 128 words. The memory matrix blocks may be arranged and used in the bit string direction. Or, divide it into a total of 4
The block length is 8 bits and the number of words is 12
The divided memory matrix blocks of 8 words may be arranged in the bit string direction and used for the memory matrix.

In the present invention, the memory matrix is divided into a total of P blocks as described above, and the search word data and the stored word data are collated in each of the divided memory matrix blocks. I am trying to shift each other.

This is performed by inputting search enable signals whose timings are mutually shifted to the independent search enable lines provided for each of the divided memory matrix blocks. The search enable signals whose timings are shifted from each other in this way can be generated by the search enable timing circuit while using a delay circuit or the like as in the embodiment described later.

As described above, in the present invention, the memory matrix to be used is divided into the plurality of divided memory matrix blocks, and the divided memory matrix blocks are sequentially searched, so that the current due to the discharge due to the mismatch of the collation during the search is generated. The peak maximum current that is distributed and flows through the power supply line during the search operation is reduced. For example,
When the memory matrix is divided into a total of two divided memory matrix blocks, it is possible to reduce the peak maximum current by almost half. By reducing the peak maximum current in this manner, for example, power supply noise radiated from the power supply line is also reduced. Further, for example, when the peak maximum current is halved, the thickness of the power supply line used can be halved, and the integration degree of the semiconductor memory device can be improved.

Further, according to the present invention, when sequentially searching for each of the divided memory matrix blocks into which the memory matrix is divided as described above, a word row which is not matched by collation in the divided memory matrix block in the preceding stage. With respect to the above, the collation is not performed in the corresponding word row of the divided memory matrix block searched thereafter.

This means that, for a word row that has already become unmatched by the collation in the divided memory matrix block in the previous stage, even if the collation is matched in the divided memory matrix blocks to be collated after that, in the end, This is because the matching of the word lines is disagreement.

Further, with respect to the word row which is not matched by the collation in the divided memory matrix block searched in the preceding stage in this way, it is unnecessary because the collation in the divided memory matrix block thereafter is not performed. It is possible to prevent a power supply current from flowing due to a discharge due to a mismatch due to a proper comparison. With this, according to the present invention, not only the peak current flowing in the power supply current at the time of the search operation can be dispersed by sequentially searching for each of the divided memory matrix blocks, but also the mismatch of the matching already occurs at the matching of the divided memory matrix blocks in the subsequent stage. Since no matching is performed on the word line that has become, it is possible to further reduce the current consumption.

As described above, based on the collation result in the divided memory matrix block in the previous stage, whether or not the collation in each word row in the divided memory matrix block in the next stage is performed is performed in the word in the previous stage. The matching result for each row, that is, the matching match auxiliary signal for each word row in the previous stage is input to the search enable timing circuit, and
This is performed by generating the search enable signal of the next stage according to the input collation matching auxiliary signal of the previous stage.

The search enable timing circuit is provided with some signal delay circuit in order to search sequentially for each of the divided memory matrix blocks. However, the present invention does not specifically limit the search enable timing circuit such as the signal delay circuit.

For example, the delay circuit used in the enable timing circuit may be a block delay circuit provided for each of the divided memory matrix blocks as in the first embodiment described later. Alternatively, the second described later
As in the embodiment, a word-by-word delay circuit may be provided for each divided memory matrix block or for each word of each divided memory matrix block.

[0043]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of a main part of an embodiment of a semiconductor memory device with a search function to which the present invention is applied.

In the semiconductor memory device shown in FIG. 1, the bit length is 64 bits and the number of words is 128 words, which corresponds to the total (64 × 128 = 8).
192) It comprises a memory matrix with memory cells. The memory matrix is composed of a total of 4 divided memory matrix blocks. That is, the first divided memory matrix block to the fourth divided memory matrix block
It consists of divided memory maritox blocks.

These divided memory matrix blocks of a total of 4 blocks each have a bit length of 16 bits, and the number of words is 128 words.
The memory matrix is composed of 512 word memories MW1a to MW128a and MW1b to MW128 in total.
b, MW1c to MW128c and MW1d to MW128
It is composed by d. That is, the first divided memory matrix block includes the word memories MW1a ...
It is composed of MW128a. The second divided memory maritox block includes the word memory MW1.
b to MW128b. The third divided memory matrix block includes the word memory M.
It is composed of W1c to MW128c. The fourth divided memory maritox block is composed of the word memories MW1d to MW128d.

These word memories MW1a to MW128
a, MW1b to MW128b, MW1c to MW128c
And MW1d to MW128d are the same as in FIG.
The memory cell M having the above-described matching circuit shown in FIG.
16 are used in total. Therefore, the first divided memory matrix block to the fourth divided memory matrix block
Each of the divided memory matrix blocks has the same structure as the memory matrix shown in FIG. 12, and the bit length N of FIG. 12 is 16 bits and the number of words M is 128 words.

In the first divided memory matrix block to the fourth divided memory Maritox block, the word lines W1 to W128 respectively have
They are connected to each other and are common. All the search enable lines EN1 to EN128 of the first divided memory matrix block are connected to each other, and the search enable signal ENa is inputted. The search enable signal ENa is the same as the enable timing signal SEa.

Further, the matching match auxiliary signals MCH1a to MCH128a output from the match lines MCH1 to MCH128 of the word memories MW1a to MW128a of the first divided memory matrix block are ANDed.
It is input to one input of each of the logic gates G1a to G128a. The enable timing signal SE is applied to the other input of each of these AND logic gates.
b is entered.

These AND logic gates G1a to G128
The output of a is the search enable signals EN1b to EN128.
b, each of the word memories MW1b to MW128 of the second divided memory matrix block.
Respective search enable lines EN1 to EN128 of b
To the search enable signals EN1b to EN128b. Also, these search enable signals EN
Each of 1b to EN128b is an AND logic gate G1.
It is also input to each one input of b to G128b.

In the second divided memory matrix block, the word memories MW1b to MW respectively.
128b match lines MCH1-MCH128
The collation matching auxiliary signals MCH1b to MC output from
H128b is the AND logic gate G1b, respectively.
~ G128b is input to each one input. The enable timing signal SEc is input to one input of each of the AND logic gates G1b to G128b.

Further, these AND logic gates G1b to G1
Search enable signals EN1c to EN1 output by 28b
28c is input to the search enable lines EN1 to EN128 of the word memories MW1c to MW128c of the third divided memory matrix block. Also, these search enable signals EN1c to EN1
28c are AND logic gates G1c to G12, respectively.
It is also input to one input of 8c.

In the third divided memory matrix block, the respective word memories MW1c ...
Matching match auxiliary signals MCH1c to MCH12 output from the match lines MCH1 to MCH128 of the MW128c.
8c is input to one input of each of the AND logic gates G1c to G128c. These AND
The enable timing signal SEd is also input to one input of each of the logic gates G1c to G128c.

Further, these AND logic gates G1c to G1
28c Search enable signal EN1d output by each
To EN128d to the search enable lines EN1 to EN128 of the word memories MW1d to MW128d of the fourth divided memory matrix block,
The search enable signals EN1d to EN128d are input, respectively. Also, these search enable signals E
N1a to EN128d are also input to respective one inputs of AND logic gates G1d to G128d.

In the fourth divided memory matrix block, each of the word memories MW1d to MW
128d Each of the match lines MCH1 to MCH12
Collation matching auxiliary signals MCH1d to MCH output from
128d are the AND logic gates G1d ...
It is input to one input of G128d.

Incidentally, these AND logic gates G1d to G
128d is the final matching result of the semiconductor memory device with search function of the first embodiment, that is, the matching match signal
1 to MC128 are output.

Further, in this embodiment, the search is started according to the input enable timing signal SEa. The enable timing signal SEa is input to the block delay circuit Ta.

The block delay circuit Ta delays the enable timing signal SEa for a predetermined time and outputs it as an enable timing signal SEb. The enable timing signal SEb is supplied to the AND logic gate G1.
It is inputted to each one input of a to G128a and also inputted to the block delay circuit Db.

The block delay circuit Db delays the input enable timing signal SEb by a predetermined time and outputs it as the enable timing signal SEc. The enable timing signal SEc is A
Each of the ND logic gates G1b to G128b is inputted to one input of the ND logic gates G1b to G128b, and the block delay circuit D
It is also entered in c.

The block delay circuit Dc delays the input enable timing signal SEc by a predetermined time and outputs it as the enable timing signal SEd.

The block delay circuits Ta to Tc are provided.
The block delay circuit Tx (hereinafter referred to as the block delay circuit) is composed of a total of six inverter gates B as shown in FIG. That is, the block delay circuit Tx obtains a predetermined delay time by the signal delay when a signal is transmitted through the cascade-connected buffer gates B. The enable timing signal SE (x + 1) output from the block delay circuit Tx is obtained by delaying the input enable timing signal SEx by such a predetermined delay time.

In the first embodiment, the search enable timing circuit of the present invention mainly comprises the block delay circuits Da to Dc and the AND logic gate G1.
a to G128a, G1b to G128b, G1c to G12
8c and G1d to G128d, and wirings related thereto.

FIG. 3 is a time chart showing the operation of the first embodiment.

In the time chart of FIG. 3, the enable timing signals SEa to SEb, the search enable signals ENma to ENmd, the matching match auxiliary signals MCHma to MCHmd, and the matching match signal MCm are shown. There is. In the code names of these signals, "m" indicates that the signal is in the word row of the m-th row.

In this time chart, in the m-th word row, when the stored word data of the bit pattern stored in the word row and the search word data of the bit pattern input to the bit line match. It is shown. The operation of this embodiment will be described below based on this time chart and according to the elapsed time.

First, the enable timing signal SE
When a rises, all the word memories MW1a to MW128a of the first divided memory matrix block.
Will be searched. That is, a search is also performed in the word memory MWma, which is the same as the enable timing signal SEa and to which the search enable signal ENma shown in this time chart is input.

On the other hand, the enable timing signal SE
The rising edge of a is delayed by the block delay circuit Da, and the enable timing signal SEb rises after a predetermined time. At the rising edge of the enable timing signal SEb, the matching in the word memory MWma is completed, and the matching matching auxiliary signal MCHma according to this is completed.
Has been confirmed.

The AND logic gate Gma is connected to the collation match auxiliary signal MCHma and the enable timing signal SE.
b is input and the logical product of these signals is output as the search enable signal ENmb. The collation matching auxiliary signal M
CHma is in the H state, that is, the word memory MW
If the result of collation at ma is a collation match, the search enable signal ENmb output from the AND logic gate Gma rises when the enable timing signal SEb rises.

When the search enable signal ENmb rises, the word memory MWmb is searched for the second divided memory matrix block. Each of the word memories MW1b to MW of the second divided memory matrix block
W128b is searched for in each of the word memories MW1a to MW1a of the first divided memory matrix block.
It is performed only for the word when the matching result of the MW128a is a matching match.

In the word memory MWmb of the second divided memory matrix block, when the search enable signal ENmb rises and a search is performed, the comparison is performed after a predetermined time, that is, before the enable timing signal SEc rises. It is output as a match auxiliary signal MCHmb. It is a verification match, and the verification match auxiliary signal MCH
When mb is in the H state, the enable timing signal SE
When c rises, the search enable signal ENmc output from the AND logic gate Gmb also rises.

When the search enable signal ENmc rises, the word memory MWmc of the third divided memory matrix block is also searched. If the search result of the search is a collation match, the enable timing signal ENmd is obtained. In accordance with the rising edge of, the word memory MWmd of the fourth divided memory matrix block is also searched. The final search result of the word row m is output from the AND logic gate Gmd as a collation matching signal MCm.

FIG. 4 is a time chart showing the operation at the time of collation disagreement in this embodiment.

In FIG. 4, in a certain word row m of a divided memory matrix block x (x is any of a to d), collation in the word memory MWmx (m is the word row of the word). A time chart is shown when the result is collation disagreement.

In this time chart, the search enable signal EN input to the word memory MWmx.
When mx rises, the word memory MW1b is searched. If the search result shows a mismatch in matching, the matching matching auxiliary signal MCHmx output from the word memory MWmx is discharged after a predetermined time and goes into the L state.

When the matching match auxiliary signal MCHmx is in the L state, the matching match auxiliary signal MCHmx, the search enable signal EMmx, and the enable timing signal SE.
The search enable signal ENm (x + 1) output from the AND logic gate Gmx receiving (x + 1) also remains in the L state. Therefore, the collation matching auxiliary signal MCHm (x + 1) output from the word memory MWm (x + 1) at the next stage of the word memory MWmx is not discharged.

FIG. 5 is a time chart when a collation disagreement occurs in a certain word row of the fourth divided memory matrix block of the final block of the first embodiment.

In the time chart of FIG. 5, a search is performed in the word memory MWmd of the mth word row of the fourth divided memory matrix block, and
This is when the search results do not match.

In the word memory MWmd, when the input search enable signal ENmd is in the H state and the search is started and the search does not match the collation, after a predetermined time,
The collation matching auxiliary signal MCHmd output from the word memory MWmd is discharged to be in the L state. When the matching match auxiliary signal MCHmd is in the L state, the matching match signal MCm output from the AND logic gate Gmd is also in the L state. Therefore, at the timing after a predetermined time elapses from the rise of the search enable signal ENmd, the collation matching signal M
By determining the logical state of Cm, such collation inconsistency can be confirmed.

In this embodiment, the AND logic gates G1b to G128b and G1c to G128c are
The 3-input AND logic gate is a search operation performed in the corresponding word memory (that is, the matching result in the preceding stage in the word memory is matching match), and the search result in the word memory is matching match. And to detect that the corresponding enable timing signal SEx rises.

In comparison with this, the AND logic gate G
1a to G128a are 2-input AND logic gates. This is because all the word memories MW1a to MW128 of the first divided memory matrix block.
This is because the search operation is always performed for a because the first divided memory matrix block is in the first stage. Therefore, the MW1a to MW128a are subjected to a search operation by a logical product of the AND logic gates G1a to G128a and the enable timing signal used as the search enable signal in the first memory matrix block, for example. This is because there is no need to judge whether it has been performed. As described above, in the present embodiment, the A which may be a 3-input AND logic gate is used.
By using the ND logic gates G1a to G128a as 2-input AND logic gates, the number of required elements can be reduced.

On the other hand, the AND logic gates G1d to G1
28d is also a 2-input AND logic gate. This is because the collation matching signals MC1 to MC128 are
This is because it is not necessary to delay by some enable timing signal. That is, it is only necessary to calculate respective logical products of the search enable signals EN1c to EN128c and the collation matching auxiliary signals MCH1d to MCH128d.

As described above, according to the first embodiment, by shifting the timing of the search operation in the first divided memory matrix block to the fourth divided memory matrix block, the current flows to the power supply line during the search operation. The peak current can be dispersed. Particularly, in the present embodiment, in the word memory in which the collation does not match,
The collation in the word memory after this is not performed. As a result, it is possible to reduce the flow of the power supply current due to the discharge of the match line, which is caused at the time of collation mismatch at the time of searching in the word memory, and the power consumption is reduced.

FIG. 6 is a circuit diagram of a main portion of a second embodiment of a semiconductor memory device with a search function to which the present invention is applied.

In FIG. 6, the semiconductor memory device has a bit length of 64 bits and a word number of 128 words as in the case of the first embodiment, and the corresponding total (64 × 128 =). 8192) comprises a memory matrix of memory cells. Further, the memory matrix is composed of a total of four blocks, namely, a first divided memory matrix block to a fourth divided memory matrix block.

Also in the second embodiment, these four divided memory matrix blocks are respectively
The bit length is 16 bits and the number of words is 128 words. The first divided memory matrix block to the fourth divided memory matrix block of the second embodiment have the same configuration as that of the first embodiment.
Each of the divided memory matrix blocks has a structure similar to that of the memory matrix shown in FIG. 7, and is formed by using the memory cell M shown in FIG. The word lines W1 to W128 of the first divided memory matrix block to the fourth divided memory matrix block are connected to each other in common.

In the second embodiment, the search enable line EN of the first divided memory matrix block is used.
1 to EN128 are connected to each other, and the search enable signal EN is input. Further, the search enable signal EN
Are input to the respective one inputs of the AND logic gates H1a to H128a, and the word-by-word delay circuits D1a to D, respectively.
It is input via 128a.

Also, the word memories MW1a to MW12.
8a Matching match auxiliary signals MCH1a to MCH output from the match lines MCH1 to MCH128, respectively.
CH128a is the AND logic gate H1
It is input to one input of a to H128a. The AND logic gates H1a to H128a obtain the logical product of the enable delay signals END1a to END128a output from the word-by-word delay circuits D1a to D128a and the collation matching auxiliary signals MCH1a to MCH128a, respectively. EN1b ~
Each of the word memories MW is set as EN128b.
Output from 1b to MW128b.

Also in the subsequent second to fourth divided memory matrix blocks, the word delay circuits D1b to D128b and D1c to D128c and the AND logic gates H1b to H are also provided.
128b and H1c to H128c are used to perform the same operation as the first divided memory matrix block. On the output side of the fourth divided memory matrix block, the word-by-word delay circuit as described above is not provided, and the search enable signals EN1d to EN128d input to the word memories MW1d to MW128d are input.
And the collation matching auxiliary signals MCH1d to MCH1 output from the word memories MW1d.
28d is the logical product of the AND logic gates H
The matching match signals MC1 to MC128 are output as the overall search result, which are obtained from 1d to H128d.

FIG. 7 is a circuit diagram focusing on one of the word memories used in the second embodiment.

As shown in FIG. 7, the search enable signal ENmx is input to the search enable line ENm of any one of the word memories MWmx (x is any of a to c) of the second embodiment. ing. Further, one word-by-word delay circuit Dmx is provided for each of the word memories MWmx, and the search enable signal ENmx is inputted. The word-by-word delay circuit Dmx outputs the enable delay signal ENDnx by using the search enable signal ENnx delayed by a predetermined time.

On the other hand, the word memory MWmx outputs the collation matching auxiliary signal MCHmx from the match line MCHm.

Further, 1 is applied to one of the word memories MWmx.
Two AND logic gates Hnx are provided. The AND
The logic gate Hmx obtains a logical product of the enable delay signal ENDmx and the collation matching auxiliary signal MCHmx, and outputs the result as a search enable signal ENm (x + 1). The search enable signal ENm (x + 1) is input to the search enable line ENm of the word memory MWm (x + 1) of the same word row in the next stage.

FIG. 8 is a circuit diagram of the word-by-word delay circuit of the second embodiment.

As shown in FIG. 8, the word delay circuits D1a to D128a, D1b to D128b and D are provided.
1c to D128c (hereinafter collectively referred to as Dmx) has a total of 6
Each buffer gate B is configured. That is, the word delay circuit Dmx uses the signal delay when the search enable signal ENmx is transmitted to the buffer gates B connected in cascade, and the search enable signal ENmx is used.
Of the enable delay signal EN delayed by a predetermined time
This is to generate and output Dmx.

In the second embodiment, the search enable timing circuit of the present invention is mainly composed of the word delay circuits D1a to D128a and D1b to D12.
8b and D1c to D128c and the AND logic gates H1a to H128a, H1b to H128b, H1c to H.
128c and H1d to H128d, and wirings related thereto.

FIG. 9 is a time chart showing the operation of the second embodiment.

In the time chart of FIG. 9, attention is paid to the word memory MWmx of the second embodiment and the word memory MWm (x + 1) of the next stage of the word memory. In this time chart, regarding the word memories MWmx and MWm (x + 1), the enable signal ENmx and the collation matching auxiliary signal MCH are provided.
mx, the enable delay signal ENDmx, and the enable signal ENm (x + 1).

In the time chart of FIG. 9, first, when the enable signal ENmx rises, a total of 16 memory cells Mm1 to Mm in the word memory MWmx.
The matching circuits and the like built in each m operate to perform the search operation for the word memory MWmx. The search result is
It is output as the matching / matching auxiliary signal MCHmx indicating matching or mismatching. It should be noted that in this time chart, the matching match is indicated by a dashed-dotted line, and the matching mismatch is indicated by a broken line.

On the other hand, the enable signal ENmx is delayed by the word delay circuit Dmx for a predetermined time and output as the enable delay signal ENDmx. The delay time corresponds to the time until the search operation performed in the word memory MWmx is completed, and is slightly longer than the time required for the search operation. Therefore, at the rising edge of the enable delay signal ENDmx, it is judged whether the matching match auxiliary signal MCHmx is matching match or mismatch, and based on this, the enable signal ENm (x + 1) is set to It is generated by the AND logic gate Hmx.

As described above, also in the second embodiment, like the first embodiment, the timing of the search operation performed in each of the first divided memory matrix block to the fourth divided memory matrix block is shifted. so,
It is possible to disperse the peak current flowing through the power supply line during the search operation. Also in the second embodiment, whether or not to execute the search in each word row after the second divided memory matrix block is based on the search result of the preceding stage. Therefore, when the collation mismatch occurs in the word memory in the previous stage, the word memory in the corresponding word row in the next stage is not searched, and it is possible to reduce the overall power consumption.

When the first embodiment and the second embodiment are compared, the delay circuit portion, that is, the block delay circuit Dx portion in the first embodiment, and the second embodiment in the second embodiment are compared. The part of the word delay circuit Dmx, the part of the logic gate Gmx of the first and second embodiments, and the circuits in the vicinity thereof are partly different. For example, in the first embodiment, a small number of delay circuits for each block are centrally provided as the block delay circuits Dx, which is excellent in this respect. On the other hand, in the second embodiment, since the word delay circuit Dmx is arranged near each word memory MWmx, the wiring related to the word delay circuit Dmx is shortened, which is excellent in this respect. These first and second embodiments may be selectively determined according to the circuit state to be provided.

FIG. 10 is a graph of the power supply current during the search operation in the conventional semiconductor memory device with the search function. On the other hand, FIG. 11 is a graph showing the power supply current during the search operation in the first embodiment or the second embodiment.

First, in the prior art, as shown in FIG. 10, the power supply current during the search operation is concentrated at time t ₁ . On the other hand, in the first and second embodiments, the peak currents during the search operation are dispersed as shown in FIG. That is, the time t in FIG.
Is as shown in ₂ ~ t ₅ dispersion, the peak maximum current is smaller than conventionally.

In particular, the time t ₂ corresponds to the search operation in the first divided memory matrix block, and the time t ₃ corresponds to the search operation in the second divided memory matrix block. , The time t
₄ corresponds to the search operation in the third divided memory matrix block, and the time t ₅ corresponds to the fourth operation.
This corresponds to the search operation in the divided memory matrix block.

As described above, when the search operation in the corresponding preceding stage of each word memory is unmatched, the search in the subsequent stage of the word memory is not performed.
The power consumption is reduced. This point is shown in FIG. 11 in which the peak current gradually decreases with respect to the broken line in accordance with the time t ₂ to t ₅ and the elapsed time.

Thus, as is clear from comparison between FIGS. 10 and 11, according to the first embodiment or the second embodiment, the peak flowing in the power supply line during the search operation is higher than in the conventional case. The maximum current can be reduced to almost 1/4. Further, in the first and second embodiments, the total power consumption during the search operation can be reduced to 1/4 or less of the conventional case as compared with the conventional case.

[0107]

As described above, according to the present invention, the power consumption during the search operation in the semiconductor memory device with the search function is reduced, and the peak maximum current flowing through the power supply line is further reduced. It is possible to obtain an excellent effect that the load on the power supply line due to the current can be reduced and the intensity of the power supply noise can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a first embodiment of a semiconductor memory device with a search function to which the present invention is applied.

FIG. 2 is a circuit diagram of a delay circuit for each block used in the first embodiment.

FIG. 3 is a time chart showing an operation at the time of matching and matching in the first embodiment.

FIG. 4 is a time chart showing the operation when the collation does not match in the first embodiment.

FIG. 5 is the fourth stage at the final stage when the collation does not match in the first embodiment.
Time chart showing the operation of the divided memory matrix block

FIG. 6 is a circuit diagram of a main part of a second embodiment of a semiconductor memory device with a search function to which the present invention is applied.

FIG. 7 is a circuit diagram focusing on one word memory according to the second embodiment.

FIG. 8 is a circuit diagram of a word-by-word delay circuit used in the second embodiment.

FIG. 9 is a time chart showing the operation of the second embodiment.

FIG. 10 is a graph of a power supply current during a search operation in a conventional semiconductor memory device with a search function.

FIG. 11 is a graph showing a power supply current during a search operation in the first embodiment or the second embodiment.

FIG. 12 is a circuit diagram of a memory matrix of a conventional semiconductor memory device with a search function.

FIG. 13 is a circuit diagram of a memory cell used in the memory matrix of the conventional semiconductor memory device with a search function.

[Explanation of symbols]

MWmx, MW1a to MW128a, MW1b to MW12
8b, MW1c to MW128c, MW1d to MW128
d ... Word memory G1a to G128a, G1b to G128b, G1c to G
128c, G1d to G128d, H1a to H128a,
H1b to H128b, H1c to H128c, H1d to H
128d ... AND logic gate Da to Dc ... Block delay circuit D1a to D128a, D1b to D128b, D1c to D
128c ... Delay circuit for each word M11 to MMN ... Memory cells T1 to T6 ... N channel MOS transistors I1, I2 ... Inverter gate B ... Buffer gate Bn (Bn bar), B1 to Bn, (B1 bar) to (Bn)
Bar) ... Bit lines Wm, W1 to W128 to Wm (or W1 to WN to W)
128) ... Word lines ENn, EN1 to ENN ... Search enable lines (or search enable signals) ENmx ... Search enable signals ENDmx, END1a to END128a, END1b.
END128b, END1c to END128c, END
1d ~END128d ... enable delay signal SEa ~SEd ... enable timing signal MCHm, MCH1~MCHM ... match line (or collation coincidence holding signal) MCHma ... collation coincidence auxiliary signal MC1～MC128 ... collation coincidence output (or collation coincidence signal) t ₁ ~ T ₅ ... time

Claims (4)

[Claims] 1. It is detected whether or not discharge by a matching circuit provided for each memory cell forming a memory matrix for storing data of a word length M with a bit length N is applied to a precharged match line. In this way, in the semiconductor memory device that obtains the collation result between the search word data of the bit pattern input to the bit line and the stored word data of the bit pattern stored in the word row of the memory matrix, By arranging a plurality of divided memory matrix blocks of a total of P blocks, each of which is provided with a bit line and has a memory cell having a matching circuit, in the bit column direction, data of a word length M and a word length M is stored. The divided memory matrix for inputting a memory matrix and a search enable signal Independently for each block, also independent for each word line of the memory matrix, a total of at least (M × (P-
1) +1) A plurality of search enable lines are precharged before the search is executed, and a word for which the matching result during searching does not match is discharged by the matching circuit of the mismatched memory cell. Will be
At least a total of (M × P) plurality of match lines, which are independent for each of the divided memory matrix blocks and independent for each word row of the memory matrix, and which transmit the matching match auxiliary signal corresponding to the precharge state. The search enable signal transmitted through the search enable line corresponding to the mth word of the divided memory matrix block to which the p-th search enable signal is input, and the match corresponding to the word The collation coincidence signal obtained by delaying the signal obtained by the logical product of these two signals with the collation coincidence auxiliary signal output from the line is detected at the (p + 1) th time by the search enable signal. The search enable signal is input to the mth word of the divided memory matrix block input by the enable line. The semiconductor memory device characterized by comprising a search enable timing circuit. 2. The search enable timing circuit according to claim 1, wherein the search enable timing circuits are cascade-connected, and from the connection point and the final stage output,
The second enable timing signal to the Pth enable timing signal used for timing control at the time of generating each of the second to Pth generated search enable signals are sequentially extracted, (P-1) in total. Each block delay circuit, the search enable signal transmitted through the search enable line corresponding to the m-th word of the divided memory matrix block to which the p-th search enable signal is input, Between the matching match auxiliary signal output from the match line corresponding to a word and the p-th connection point of the cascaded block delay circuits or the p-th enable timing signal extracted from the final stage output, From the logical product of these three signals, the (p
Search enable signal generation circuit for generating a collation coincidence signal, which is input to the m-th word of the divided memory matrix block to which the search enable signal is input at the (1) th) search enable line. A semiconductor memory device comprising: 3. The search enable signal generation circuit according to claim 2, wherein the search enable signal generation circuit corresponds to the mth word of the divided memory matrix block to which the search enable signal is input first. From the logical product of these two signals, the matching match auxiliary signal output from the match line and the first enable timing signal extracted from the first connection point of the block delay circuits connected in cascade, A semiconductor memory device characterized in that it generates a collation matching signal. 4. The search enable timing circuit according to claim 1, wherein the search enable line corresponds to the m-th word of the divided memory matrix block to which the p-th search enable signal is input. The word enable delay circuit that inputs the search enable signal that is transmitted and outputs the enable delay signal that is a delay of the search enable signal, the enable delay signal that the word delay circuit outputs, and the enable delay signal From the logical product of these two signals with the matching match auxiliary signal corresponding to the corresponding word, the (p + 1) th search enable signal is input to the m-th word. A search enable signal generating circuit for generating a collation matching signal, which is input to the eye as the search enable signal. A semiconductor memory device provided with.