JPH07143522A - Head mount video display device - Google Patents

Abstract

PURPOSE:To realize cost reduction by reducing memories by half by enabling address correction for right and left eyes by alternately reading one address correction table from opposite directions for each frame while utilizing the right and left symmetry of right and left address correction tables. CONSTITUTION:In a video signal processor 1, the address correction tables of 17 bits are read out of an address correction table 20 from the opposite directions for each field, based on the read-out correction table, a frame memory 12 performs address correction to video signals SL and SR for left and right eyes to be displayed, and the address corrected video signals for left and right eyes are alternately outputted to LCD 2L and 2R while being switched for each field by a switch 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head-mounted image display device capable of observing an image by guiding the image to the left and right eyes of an observer.

[0002]

2. Description of the Related Art A conventional example of a head-mounted image display device is shown in FIG. In this conventional example, the left and right video display elements (the same signal and the left and right video signals for stereoscopic viewing, respectively) that display the input left-eye video signal and right-eye video signal may be displayed. The left-eye video signal and the right-eye video signal displayed on the LCD) 51L, 51R are projected on the left and right eyes 54L, 54R of the observer by the eccentric concave optical system including the lenses 52L, 52R and the concave mirrors 53L, 53R, respectively. I am trying.

In this conventional example, since the decentered concave optical system is used, the viewing angle can be increased. However, when the viewing angle is increased, the image distortion becomes large. Therefore, the distortion is corrected by the address correction table. I am trying to correct it.

[0004]

In the above-mentioned conventional example, since the distortion of the image for the left eye and the distortion of the image for the right eye are opposite in the left-right direction (symmetrical), the left-eye image and the right-eye image are distorted. Two address correction tables are needed. As a result, the memory capacity for storing the address correction table increases, which inevitably increases the cost.

The present invention has been made in view of the above problems, and utilizes the left-right symmetry of the left-right address correction table to alternately read one address correction table for each frame from the opposite direction. Accordingly, it is an object of the present invention to provide a head-mounted image display device capable of address correction equivalent to the case of using two address correction tables and realizing a cost reduction by halving the memory.

[0006]

To this end, the present invention provides an address correction table, a correction table reading means for reading out the address correction table for each field from the reverse direction, and a display based on the read correction table. And a field switching output means for switching the address-corrected left-eye video signal and right-eye video signal for each field and outputting the corrected left-eye video signal and right-eye video signal. A video signal processing device, left and right video display devices for respectively displaying a left eye video signal and a right eye video signal input from the video signal processing device, and a left eye video displayed on these video display devices And an eccentric concave optical system for projecting the signal and the image signal for the right eye onto the left and right eyes of the observer, respectively.

[0007]

According to the present invention, when the left-eye video signal and the right-eye video signal to be displayed are input to the video signal processing device, the correction data reading means reads the address correction table for each field from the reverse direction. (For example, the odd field is read from left to right and the even field is read from right to left.) The address correction unit addresses the left-eye video signal and right-eye video signal to be displayed based on the read correction table. Since the corrected and field switching output means switches the address-corrected left-eye video signal and right-eye video signal for each field and alternately outputs them to the left and right video display elements, two address correction tables for left and right are used. The same address correction as in the conventional example can be performed, and the cost can be reduced by halving the memory.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a first embodiment of a head-mounted image display device of the present invention, and FIG. 2 is a diagram showing details of a video signal processing device of the first embodiment.

First, a schematic structure will be described with reference to FIG. In FIG. 1, a left-eye video signal S _L input from a video camera (not shown) (alternatively, a video signal supply device; a video reproduction device or the like, or television broadcasting may be used).
And a video signal processing device 1 which corrects the right-eye video signal S _R by address and outputs the right and left alternately.
Left and right video display elements (LCD) 2 for displaying the left-eye video signal S _L and the right-eye video signal S _R input from
L and 2R, and lenses 3L and 3 that are eccentrically arranged with respect to each other.
R and a eccentric concave optical system composed of concave mirrors 4L, 4R, and the left eye image signal S _L and the right eye image signal S _R displayed on the LCDs 2L, 2R are observed by the eccentric concave optical system. The images are projected on the eyes 5L and 5R, respectively. The left-eye video signal S _L and the right-eye video signal S _R may use the same signal or may use different signals for left and right for stereoscopic viewing.

Next, as described above, L is applied to each of the left and right eyeballs.
A control system for projecting an image displayed on a CD to observe the image will be described with reference to FIG. The video signal processing apparatus 1 shown in FIG. 2 is input with a composite video signal including each signal for performing video observation from the outside. This video signal includes a left-eye video signal S _L , a right-eye video signal S _R, and a synchronization signal. For example, an odd field is a right-eye video signal S _R and an even field is a left-eye video signal S _L. (Even-numbered field may be right-eye video signal S _R and odd-numbered field may be left-eye video signal S _L ). The left and right eye video signals S _L and S _R are A /
The data is A / D converted by the D converter 11 and serially written in the frame memory 12 as 8-bit data.
On the other hand, the sync signal is separated by the sync signal separation circuit 13 to become three signals FD, HBRK and VBRK.

The signal FD is a signal indicating whether it is an odd field or an even field, and is in a "high" state in an odd field and in a "low" state in an even field. The signal FD is input to the register 14, the switch 15, and the up / down input terminals of the first counter 16. The signals HBRK and VBRK are signals indicating the horizontal display period and the vertical display period, respectively, and the signal VBRK is the load input terminal and the second input terminal of the first counter 16.
The signal is input to the clear input terminal of the counter 17 and the signal HBRK is input.
Is input to the clock input terminal of the second counter 17 and the input terminal of the AND gate 18. Examples of the waveforms of these three signals are shown in the time charts of FIGS.

The first counter 16 is a 9-bit binary up / down counter with a preset function, which is preset to 0 in the case of an odd field and is up-counted, and 1FF (16 in the case of an even field.
It is preset to "advanced" and down-counted. The first counter 16 has the above-mentioned signals VBRK and FD.
In addition, the 9-bit preset data from the register 14 is input to the preset data input terminal, and the clock signal CLK (an example of the waveform is shown in FIG. 3D) from the oscillator 19 is input to the signal HBRK. An output signal of an AND gate 18 that performs an AND operation with and is input to the clock input terminal, and the address correction table 20 outputs a signal instructing the lower 9-bit address forming the 17-bit address correction table.

On the other hand, the second counter 17 is an 8-bit binary counter with a clear function, and the input signal HBRK is applied regardless of whether it is an odd field or an even field.
Is counted at the falling edge of the address correction table 2 and cleared at the falling edge of the signal VBRK.
A signal indicating 0 to the upper 8 bits of the address correction table of 17 bits is output to 0.

In the address correction table, as shown in FIG. 4, for example, one field is 512 horizontal × 24 vertical.
It consists of three, so one field is 512 horizontal ×
Frame memory 12 sampled at 243 vertically
In this case, 17-bit address correction data as shown in FIG. 4 is required. Each numerical value in FIG. 4 indicates the address (hexadecimal notation) of the address correction table, and the address correction table has the data of the address indicated by the first counter 16 and the second counter 17, that is, the correction address consisting of 17 bits. is doing. Therefore, the left-eye video signal S _L and the right-eye video signal S _R written in the frame memory 12
Is randomly read according to the value of the correction address and is input to the switch 15 via the D / A converter 21. In this embodiment, writing of the video signal is serial and reading is random, but writing may be random and reading may be serial.

The switch 15 has its state inverted according to the input signal FD, and in the case of an odd field, the L for the right eye is used.
When the CD drive circuit 22R is selected, the LCD drive circuit 22L for the left eye is selected in the even field, and finally, the image for the right eye is displayed on the LCD 2R for the right eye in the odd field, and the image for the even field is displayed. LCD for left eye
The image for the left eye is displayed on 2R.

By the way, in the above, the first counter 1
6 is counted by the clock signal CLK from the oscillator 19. That is, the oscillation frequency of the oscillator 19 is set so that the clock signal CLK has 512 pulses in one horizontal period, and the AND gate 18 outputs the AND operation result of the clock signal CLK and the signal HBRK to the first counter 16. Since it is input, the first counter 16
Are counted according to the display period by the clock signal CLK, the address correction table is updated, and the signal HBR
The preset data is loaded at the falling edge of K.

The preset data is set by the register 14. The register 14 sets the preset data to 0 in the odd field and sets the preset data to 1 in the even field according to the signal FD.
Set to FF (hexadecimal). The first counter 16
The up / down switching in is also performed according to the signal FD.

At this time, the first counter 16 has 1FF.
After counting up to (hexadecimal), the value then returns to 0, whereupon the second counter 17 starts counting by the signal HBRK, and the address becomes 2000 (hexadecimal).
That is, in the address correction table of FIG. 4, the correction addresses are sequentially output from the leftmost row from the top row.

On the other hand, in the even field, the first counter 16 sequentially counts from 1FF (hexadecimal) in the decreasing direction, while the second counter 17 counts in the increasing direction as in the case of the odd field. Therefore, in the address correction table of FIG. 4, correction addresses are sequentially output from the rightmost row from the top row.

The odd field and the even field are obtained by reversing the address table in the horizontal direction. In addition, the horizontal 9-bit address line
Since a subtracter (not shown) is inserted here, the subtractor is controlled by the signal FD to directly specify the horizontal address of the frame memory 12 in the odd field and 512 (hexadecimal 1F in the hexadecimal field).
The horizontal address of the frame memory 12 is designated by a value obtained by subtracting the horizontal address obtained from the address correction table from F). As a result, in the odd-numbered field and the even-numbered field, the addresses in the vertical direction are output with the left and right reversed, so that only the distortion is displayed with the left and right reversed in the image display of the left and right LCDs. Distortion correction in the opposite direction can be performed on the eye.

As a result, in the head-mounted image display device for observing images with both the left and right eyes, the capacity of the frame memory for storing the address correction table is halved by sharing one address correction table between the left and right. , A significant cost reduction is possible.

In the above embodiment, the number of horizontal pixels of the image is set to 512, so when the first counter of 9 bits is used to make one cycle, it becomes 512. However, if the horizontal pixel is 760
If the number is halfway, it can be dealt with by using the circuit shown in FIG. 5 and modifying FIG. That is, as shown in FIG. 5, an adder 23 is inserted between the first counter 16 and the address correction table 20, and a multiplier 24 is inserted between the second counter 17 and the adder 23, so that the multiplier 24 has 760 10-bit signal representing the horizontal pixel of is input. Then, the first counter 16 outputs a signal instructing the lower 10-bit address forming the 18-bit address correction table, and the second counter 17 instructing the upper 8-bit address forming the 18-bit address correction table. The address correction table may be adjusted so that the address correction table has 18 bits.

[0023]

As described above, according to the present invention, when the left-eye video signal and the right-eye video signal to be displayed are input to the video signal processing device, the correction data reading means stores the address correction table. Each field is read from the reverse direction (for example, an odd field is read from left to right and an even field is read from right to left), and the address correction unit outputs a left-eye video signal to be displayed based on the read correction table and The right-eye video signal is address-corrected, and the field switching output means switches the address-corrected left-eye video signal and right-eye video signal for each field and alternately outputs them to the left and right video display elements. The same address correction as the conventional example using a single address correction table can be performed, and the cost can be reduced by halving the memory.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a first embodiment of a head-mounted image display device of the present invention.

FIG. 2 is a diagram showing details of the video signal processing device of the first embodiment.

3A to 3D are signals F in the first embodiment.
It is a time chart which shows an example of a waveform of D, HBRK, VBRK, and CLK.

FIG. 4 is a diagram showing an example of an address correction table used in the first embodiment.

FIG. 5 is a diagram showing only a changed portion when the number of horizontal pixels is changed in the first embodiment.

FIG. 6 is a diagram for explaining a conventional technique.

[Explanation of symbols]

 1 Image signal processing device 2L, 2R Image display element (LCD) 3L, 3R Lens 4L, 4R Concave mirror 5L, 5R Left and right eyeballs of observer

Claims (1)

[Claims] 1. An address correction table, correction table reading means for reading the address correction table from the opposite direction for each field, and a left-eye video signal and a right-eye video signal to be displayed based on the read correction table. A video signal processing device having address correction means for performing address correction, field switching output means for switching the address-corrected left-eye video signal and right-eye video signal for each field, and outputting the video signal processing device. Left and right video display elements that display the input left-eye video signal and right-eye video signal, respectively, and the left-eye video signal and the right-eye video signal displayed on these video display elements A head-mounted image display device, characterized in that it comprises a decentered concave optical system for projecting on each.