JPH07142588A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the frequency characteristics of the entire body of buffers by satisfying specified conditions for the relationship between the gate width of the differential pair transistors of the differential part of a buffer circuit and the gate width of a pair of transistors of a source follower part. CONSTITUTION:In a semiconductor integrated circuit, wherein buffer circuits are connected in a cascade pattern of N stages, the buffer circuits must drive larger loads when the number of the stages advances. Therefore, the gate width WDIF (i) of each of the pair transistors on the differential part of each buffer circuit is gradually increased from the first stage to the final stage. In the buffer circuit of each stage (i), the gate width WSF (i) of each of the pair transistors T4i and T5i constituting a source follower part is made larger than the gate width WDIF (i) of each of the part transistors T1i and T2i at of the differential part. The gate width WDIF (i+1) of each of the transistors T1i+1 and T2i+2 in the next stage i+1 is made smaller than the gate width WSF (i) of each of the transistors T4i and T5i.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a SCFL (Source Cou
pled FET logic).

[0002]

2. Description of the Related Art In recent years,
Development of semiconductor integrated circuits for ultra-high-speed communication systems such as optical communication systems is active. These semiconductor integrated circuits
GaAs semiconductors are used mainly because of their high speed.

There are many types of basic circuits in integrated circuits using GaAs semiconductors. Typical examples are DCFL (Direct Couple FET Logic) which is a single phase drive system and SCFL (Source Coupled) which is a two phase drive system. FET Logi
c) is mentioned. Of these basic circuits, SCFL
Is suitable for ultra high speeds. The main reason is that the logic capability is large and the T-type flip-flop and the D-type flip-flop, which are the main circuit elements of the ultrahigh-speed circuit, can be configured with two gates.

An example of the structure of the SCFL is shown in FIG. This S
The CFL is used as a buffer and is composed of a differential section and a source follower section. This differential portion includes a level shift resistor R1, a load resistor R2 and a MES.
(Metal semiconductor) A first series circuit including a field effect transistor (hereinafter, simply referred to as a transistor) T1 and a second series circuit including a resistor R3 and a transistor T2.
And a constant current source composed of a transistor T3 and a resistor R4, and the first series circuit and the second series circuit form a differential pair. Further, the source follower unit includes a source follower circuit including a transistor T4, a diode D1, a transistor T6, and a resistor R5 connected in series, and a transistor T5 and a diode D connected in series.
2, a source follower circuit including a transistor T7 and a resistor R6. And the transistor T
One of the pair of outputs of the differential section is input to the gate of the transistor 4, the other of the pair of outputs of the differential section is input to the gate of the transistor T5, and the output of the SCFL circuit is output from the output terminal of the diode D1. One of the output OUT is taken out from the output end of the diode D2 to the other output bar OUT.
Is taken out.

The frequency characteristic of this SCFL circuit will be described with reference to FIG. In FIG. 3, the graph g ₁ is SCFL
The frequency characteristic of the differential portion of the circuit is shown, the graph g ₂ shows the frequency characteristic of the source follower portion, and the graph g ₃ shows the SCFL.
The frequency characteristic of a circuit is shown. As can be seen from the graphs g ₁ and g ₂ , the gain of the source follower unit is 0 dB or less in principle, and the differential unit produces the gain. Further, it can be seen that the source follower section starts to attenuate in a region where the frequency is lower than that of the differential section. Therefore, it is the frequency characteristic of the source follower section that adversely affects the frequency characteristic of the SCFL circuit, which is the sum of the specific frequency characteristics of the differential section and the source follower section.

As a typical IC for ultra-high-speed communication systems, a multiplexer for time-multiplexing a data signal of a plurality of bits into a 1-bit data signal having a large bit rate, or a de-conversion device for performing the inverse conversion. Examples include multiplexers. Inside these ICs, there are a timing generation circuit for generating several kinds of clock signals having different frequencies, and a clock buffer circuit necessary for giving the appropriate delay time to the core circuit and distributing the generated clock signal to the core circuit. .

Here, the 20 Gbps that we actually designed
In the case of an 8-bit multiplexer operating in, for example, there is a 15-stage connected buffer chain inside which a 10 GHz clock signal is transmitted. It was necessary to connect 15 stages of buffers in order to apply a clock signal to the core circuit at an appropriate timing. In this way, ultra-high speed IC
Therefore, high frequency signals are often transmitted through buffer circuits connected in multiple stages.

Here, points to be noted when designing such a cascade-connected buffer circuit will be described. Each buffer circuit gives a gain to the input waveform, and
It is necessary to send the buffer signal to the next stage that has a larger input capacity than myself. Further, the cutoff frequency (frequency at which the gain becomes 0 dB) in the frequency characteristic of each buffer should have a sufficient margin with respect to the frequency of the signal to be transmitted. The point to be noted here is that this margin needs to be increased as the number of stages connected in cascade increases. The reason for this is that there are actually variations in device characteristics, but a supplementary explanation will be added below.

When the frequency of the transmitted signal approaches the cutoff frequency of the buffer, its output waveform is no longer a square wave but a sine wave. This is because there is no gain for higher-order frequency components when Fourier expansion is performed. Actually, there are variations in element characteristics, which may cause the amplitude center levels of the two-phase signals to deviate from each other. And since the waveform is already a sine wave,
The duty ratio (the ratio of the high level time in one cycle) deviates from 50% of the ideal value. A waveform whose duty ratio deviates from 50% has a high-order frequency component, and it becomes difficult for the buffer at the next stage to give a gain to this waveform and output it. That is, the amplitude is attenuated.

Further, as described above, the source follower section, which is the output stage of the SCFL circuit, has a gain of 0 dB in principle.
It is below, and considerable attenuation occurs in the high frequency region. Since it is a two-phase drive system, there are two source follower circuits per SCFL circuit, and the pair of source follower circuits are independent from each other. Now, let's assume that a waveform with a different duty ratio is input to the source follower circuit through the differential section. If there is no element variation in the differential unit itself, the outputs of both phases will not deviate from the high level and the low level even if the duty is deviated. But,
The fundamental wave, which is the first-order term, is a two-phase sine wave having different amplitude center levels. Now, since the frequency near the cutoff frequency of the buffer is assumed, the source follower circuit cannot give a gain to a high-order frequency component. Therefore, it is equivalent to inputting the sine wave signals of both phases whose amplitude center levels are deviated to the pair of source followers. Now, when the sine waves of both phases having different amplitude center levels are respectively input to the pair of source follower circuits, the amplitudes are attenuated with the respective amplitude center levels being the reference. This is a phenomenon in which the deviation of the duty ratio is further increased.

As described above, the duty is deviated due to the element variation, and once the duty ratio is deviated, the original characteristic of the source follower circuit constituting the output stage of the SCFL circuit is caused.
Each time the signal passes through the buffer, the deviation of the duty ratio is amplified. As a result, the larger the number of connected buffer stages, the greater the deterioration of the waveform.

In order to avoid such a phenomenon, the cutoff frequency of each buffer circuit must be sufficiently higher than the frequency of the signal to be transmitted.

When an 8-bit or more multi-bit multiplexer or demultiplexer is designed in this way, a multistage connected buffer circuit through which a high frequency signal passes is required. It can be seen that the specifications for frequency characteristics are quite strict. The frequency characteristic of each buffer often becomes the deciding factor of the performance of the entire circuit. That is, even if the frequency of the D-type flip-flop, which is a main component of the multiplexer and the demultiplexer, is operable, waveform deterioration occurs in the clock buffer circuits connected in multiple stages, and the circuits do not operate.

As described above, it is important to improve the frequency characteristics of the SCFL buffer, and for that purpose, it is necessary to improve the frequency characteristics of the source follower section as described above.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit having clock buffers connected in multiple stages with good frequency characteristics.

[0016]

A semiconductor integrated circuit according to the present invention includes a differential section having a pair of differential pair transistors.
A semiconductor integrated circuit in which a buffer circuit composed of an SCFL including a source follower unit having a pair of transistors for receiving the output of the differential unit is cascade-connected in N stages, i (1 ≦ i ≦ N) The gate width of the differential pair transistor of the differential part of the buffer circuit of the first stage is W _DIF (i), and the gate width of the pair of transistors of the source follower part of the buffer circuit of the i stage is W _SF (i). In this case, the following condition (a) for i = 1, ... N−1: W _DIF (i) <
W _DIF (i + 1) (b) For i = 1, ... N W _DIF (i) <
W _SF (i) (c) For i = 1, ... N-1, W _SF (i)>
It is characterized by satisfying W _DIF (i + 1).

[0017]

By performing a circuit simulation of the semiconductor integrated circuit of the present invention having the above-described structure, it can be seen that it is possible to obtain better frequency characteristics than the conventional one.

[0018]

FIG. 1 shows the configuration of an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit of this embodiment is shown in FIG.
A pair of transistors T in the differential section of the i (1 ≦ i ≦ N) -th stage SCFL circuit in which the buffer circuits including the SCFL circuit shown in FIG.
When the gate widths of 1 _i and T2 _i are W _DIT (i), the transistor T of the source follower section of the i-th stage SCFL circuit is
When the gate widths of 4 _i and T5 _i are W _SF (i), W _DIF (i) <for the following condition (a) i = 1, ...
W _DIF (i + 1) (b) For i = 1, ... N W _DIF (i) <
W _SF (i) (c) For i = 1, ... N-1, W _SF (i)>
It satisfies W _DIF (i + 1). That is, the condition (a) is that the buffer circuit needs to drive a large load as the number of stages progresses, so that the gate width W _DIF (i) of the pair transistors of the differential section of each buffer circuit is from the first stage to the final stage. It shows that it is gradually increasing toward.

The condition (b) is that in the buffer circuit of each stage i, the transistors T4 _i and T5 _i forming the source follower portion are more than the gate width W _DIF (i) of the pair transistors T1 _i and T2 _i of the differential portion. It is shown that the gate width W _SF (i) of is increased.

Further, the condition (c) is that the transistors T4 _i and T5 which form the source follower section of the buffer of a certain stage i.
_i of the gate width W _SF (i) the next stage i + 1 of the transistors of the differential section of the pair T1 than i _{+ 1,} T2 i + ₁ of the gate width W _DIF
This indicates that (i + 1) is set small.

The above conditions (a), (b) and (c) are set for the following reason.

The input capacitance of the source follower section is 1 / th that of the differential section composed of transistors having the same gate width.
It is as small as 3. However, the driving capability is large enough to match the gate width. Then, we have found the following characteristics.

That is, in constructing one buffer for driving a certain load, the frequency characteristics are improved by making the gate width of the source follower section about twice larger than that of the differential section. This is true even when the gate width of the source follower section that is set to a large value is larger than that of the differential section of the next stage, as shown in equation (c).
By making the gate width of the source follower larger than that of the differential section at the next stage, the load on the differential section at the preceding stage of the source follower section becomes large and the frequency characteristic of the differential section deteriorates accordingly. Will. However, since the input capacitance per unit gate width of the source follower portion is small, the deterioration is not so large. On the other hand, for the source follower unit, the load on the next stage is reduced, and its frequency characteristic is improved. That is, the frequency characteristic of the differential section, which was originally superior to the source follower section, is slightly deteriorated, and instead, the frequency characteristic of the source follower section is improved, thereby improving the frequency characteristic of the entire SCFL buffer.

For example, in this embodiment, the transistors T1 _i , T2 _i , T of the differential section of the buffer circuit at a certain stage i are used.
3 _{i has} a gate width W _DIF (i) of 28 μm, and the source follower transistors T4 _i , T5 _i , T6 _i , T7 _i ,
Has a gate width W _SF (i) of 60 μm and transistors T1 _{i + 1} , T2 _{i + 1} , T3 _{i + 1} of the differential section of the buffer circuit of the next stage.
_Has a gate width W _DIF (i + 1) of 42 μm, and the source follower transistors T4 _{i + 1} , T5 _{i + 1} , T6 _{i + 1} , T
The gate width W _SF (i + 1) of 7 _{i + 1} is 90 μm. That is, the gate width ratio of the transistors in the i-th stage and the i + 1-th stage differential part is set to 1: 1.5, and the gate width ratio of the transistors in the i-th stage and the i + 1-th stage source follower part is also set to 1: 1.
Set to 5. On the other hand, in the conventional buffer circuit of each stage, the transistor T of the differential portion and the source follower portion is
1 _i , T2 _i , T3 _i , T4 _i , T5 _i , T6 _i , T7
The gate width of _i is the same. Now, as in the differential section of the present embodiment, the gate width of the transistor of the conventional buffer circuit of one stage is 28 μm, and the gate width of the transistor of the next stage is 42 μm (the gate width of the transistor of the next stage is 42 μm.
When the cutoff frequency of the buffer circuit in the case of (= 28 × 1.5) is examined by circuit simulation, the conventional buffer circuit has 11.1 GHz, whereas the present embodiment shows that 20% improvement, 13.3 GHz
Met.

As described above, according to this embodiment,
The frequency characteristics of the clock buffers connected in multiple stages can be improved by 20% without changing the FET manufacturing process.

The simulation FET model is obtained by measuring the following MESFET and extracting the model.

That is, this is a MESFET composed of a tungsten nitride in which an active layer is formed by selective ion implantation of Si on a semi-insulating GaAs substrate and tungsten is stacked on the gate, and a PES having a gate length of 0.35 μm.
It is formed using a layer embedding process.

The main circuit parameters are as follows. The gate-source voltage when the switching FETs included in the SCFL circuit are on is 0.35V, and the design value of the logic amplitude is 0.9Vp-p.

The power supply voltage VSS is -5.2V and the bias voltage VB is -4.5V.

As described above, the SC using the GaAs MESFET
Although the embodiment using the FL circuit is shown, the present invention is also effective for ECL (Emitter Coupled Logic) which is the same circuit system.

[0031]

As described above, according to the present invention, it is possible to obtain a semiconductor integrated circuit having multistage connected clock buffers having good frequency characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of an SCFL circuit.

FIG. 3 is a graph showing frequency characteristics of the SCFL circuit.

[Explanation of symbols]

T1 _i , T2 _i differential section transistor T4 _i , T5 _i source follower section transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kei Wakimoto 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Toshiba Corporation R & D Center

Claims (1)

[Claims] 1. A N-stage cascaded buffer circuit composed of an SCFL including a differential section having a pair of differential pair transistors and a source follower section having a pair of transistors receiving an output of the differential section. In the connected semiconductor integrated circuit, the gate width of the differential pair transistor of the differential section of the buffer circuit of the i-th (1 ≦ i ≦ N) stage is W
_{When DIF} (i) and the gate width of the pair of transistors in the source follower section of the i-th stage buffer circuit is W _SF (i), the following condition (a): i = 1, ... W _DIF (i) <
W _DIF (i + 1) (b) For i = 1, ... N W _DIF (i) <
W _SF (i) (c) For i = 1, ... N-1, W _SF (i)>
A semiconductor integrated circuit characterized by satisfying W _DIF (i + 1).