JPH07142576A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate error connection between both wirings and the generation of defective connection by forming a column-like contact part in a lower layer wiring at the time of forming a lower layer pattern to prevent positional displacement and a contact resistance defect between the lower layer wiring and the contact part. CONSTITUTION:An intermediate aluminum in which a first wiring 2, an etching stopper 3 and a contact part 4 are formed is bonded to cover a wafer 1. Etching is performed by using a resist pattern 5 to form a first layer aluminum layer to intermediate aluminum layer in accordance with the patterns of the first layer wiring. Next, the resist pattern 5 is removed, and a resist 6 is applied thereto again, and a resist on non-contact part is removed. At that time, adequate margin 14 is taken. Only non-contact part 13 is removed to form a column-like part to make the contact part 4 on the first layer wiring 2. Next, an oxide film 7 is deposited and then flattening is performed until the contact part 4 is exposed. Thereby, an upper and a lower layer wiring can be surely interconnected.

Description

Detailed Description of the Invention

[0001]

2. Description of the Related Art In manufacturing a semiconductor device, a lower layer aluminum wiring and an upper layer aluminum wiring are connected at the time of forming a wiring. A conventional technique relating to this connection will be described with reference to FIG. After forming the wiring 8, an insulating film 11 is deposited, and a contact hole 12 is formed by etching the insulating film. Then, an upper wiring 9 is formed and a contact portion is formed by filling the contact hole 12 with aluminum. The upper layer wiring and the lower layer wiring are connected.

In recent years, with the high integration of semiconductor devices, wiring patterns tend to become finer. As a result, there is no margin for misalignment between the wiring pattern and the etching resist pattern, and a slight misalignment prevents the contact hole from being properly positioned on the lower layer wiring, causing the contact part to not be properly connected to the lower layer wiring. It is necessary to widen the portion in contact with the contact portion, but this is against the miniaturization of the wiring pattern and therefore the high integration.

If the diameter of the contact hole is reduced, aluminum may not be uniformly filled in the hole and the contact resistance may be increased. As a countermeasure against this, a method of forming the contact portion by selective growth of tungsten has been studied, but there is a problem that the growth rate is slow.

[0004]

The method of forming the above-mentioned contact hole and burying aluminum in the above-mentioned contact hole or growing tungsten to form the contact portion between the upper and lower wirings is a method of making a contact error and a contact resistance defect. There are drawbacks.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a multilayer wiring structure in which upper and lower wirings are surely connected without hindering high integration.

[0006]

According to the method of manufacturing a semiconductor device of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:
A third conductive layer is overlaid via a second conductive layer as an etching stopper, the three layers are etched according to a lower wiring pattern, and a portion of the third conductive layer other than the portion corresponding to the contact portion is removed. There is a step of forming a contact portion by removing it, depositing an insulating film, and planarizing until the contact portion is exposed.

[0007]

The third conductive layer is provided on the first conductive layer forming the lower wiring via the second conductive layer as an etching stopper, these three layers are etched according to the under wiring pattern, and then the upper wiring is formed. The third metal layer other than the portion corresponding to the contact portion with and is removed, and the columnar portion of the conductive layer remaining on the lower wiring is flattened after the insulating layer is deposited until the columnar portion, that is, the contact portion is exposed.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view and a plan view of a contact portion showing a main part of a process included in a manufacturing method according to an embodiment of the present invention, and a, b-1, c and d-1 are cross-sectional views. ,
b-2 and d-2 are plan views, and b-1 and d-1 are cross-sectional views at positions crossing the contact portion in plan views b-2 and d-2, respectively.

First, an aluminum layer to be a first layer wiring 2 which is a lower layer wiring, a titanium nitride layer to be an etching stopper 3 and an intermediate aluminum layer where a contact portion 4 is formed are deposited on a wafer by a sputtering method, and then a resist pattern 5 is formed. Is used to form a first aluminum layer to an intermediate aluminum layer according to the pattern of the first layer wiring (FIG. 1a).

Next, the resist pattern 5 is removed, the resist is applied again, and the resist located on the intermediate aluminum layer (non-contact portion 13) other than the portion to be the contact portion is removed (FIG. 1b-1, FIG. 1b-1). b-2).

At this time, a sufficient margin 14 is provided at the boundary of the area where the resist should be removed in the resist pattern 6 so that the aluminum columnar part is not formed in the part other than the contact part due to the deviation between the first layer wiring pattern and the resist pattern. Need to take.

In FIGS. 2a and 2b, the margin is taken by widening the line width of the lower layer wiring 8 in contact with the bottom surface 10 of the contact hole.
In this case, since the margin is provided for the resist pattern 6 for removing the non-contact portion 13, it is not necessary to widen the wiring width.

If only the non-contact portion 13 is removed by etching, a columnar portion to be the contact portion 4 is formed on the first layer wiring 2 with the first layer wiring 2 remaining under the etching stopper 3. To be done.

Next, an oxide film 7 to be an insulating film is deposited by chemical vapor deposition (FIG. 1c), and planarized by polishing until the contact portion 4 is exposed (FIG. 1d).
-1, d-2). By planarizing the interlayer film with the second-layer wiring in this way, the positional deviation of the second-layer pattern can be reduced to such an extent that it does not hinder.

The formation of the contact portion used for connecting the first layer wiring and the second layer wiring has been described above, but the same applies to the connection of the second layer wiring and the third layer wiring.

[0017]

As described above, according to the present invention, since the contact portion is formed in a columnar shape on the lower layer wiring when the lower layer wiring pattern is formed, the contact portion is misaligned or the contact resistance is increased due to the defective filling. There is no defect such as that, and the interlayer film with the upper wiring is finished flat. Further, it is not necessary to widen the wiring width in the vicinity of the contact portion, which has been conventionally performed to prevent the displacement of the contact portion, with a margin for the positional displacement.
This has the effect of contributing to the improvement of wiring integration.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view and a plan view of a contact portion showing a main part of steps included in a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view and a plan view of a conventional example of a contact portion.

[Explanation of symbols]

 1 Wafer 2, 8 Lower layer wiring 3 Etching stopper 4 Contact part 5, 6 Resist pattern 7 Oxide film 9 Upper layer wiring 10 Bottom of contact hole 11 Insulating film 12 Contact hole 13 Non-contact part 14 Margin

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, wherein adjacent upper and lower wirings are connected by a contact portion formed between the two wirings, wherein an etching stopper is formed on a first conductive layer on which a lower wiring is formed. A third conductive layer is provided via a second conductive layer as an insulating layer, the three layers are etched according to a lower wiring pattern, and a portion of the third conductive layer other than a portion corresponding to the contact portion is removed. A method of manufacturing a semiconductor device, comprising the steps of forming the contact portion by removing, depositing an insulating film, and planarizing the insulating film until the contact portion is exposed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first and third conductive layers are aluminum layers, and the second conductive layer is a titanium nitride layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of planarizing until the contact portion is exposed is performed by planarizing the insulating film by etching or polishing. 4. The semiconductor device according to claim 1, wherein the step of removing the portion other than the portion corresponding to the contact portion is performed by removing the portion other than the portion corresponding to the contact portion with a certain margin. Production method.