JPH0530065B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a semiconductor device having a so-called multilayer wiring structure in which the wiring layer structure is two or more layers.

[Prior art and its problems] Conventionally, semiconductor devices and integrated circuits with multilayer wiring structures have been produced by forming an insulating film such as a silicon oxide film on a semiconductor substrate on which the device is formed, and connecting the device with the device on the substrate.
Holes are formed in the insulating film in the portions necessary for connection with the wiring layer formed on the insulating film thereon by photolithography, and a film of, for example, aluminum is coated on the entire surface.
First wiring in a predetermined pattern is formed using photolithography.

Furthermore, after forming an insulating film such as a silicon oxide film on this by vapor phase growth etc., in order to make a connection with the wiring layer formed on it, the connection is made again using photolithography. After drilling holes and coating the entire surface with a film such as aluminum, a predetermined pattern is formed.
This is the second wiring layer.

However, in such conventional manufacturing methods, due to the step etc. caused by the first wiring layer,
This may cause the second wiring layer to become thinner and more likely to break at the sidewalls of the step, or the wiring pattern formed by photo-etching to become thinner at the resistance of the step, reducing the reliability of the wiring layer. There is.

In order to improve this problem, a method has been devised in which a flat insulating film is formed on the first wiring layer to thereby prevent the second wiring layer from breaking. As an example of this leveling, there is a method of spin-coating a fluid polymeric material such as polyimide resin, and this leveling has a very large effect on the reliability of the wiring layer.

However, this does not mean that all problems with the wiring layer have been solved. When forming a connection hole with the second wiring layer, a so-called through hole, in the insulating film on the first wiring layer, photolithography is used to form a through hole with the same size as the width of the first wiring layer. A deep groove is created in the insulating film inside the through hole due to misalignment of the mask. FIG. 1 shows this state, in which a is a plan view and b is a sectional view. As shown in FIG. 1B, the groove at the bottom of the through hole 10 causes the second wiring layer 11 (for example, aluminum) to be disconnected, and the reliability of the connection between the wiring layers is significantly reduced.

In this case, if the size of the through hole 10 is made sufficiently smaller than the width of the first wiring layer 3 in consideration of the misalignment of the mask, the through hole 10 described above can be
However, if the width of the first wiring layer 3 is 2.0 μm, the size of the through hole 10 will inevitably be 2.0 μm or less if mask misalignment is taken into account. Moreover, the alignment accuracy of the mask alignment device is ±0.2 to 0.3 μm. As a result, the through hole 10 must have a diameter of 1.4 μm or less, which lowers the reliability of interconnection between wiring layers and increases contact resistance, which greatly impedes high-speed operation of the device.

A conventional example for avoiding the above problem is shown in FIG. As in FIG. 1, a is a plan view and b is a sectional view. As shown in FIG. 2, the width of the first wiring layer 3 is expanded only at the through hole 10,
0, even if a mask misalignment occurs in the photolithography method, the through hole 10 will be connected to the first wiring layer 3.
The structure is such that it does not shift from the width. However, as mentioned above, the alignment accuracy of the mask alignment device is ±0.2 to 0.3 μm (this is how it is), and for this reason,
The width of the first wiring layer 3 at the through hole 10 is as follows:
It is widened by more than 0.5μm on one side. As a result, the melting potential of the first wiring layer increases, increasing the area occupied by the wiring, and restricting the melting density of the wiring layers, which impedes higher density of wiring layers and elements and limits the degree of integration. .

Furthermore, increasing the density of the second wiring layer 9 is also limited, and the more wiring layers are formed, the greater this influence becomes.

New structures are being devised to address these problems.

As shown in FIG. 3a, after forming the first wiring layer 3, a first insulating film, for example, a silicon chloride film 5, is deposited on the entire surface, and then reactive ion etching is performed using CF ₄ /H ₂ gas. When the entire surface is etched using the method, a silicon nitride film 5 can be formed on the sidewalls of the first wiring layer 3. Thereafter, as shown in FIG. 3B, a second insulating film, for example a silicon dioxide film 8, is deposited, and a resist 9 is further applied. Through hole 1 made by photo-etching method
0, the second insulating film 8 is etched using the resist 9 as a mask, and a through hole 10 is formed. If the etching conditions (speed) at this time are that the first insulating film is smaller than the second insulating film, even if the through-holes are formed out of alignment as shown in Figure b, the etching will stop at the first insulating film, as described above. As shown in FIG. 3c, it is possible to form a second wiring layer without any steps, without forming any grooves.

However, to form an insulating film on the sidewalls of the wiring layer, the anisotropic etching properties of reactive ion etching are used, but the theoretical (ideal) shape is not always obtained. do not have. Figure 4a shows the theoretical form, and Fig. 4b shows the actually obtained form. Ideally, in the method of using the insulating film on the side wall of the wiring layer, it is desirable that the dimensions of the insulating film on the side wall of the wiring layer are the same width on the top and bottom, as shown in a. This is because the apparent width of the wiring layer is thereby increased, so that misalignment of the through holes can be sufficiently compensated for.

However, it is difficult to form this shape due to optimization of the reactive ion etching conditions and other reasons, and the shape shown in b is often obtained. However, with this shape, if there is a large misalignment, a groove-like shape will still form in the lower part 12 of the through hole in Figure 3 b, c, and there is a risk of breakage when forming the second wiring layer, resulting in a complete It can not be said.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a fine multilayer wiring structure that solves the above problems, increases the degree of integration of wiring and elements, and has high reliability.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device with a multilayer wiring structure, in which a first insulating film is deposited on a semiconductor substrate on which a first wiring conductor layer is formed, and Ar, P,
Ion implantation of impurities such as As.

After this, by etching the entire surface, the first
A first insulating film is formed on the sidewall of the wiring layer. then the second
An insulating film is deposited, a connection hole is formed in a predetermined region of the second insulating film using an etching method in which the etching rate of the second insulating film is faster than that of the first insulating film, and then a second wiring is formed. This is a method of forming layers.

〔Effect of the invention〕

According to the present invention, when forming a connection hole (through hole) that is the same size as the width of the first wiring layer or larger, it is possible to change the etching conditions even if mask misalignment occurs during photolithography. According to
The first insulating film is hardly etched, and the surface of the first wiring layer and the surface of the first insulating film are at the same height and are completely flattened, preventing breaks in the second wiring layer at connection holes. Therefore, a highly reliable wiring layer can be formed. Furthermore, since there is no need to increase the width of the first wiring layer relative to the size of the connection hole (through hole), it is possible to miniaturize the wiring layer, and the area occupied by the wiring layer is reduced.
Since the element density can be increased, a semiconductor device with a small chip size and high integration can be obtained.

[Embodiments of the invention]

Hereinafter, specific embodiments of the present invention will be described using the drawings. First, as shown in FIG.
A silicon dioxide film 2 of
A 0.8 μm aluminum (hereinafter referred to as Al) film 3 was deposited,
Further, a photoresist is applied, and a photoresist film 4 is formed by photolithography.

Thereafter, using the photoresist film 4 as a mask and using, for example, BCl ₃ /Cl ₂ gas, the Al film 3 is etched by reactive ion etching to form a first wiring layer. After removing the photoresist film 4, plasma is applied using SiH ₄ /NH ₄ gas, for example, as shown in b.
After depositing a silicon chloride film 5 with a thickness of 1.0 μm using the CVD method, for example, 1×10 ¹⁵ cm of phosphorus (P ⁺ ) 6 is deposited on the entire surface.
Perform ion implantation at ^-2 . At this time, if the implantation amount in the depth direction is controlled to the same depth as the thickness of the silicon nitride film 5, ions will not be implanted inside the broken line 7.

In this state, if the entire surface is etched by reactive ion etching using CF ₄ /H ₂ gas, for example,
Since the etching rate of the ion-implanted silicon nitride film 5 is increased, it is possible to form the silicon nitride film 5 having the same upper and lower widths on the side wall of the first wiring layer 2, as shown in c. Thereafter, as shown in d, a silicon dioxide film 8 with a thickness of 1.0 μm is deposited by plasma CVD using, for example, SiH ₄ /O ₂ gas, a photoresist is further applied, and a photoresist film 9 is formed by photolithography. and use this as a mask, e.g.
A through hole 10 is formed by a reactive ion etching method using CF ₄ /H ₂ gas. In this case, as shown in the figure, even if misalignment of the mask occurs during photoetching, the selection ratio between the silicon dioxide film 8 and the silicon nitride film 7 can be controlled by changing the reactive ion etching conditions. , it is possible to prevent the phenomenon explained in Fig. 1, and by etching after ion implantation, it is possible to form an ideally shaped insulating film on the side wall of the wiring layer as shown in Fig. 4a. Therefore, it is possible to sufficiently cope with misalignment of the mask during photoetching.
The etching selection ratio described above can be controlled, for example, as follows. That is, "Very LSI Technology 6, Semiconductor Process Part 2, Semiconductor Research 19 (edited by Junichi Nishizawa, published by Semiconductor Research Promotion Association Industrial Research Group), pp. 232 to 233.
CF ₄ 21cc/
min, H ₂ 12cc/min pressure 1×10 ^-2 Tor,
When N ₂ is added at a flow rate of 0 to 2 cc/min under the condition of RF power 150W, the etching rate can be controlled so that the etching rate of the silicon dioxide film 8 is faster than that of the silicon nitride film 7. . After that, the photoresist film 9 is removed, and as shown in e, a second wiring layer is formed, for example.
An Al film 11 is deposited and processed.

The second wiring layer formed in this way is the fifth wiring layer.
As can be seen from Figure e, even if mask misalignment occurs in the photolithography process when forming through-holes, by changing the conditions of the reactive ion etching process,
Etching can be stopped when the silicon nitride film appears, and it is possible to prevent a step (groove) from occurring at the bottom of the through hole as described in FIG. 1. Moreover, the silicon nitride film formed on the side wall of the first wiring layer can be formed into an ideal shape as shown in FIG. 4a by combining ion implantation and etching. The effect on mask misalignment is greater than that in Fig. 4b, and there is no need to take into account the mask misalignment explained in Fig. 2 and widen the width of the wiring layer of the through hole F, which was a problem in the past. It is possible to reduce the melting point of the interconnection layer, which was previously used, and achieve higher density and higher integration of devices.

In the above embodiment, when forming the first insulating film on the side wall of the first wiring layer, P ⁺ (phosphorous) was implanted in the ion implantation, but other materials such as O ₂ , N ₂ , Ar, As, and B were also implanted. However, although reactive ion etching using CF ₄ /H ₂ gas was used for etching, other anisotropic etching methods and isotropic etching methods such as plasma etching could also be used. An insulating film having an ideal shape as shown in a can be formed.

Furthermore, although aluminum was used as the wiring material in the above embodiments, the present invention can also be applied to other materials such as molybdenum, tungsden, tantalum titanium, platinum, the silicides, and polycrystalline silicon. Further, in the embodiment, the case where two wiring layers are provided is explained, but multilayer wiring with three or more wiring layers can also be realized by repeating the method described in the above embodiment. .

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views for explaining problems and countermeasures in conventional multilayer wiring technology, Figure 3 is a process cross-sectional view for explaining new multilayer wiring technology, and Figure 4 is , FIG. 3 is a sectional view showing the ideal shape and actual shape of the silicon nitride film pattern according to the method explained, and FIG. It is a diagram. 1...Silicon substrate, 2...Silicon dioxide film, 3
...First wiring layer (Al), 4...Photoresist film, 5...Silicon chamber oxide film, 7...Silicon chamber film without ion implantation, 8...Silicon dioxide film, 9...Photoresist film, 10...Through hole, 11...
Second wiring layer (Al).

Claims (1)

[Claims] 1. In a semiconductor substrate on which a first wiring layer is formed, a step of forming a first insulating film on the first wiring layer and then implanting impurity ions into the entire surface;
etching the entire surface of the first insulating film into which the impurities have been ion-implanted to leave the first insulating film on the side surface of the first wiring layer; and forming a second insulating film on the entire surface. a step of forming a wiring connection hole in a predetermined region of the second insulating film using an etching method in which the etching rate of the second insulating film is faster than that of the first insulating film; 1. A method of manufacturing a semiconductor device, comprising the step of forming a layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity ion-implanted into the entire surface of the first insulating film is O ₂ , N ₂ , Ar, P, As, or B. 3. A method of manufacturing a semiconductor device according to claim 1, characterized in that a wiring connection hole is formed having a width equal to or larger than the width of the first wiring conductor layer.