JPH07142541A - Probe - Google Patents

Abstract

PURPOSE:To provide a probe for testing an IC with narrow-pitch electrodes by carrying out specified machining to a silicon semiconductor constitute a probe. CONSTITUTION:A square-shaped opening 12 is formed at the central section of a silicon substrate 11 while a plurality of beams 13 protected into the opening 12 from one surface side of the substrate are formed. Diffused layers 14a, 14b containing P-type impurities are shaped on one surface side and the other surface side of the silicon substrate 11 respectively. Silicon oxide films 15 and silicon nitride films 16 are formed on the whole surfaces on one surface side of the silicon substrate 11, and metallic wiring layers 17 extended from the front ends of each beam 13 to the outsides of frame sections are formed onto the silicon nitride films 16. On the other hand, silicon oxide films 18, 19 are shaped on the whole surfaces on the other surface side of the silicon substrate 11. Since a probe is composed of the silicon substrate, to which specified machining is carried out, the pitches of the beams can be constituted easily in size narrower than 60mum, and ICs such as an LCD driver, an ASIC, etc., can be tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an LCD driver and an AS.
The present invention relates to a probe used for testing an IC having a narrow pitch electrode (pad, bump, etc.) such as an IC.

[0002]

2. Description of the Related Art With the recent high integration of semiconductor elements, the number of pad electrodes required for a semiconductor chip is increasing and the area of the semiconductor chip is decreasing.

If high integration is achieved without changing the area of the semiconductor chip, more input / output pads and electrode pads are required because a chip having more functions can be obtained. Therefore, it is necessary to arrange many pads without increasing the cost, that is, without increasing the chip size, so that it becomes necessary to narrow the pad pitch.

Further, without changing the number or function of integrated elements,
Therefore, if the number of pad electrodes is not changed, a smaller chip size can be obtained as compared with the chip size realized by the manufacturing technology of one generation ago, the chip cost can be reduced, and the pad pitch can be narrowed. The need arises.

Conventionally, even if the degree of integration is increased, the pad pitch is 100 to 120 .mu.m, and no technical problem has occurred in the probe card used at the time of die-testing in the wafer state. However, in recent years, the degree of integration of semiconductor chips has increased more and more, and for the reasons described above, if pad electrodes with a finer pitch are provided, the probe cart required for the die-saw cannot be manufactured. It is becoming a situation.

Therefore, even if an attempt is made to increase the number of pads in order to increase the degree of integration and further enhance the function, if the pad pitch cannot be reduced, the chip size is expanded and the chip cost is increased. Further, even if it is attempted to reduce the cost by reducing the chip size while keeping the function as it is, the chip pitch cannot be reduced because the pad pitch cannot be reduced, which causes a problem of hindering cost reduction.

FIG. 57 shows a cross-sectional structure of a conventional probe card. A tungsten needle 103 is fixed with an epoxy resin 105 on a multilayer wiring substrate 101 composed of a glass epoxy substrate or the like. Tungsten needle 10
One end of 3 is connected to an electrode on the wiring board by solder 104.

As the material of the needle, there are palladium, an alloy of beryllium and copper, in addition to tungsten. FIG. 58 is an enlarged view of the tip portion of the needle. The tip of the needle 103 is thin and bent in a hook shape. The minimum tip diameter b at present is about 40 μm,
The minimum pitch p is about 80 μm. The root of the needle 103 is thicker than the tip, and for example, the diameter a of the root is a.
Is about 200 μm.

These needles 103 are arranged so as to match the pad electrodes of the semiconductor chip. Generally, the positional accuracy in the horizontal direction is ± 10 to 20 μm, and the positional accuracy in the height direction is ± 10 to 20 μm. is there.

In order to achieve a finer pitch by using such a technique, it is necessary to make the tip portion of the needle thinner, but not only the strength of the needle is weakened, but also the needle itself is molded thin. Is difficult. Also, as the pitch becomes finer, it is necessary to further improve the position accuracy of the needle,
The conventional technique has a problem in that the positional accuracy cannot be sufficiently secured for a pitch narrower than 60 μm. further,
In the conventional manufacturing method, it has become difficult to arrange the needles at a fine pitch for the number of pads exceeding 200.

[0011]

As described above, a needle obtained by processing and molding a conventional metal such as tungsten is used as a needle, and is aligned with the position of the pad electrode of the semiconductor chip on the multilayer substrate made of resin such as glass epoxy. With a probe that is placed one by one and fixed with epoxy resin, 60 μm
This causes a problem that it is difficult to arrange a large number of needles with high positional accuracy in accordance with a pad pitch that is narrower than that.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to be used for testing an IC having electrodes (pads, bumps) with a pitch smaller than 60 μm, such as an LCD driver and an ASIC. It is to provide a new probe.

[0013]

In order to achieve the above object, a probe of the present invention has two main surfaces and an opening formed in a central portion, and one main surface side to the opening. A semiconductor substrate having a plurality of beams protruding and curved toward the one main surface side, and a beam formed on one main surface of the semiconductor substrate via a first insulating film. A wiring layer extending from the tip of the semiconductor substrate to the outer peripheral portion of the semiconductor substrate, and a second layer formed on the other main surface of the semiconductor substrate.
And an insulating film.

The plurality of beams are regularly arranged so that their tips correspond to the arrangement of electrodes on the semiconductor chip, and the tips of the plurality of beams have electrodes on the semiconductor chip. To contact.

In the two main surface regions of the semiconductor substrate,
Diffusion layers each containing a predetermined concentration of impurities and having a predetermined depth are formed. In addition, conductive projections are formed on the tips of the plurality of beams.

[0016]

According to the above structure, the probe is composed of a semiconductor substrate which has been subjected to a predetermined process. Therefore, unlike the conventional case, there is no troublesome operation of arranging the metal needles one by one on the multilayer substrate in accordance with the positions of the electrodes (pads, bumps) of the semiconductor chip. The arrangement of beams can be achieved. Also, LCD driver and A
It is possible to provide a probe capable of testing ICs having electrodes with a pitch smaller than 60 μm, such as SIC.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.
The details will be described. FIG. 1 shows a probe according to a first embodiment of the present invention. Reference numeral 11 is a silicon (Si) substrate. In the central part of the silicon substrate 11,
For example, a rectangular opening 12 is formed. Therefore, the silicon substrate 11 has a substantially frame shape.

The silicon (single crystal) substrate 11 has a plurality of beams (beam-shaped projections) 13 protruding from one surface side of the silicon substrate to the opening 12. Diffusion layers 14a and 14b containing about 10 ¹⁶ cm ^-2 p-type impurities (for example, BF ₂ ) are formed on one surface side (including the beam) and the other surface side of the silicon substrate 11, respectively.

A silicon oxide film 15 is formed on the entire one surface of the silicon substrate 11. Silicon substrate 11
In the frame portion (excluding the beam), a silicon nitride film (SiN, Si ₃ N ₄ etc.) 16 is formed on the silicon oxide film 15. A wiring layer 17 extending from the tip of each beam 13 to the outside of the frame portion of the silicon substrate 11 is formed on one surface side of the silicon substrate 11.

The wiring layer 17 is made of tungsten (W), aluminum (Al), copper (Cu), palladium (Pd), beryllium (Be), nickel (Ni),
It can be composed of metals such as titanium (Ti), gold (Au), silver (Ag), and astatine (At). In addition, the wiring layer 17
May be a laminate in which a plurality of these metals are stacked, or an alloy of these metals. further,
The wiring layer 17 may be composed of a single layer portion (for example, only tungsten) and a laminated portion (for example, a laminated layer of tungsten and copper).

Silicon oxide films 18 and 19 are formed on the entire other surface of the silicon substrate 11. Each bee
The frame 13 is curved to one side of the silicon substrate 11.
This is the silicon substrate 11, the silicon oxide films 15 and 19
And the thermal expansion coefficient of the wiring layer 17 near room temperature is different.

According to the above structure, the probe is composed of a silicon substrate which has been subjected to a predetermined process. Therefore, the beam pitch can be easily made narrower than 60 μm. Moreover, the beam is curved so as to easily contact the pad of the IC. This allows the LCD driver and A
It is possible to provide a novel probe that can be used for testing an IC having an electrode pad with a pitch smaller than 60 μm, such as an SIC.

FIG. 2 conceptually shows the contact state between the probe of the present invention and the pad of the IC. That is, the beam 13
Is curved to one side of the silicon substrate 11. Therefore, the wiring layer 17 of the probe can be easily brought into contact with the pad 21 of the semiconductor chip (IC) 20 arranged on the one surface side of the silicon substrate 11.

FIG. 3 shows a probe according to the second embodiment of the present invention. This probe differs from the probe according to the first embodiment in the following points. That is, the probe of this embodiment has a conductive projection 22 at the tip of each beam 13.

The conductive protrusions 22 are formed on the wiring layer 1 of the probe.
This is for easily contacting the pad of 7 and the IC. The projections 22 may be formed by plating the tip of the beam 13 with metal, by adhering a conductive material to the tip of the beam 13, or by depositing (sputtering) a conductive film and etching. Can be obtained by

FIG. 4 shows a probe according to the third embodiment of the present invention. In the central part of the silicon substrate 11,
For example, a rectangular opening 12 is formed. Therefore, the silicon substrate 11 has a substantially frame shape.

Further, the silicon (single crystal) substrate 11 has a plurality of beams 13 protruding from one surface side of the silicon substrate to the opening 12. A diffusion layer 14 containing about 10 ¹⁶ cm ^-2 p-type impurities (for example, BF ₂ ) on one surface side (including the beam) and the other surface side of the silicon substrate 11, respectively.
a and 14b are formed.

A silicon oxide film 15 is formed on the entire one surface of the silicon substrate 11. Silicon oxide film 1
Silicon nitride film (SiN, Si ₃ N _4, etc.) is formed on
16 are formed. A wiring layer 17 is formed on one surface of the silicon substrate 11 and extends from the tip of each beam 13 to the outside of the frame portion of the silicon substrate 11.

The wiring layer 17 can be made of metal such as tungsten as in the first embodiment. The wiring layer 17 may be a stack of a plurality of metals or an alloy. Further, the wiring layer 17 may be composed of a single layer portion and a laminated portion.

Silicon oxide films 18 and 19 are formed on the entire other surface of the silicon substrate 11. Each bee
The frame 13 is curved to one side of the silicon substrate 11.
This is the silicon substrate 11, the silicon oxide films 15 and 19
And the thermal expansion coefficient of the wiring layer 17 near room temperature is different.

According to the above structure, the probe is composed of a silicon substrate which has been subjected to a predetermined process, as in the first embodiment. Therefore, the beam pitch can be easily made narrower than 60 μm. Also, the beam is IC
It is curved to make it easy to contact the pad of. This makes it possible to provide a novel probe that can be used for testing ICs having electrode pads with a pitch smaller than 60 μm, such as LCD drivers and ASICs.

FIG. 5 shows a probe according to the fourth embodiment of the present invention. This probe is different from the probe according to the third embodiment in the following points. That is, the probe of this embodiment has a conductive projection 22 at the tip of each beam 13.

The conductive protrusions 22 are formed on the wiring layer 1 of the probe.
This is for easily contacting the pad of 7 and the IC. Similar to the second embodiment, the projection 22 is formed by depositing a conductive film, for example, by plating the tip of the beam 13 with metal, or by adhering a conductive material to the tip of the beam 13. It can be obtained by (sputtering) and etching.

6 to 20 show a method of manufacturing a probe according to the first embodiment of the present invention. This example relates to a method of manufacturing the probe of FIG. Hereinafter, a method for manufacturing the probe will be sequentially described.

First, as shown in FIG. 6, p ⁺ type diffusion layers 14a and 14b having a depth of about 0.4 μm and an impurity concentration of about 10 ¹⁶ cm ^-2 are formed on both surfaces of the n-type silicon substrate 11. Form each. Further, thermal oxidation is performed at a temperature of about 1000 ° C. to form silicon oxide films 15 and 18 having a film thickness of about 0.1 μm on both surfaces of the silicon substrate 11. Further, a silicon nitride film (SiN, Si ₃ N _4, etc.) 16 is formed on the silicon oxide film 15 on the one surface side of the silicon substrate 11.

Next, as shown in FIG. 7, the silicon substrate 1
Photoresist 23 is applied to both sides of 1. The photoresist 23 is exposed and developed to form an opening 24 in the central portion on the other surface side of the silicon substrate 11.

Next, as shown in FIG. 8, the silicon oxide film 18 exposed in the opening 24 is removed by etching using, for example, an HF solution. In addition, for example, HF: HNO ₃ : CH ₃
The diffusion layer 14b exposed in the opening 24 is isotropically etched using a solution of COOH = 1: 3: 8, and the diffusion layer 14b in this portion is removed.

Next, as shown in FIG. 9, the silicon substrate 11 exposed in the opening 24 is anisotropically etched by using, for example, a KOH solution, and the bottom portion of the silicon substrate 11 is a diffusion layer on one surface side of the substrate. A recess reaching 14a is formed.

Next, as shown in FIG. 10, after removing the photoresist 23, thermal oxidation at a temperature of about 1000 ° C. is performed. As a result, a silicon oxide film 19 having a film thickness of about 1.0 μm is formed on the other surface side of the silicon substrate 11. The silicon nitride film 16 is formed on one surface side of the silicon substrate 11.
Since the substrate is covered with, the one surface side of the substrate is not thermally oxidized.

Next, as shown in FIG. 11, a photoresist 25 is applied to one surface side of the silicon substrate 11. The photoresist 25 is exposed and developed to form an opening 26 in the central portion on one surface side of the silicon substrate 11. This opening 26 is
It is formed symmetrically with the opening 24 provided in the photoresist 23.

Next, as shown in FIGS. 12 and 13, the silicon nitride film 16 exposed in the opening 26 is removed by etching. As a result, the pattern of the silicon nitride film 16 becomes a frame shape on the silicon substrate 11. Then, the photoresist 25 is peeled off.

Next, as shown in FIG. 14, a conductive film (eg, tungsten) is formed on the entire surface of one side of the silicon substrate 11.
27 is formed (sputtered) to about 0.4 μm. Next, FIG.
As shown in FIG. 5, photoresists 28a and 28b are applied to both surfaces of the silicon substrate 11. Photoresist 28
A and 28b are exposed and developed to form a wiring pattern on the photoresist 28a on one side of the silicon substrate 11.

Next, as shown in FIG. 16, the conductive film 27 is removed by etching using the photoresists 28a and 28b as masks, and a wiring layer having a predetermined wiring pattern is formed on one surface of the silicon substrate 11. 17 is formed.

Then, as shown in FIG. 17, the silicon oxide film 15 on one surface of the silicon substrate 11 is removed by etching using the silicon nitride film 16 and the photoresist 28a as a mask.

Next, as shown in FIGS. 18 and 19, for example, a solution of HF: HNO ₃ : CH ₃ COOH = 1: 3: 8 is used and the silicon nitride film 16 and the photoresist 28 are used.
Using a as a mask, the diffusion layer 14a on the one surface side of the silicon substrate 11 is isotropically etched, and the diffusion layer 14a at this portion is etched.
To remove. Further, the silicon oxide film 19 on the other surface side of the silicon substrate 11 is also removed by etching using the silicon nitride film 16 and the photoresist 28a as a mask.

At this time, since the silicon nitride film 16 has a frame shape and the photoresist 28a has a wiring pattern, the opening 12 is formed in the central portion of the silicon substrate 11, and A plurality of beams 13 are formed in the opening. After that, the photoresists 28a and 28b are peeled off to complete the probe of the present invention.

As shown in FIG. 20, in the probe of the present invention, the beam 13 is curved to one surface side (the wiring layer 17 side) of the silicon substrate 11 at a temperature near room temperature. This is because the thermal expansion coefficient of the wiring layer 17 is smaller than that of the silicon substrate 11 and the silicon oxide films 15 and 19. Therefore, this beam 13 can be used as a needle of the probe.

According to the above manufacturing method, a probe that can be used for testing an IC such as an LCD driver or an ASIC having an electrode pad with a pitch narrower than 60 μm can be prepared with high accuracy.

21 to 31 show a method of manufacturing a probe according to the second embodiment of the present invention. This example relates to a method of manufacturing the probe of FIG. Hereinafter, a method for manufacturing the probe will be sequentially described.

First, as shown in FIG. 21, a photoresist 29 is applied to one surface of the n-type silicon substrate 11. The photoresist 29 is exposed and developed, and the photoresist 29 is formed only on the central portion on one surface side of the silicon substrate 11.
To remain in a square shape. After that, using the photoresist 29 as a mask, for example, BF ₂ is ion-implanted into both surfaces of the silicon substrate 11, and a depth of about 0.4 μm is applied to both surfaces of the substrate.
m, p ⁺ -type diffusion layer 14 having an impurity concentration of about 10 ¹⁶ cm ^-2
a and 14b are formed respectively.

Next, as shown in FIG. 22, the temperature is about 10
Thermal oxidation is performed at 00 ° C. to form silicon oxide films 15 and 18 having a film thickness of about 0.1 μm on both surfaces of the silicon substrate 11. Further, on the silicon oxide film 15 on the one surface side of the silicon substrate 11, a silicon nitride film (SiN, Si ₃
N ₄ etc.) 16 is formed.

Next, as shown in FIG. 23, a photoresist 30 is applied to both surfaces of the silicon substrate 11. The photoresist 30 is exposed and developed to form an opening 31 in the central portion on the other surface side of the silicon substrate 11.

Next, as shown in FIG. 24, the silicon oxide film 18 exposed in the opening 31 is removed by etching using, for example, an HF solution. Further, for example, HF: HNO ₃ : CH
_The diffusion layer 14b exposed in the opening 31 is isotropically etched using a solution of ₃ COOH = 1: 3: 8, and the diffusion layer 14b in this portion is removed.

Next, as shown in FIG. 25, for example, KOH
The liquid is used to anisotropically etch the silicon substrate 11 exposed in the openings 31. As a result, a recess is formed in the silicon substrate 11, the bottom of which reaches the silicon oxide film 15 in the diffusion layer 14a on the one surface side of the substrate and in the central portion where the diffusion layer 14a is not present.

Next, as shown in FIG. 26, after removing the photoresist 23, thermal oxidation at a temperature of about 1000 ° C. is performed. As a result, a silicon oxide film 19 having a film thickness of about 1.0 μm is formed on the other surface side of the silicon substrate 11. The silicon nitride film 16 is formed on one surface side of the silicon substrate 11.
Since the substrate is covered with, the one surface side of the substrate is not thermally oxidized.

Further, a photoresist 32 is applied to one surface side of the silicon substrate 11. The photoresist 32 is exposed and developed to form an opening 33 in the central portion on one surface side of the silicon substrate 11. This opening 33 is formed in the photoresist 30.
It is formed symmetrically with the opening 31 provided in.

Next, as shown in FIG. 27, the silicon nitride film 16 exposed in the opening 33 is removed by etching. As a result, the pattern of the silicon nitride film 16 becomes a frame shape on the silicon substrate 11. After removing the photoresist 32, a conductive film (for example, tungsten) 27 having a thickness of about 0.4 μm is formed (sputtered) on the entire one surface of the silicon substrate 11.

Next, as shown in FIG. 28, photoresists 34a and 34b are applied to both surfaces of the silicon substrate 11. The photoresists 34a and 34b are exposed and developed to form a wiring pattern on the photoresist 34a on one surface of the silicon substrate 11.

Next, as shown in FIGS. 29 and 30, the conductive film 2 is formed by using the photoresists 34a and 34b as masks.
When 7 is removed by etching, a wiring layer 17 having a predetermined wiring pattern is formed on one surface side of the silicon substrate 11. Further, the silicon oxide film 15 on one surface of the silicon substrate 11 is removed by etching using the silicon nitride film 16 and the photoresist 34a as a mask.

Further, for example, HF: HNO ₃ : CH ₃ CO
Using the solution of OH = 1: 3: 8 and using the silicon nitride film 16 and the photoresist 34a as a mask, the diffusion layer 14a on the one surface side of the silicon substrate 11 is isotropically etched to remove the diffusion layer 14a in this portion. To do. The silicon oxide film 19 on the other surface side of the silicon substrate 11 is also removed by etching using the silicon nitride film 16 and the photoresist 34a as a mask.

At this time, since the silicon nitride film 16 has a frame shape and the photoresist 34a has a wiring pattern, the opening 12 is formed in the central portion of the silicon substrate 11, and A plurality of beams 13 are formed in the opening. After that, the photoresists 34a and 34b are peeled off to complete the probe of the present invention.

As shown in FIG. 31, in the probe of the present invention, the beam 13 is curved to one surface side (the wiring layer 17 side) of the silicon substrate 11 at a temperature near room temperature. This is because the thermal expansion coefficient of the wiring layer 17 is smaller than that of the silicon substrate 11 and the silicon oxide films 15 and 19. Therefore, this beam 13 can be used as a needle of the probe.

According to the above manufacturing method, a probe that can be used for testing an IC such as an LCD driver or an ASIC having an electrode pad with a pitch narrower than 60 μm can be prepared with high accuracy.

32 to 45 show a method of manufacturing a probe according to the third embodiment of the present invention. This example relates to a method of manufacturing the probe of FIG. Hereinafter, a method for manufacturing the probe will be sequentially described.

First, as shown in FIG. 32, p ⁺ type diffusion layers 14a and 14b having a depth of about 0.4 μm and an impurity concentration of about 10 ¹⁶ cm ^-2 are formed on both surfaces of the n-type silicon substrate 11. Form each. Further, thermal oxidation is performed at a temperature of about 1000 ° C., and the film thickness is about 0.1 μm on both surfaces of the silicon substrate 11.
The silicon oxide films 15 and 18 are formed respectively. Further, a silicon nitride film (SiN, Si ₃ N _4, etc.) 16 is formed on the silicon oxide film 15 on the one surface side of the silicon substrate 11.

Next, as shown in FIG. 33, a photoresist 23 is applied to both surfaces of the silicon substrate 11. The photoresist 23 is exposed and developed to form an opening 24 in the central portion on the other surface side of the silicon substrate 11.

Next, as shown in FIG. 34, the silicon oxide film 18 exposed in the opening 24 is removed by etching using, for example, an HF solution. Further, for example, HF: HNO ₃ : CH
_The diffusion layer 14b exposed in the opening 24 is isotropically etched using a solution of ₃ COOH = 1: 3: 8, and the diffusion layer 14b in this portion is removed.

Next, as shown in FIG. 35, for example, KOH
The liquid is used to anisotropically etch the silicon substrate 11 exposed in the openings 24 to form a recess in the silicon substrate 11 whose bottom reaches the diffusion layer 14a on one surface side of the substrate.
Then, the photoresist 23 is peeled off.

Next, as shown in FIG. 36, the temperature is about 10
Perform thermal oxidation at 00 ° C. As a result, on the other surface side of the silicon substrate 11, a silicon oxide film 19 having a thickness of about 1.0 μm is formed.
Is formed. Since the one surface side of the silicon substrate 11 is covered with the silicon nitride film 16, the one surface side of the substrate is not thermally oxidized.

Next, as shown in FIG. 37, a conductive film (for example, tungsten) is formed on the entire surface of one side of the silicon substrate 11.
27 is formed (sputtered) to about 0.4 μm. Next, FIG.
As shown in FIG. 8, a photoresist 35 is applied to one surface side of the silicon substrate 11. Expose the photoresist 35,
Develop and photoresist 3 on one side of silicon substrate 11
A wiring pattern is formed at 5.

Next, as shown in FIGS. 39 and 40, when the conductive film 27 is removed by etching using the photoresist 35 as a mask, a wiring having a predetermined wiring pattern is formed on one surface of the silicon substrate 11. Layer 17 is formed. Further, using the photoresist 35 as a mask, the silicon nitride film 16 and the silicon oxide film 15 on the one surface side of the silicon substrate 11 are removed by etching. Then, the photoresist 35 is peeled off.

Next, as shown in FIGS. 41 and 42, photoresist 36a, again on both surfaces of the silicon substrate 11 is formed.
Apply 36b. The photoresists 36a and 36b are exposed and developed to form an opening 37 in the central portion on one surface side of the silicon substrate 11. This opening 37 is formed in the photoresist 23.
It is formed symmetrically with the opening 24 provided in the.

Next, as shown in FIGS. 43 and 44, for example, a solution of HF: HNO ₃ : CH ₃ COOH = 1: 3: 8 is used and the wiring layer 17 and the photoresist 36a are used as a mask to form a silicon substrate. The diffusion layer 14a on the one surface 11 is isotropically etched to remove the diffusion layer 14a in this portion. Further, the silicon oxide film 19 on the other surface side of the silicon substrate 11 is also removed by etching using the wiring layer 17 and the photoresist 36a as a mask.

At this time, since the photoresist 28a has a frame shape, the opening 1 is formed at the center of the silicon substrate 11.
2 is formed, and a plurality of beams 1 are formed in the opening.
3 is formed. After this, the photoresists 36a, 36
By peeling off b, the probe of the present invention is completed.

As shown in FIG. 45, in the probe of the present invention, the beam 13 is curved to one surface side (the wiring layer 17 side) of the silicon substrate 11 at a temperature near room temperature. This is because the thermal expansion coefficient of the wiring layer 17 is smaller than that of the silicon substrate 11 and the silicon oxide films 15 and 19. Therefore, this beam 13 can be used as a needle of the probe.

According to the above manufacturing method, a probe that can be used for testing an IC such as an LCD driver or an ASIC having an electrode pad with a pitch narrower than 60 μm can be prepared with high accuracy.

46 to 56 show a method of manufacturing a probe according to the fourth embodiment of the present invention. This example relates to a method of manufacturing the probe of FIG. Hereinafter, a method for manufacturing the probe will be sequentially described.

First, as shown in FIG. 46, a photoresist 29 is applied to one surface of the n-type silicon substrate 11. The photoresist 29 is exposed and developed, and the photoresist 29 is formed only on the central portion on one surface side of the silicon substrate 11.
To remain in a square shape. After that, using the photoresist 29 as a mask, for example, BF ₂ is ion-implanted into both surfaces of the silicon substrate 11, and a depth of about 0.4 μm is applied to both surfaces of the substrate.
m, p ⁺ -type diffusion layer 14 having an impurity concentration of about 10 ¹⁶ cm ^-2
a and 14b are formed respectively.

Next, as shown in FIG. 47, the temperature is about 10
Thermal oxidation is performed at 00 ° C. to form silicon oxide films 15 and 18 having a film thickness of about 0.1 μm on both surfaces of the silicon substrate 11. Further, on the silicon oxide film 15 on the one surface side of the silicon substrate 11, a silicon nitride film (SiN, Si ₃
N ₄ etc.) 16 is formed.

Next, as shown in FIG. 48, a photoresist 30 is applied to both surfaces of the silicon substrate 11. The photoresist 30 is exposed and developed to form an opening 31 in the central portion on the other surface side of the silicon substrate 11.

Next, as shown in FIG. 49, the silicon oxide film 18 exposed in the opening 31 is removed by etching using, for example, an HF solution. Further, for example, HF: HNO ₃ : CH
_The diffusion layer 14b exposed in the opening 31 is isotropically etched using a solution of ₃ COOH = 1: 3: 8, and the diffusion layer 14b in this portion is removed.

Next, as shown in FIG. 50, for example, KOH
The liquid is used to anisotropically etch the silicon substrate 11 exposed in the openings 31. As a result, the silicon substrate 11 is formed with a recess whose bottom reaches the silicon oxide film 15 in the diffusion layer 14a on the one surface side of the substrate and in the central portion where the diffusion layer 14a is not present. Then, the photoresist 23 is peeled off.

Next, as shown in FIG. 51, the temperature is about 10
Perform thermal oxidation at 00 ° C. As a result, on the other surface side of the silicon substrate 11, a silicon oxide film 19 having a thickness of about 1.0 μm is formed.
Is formed. Since the one surface side of the silicon substrate 11 is covered with the silicon nitride film 16, the one surface side of the substrate is not thermally oxidized.

Next, as shown in FIG. 52, a conductive film (for example, tungsten) is formed on the entire one surface of the silicon substrate 11.
27 is formed (sputtered) to about 0.4 μm. Next, FIG.
As shown in FIG. 3, photoresists 34a and 34b are applied to both surfaces of the silicon substrate 11. Photoresist 34
A and 34b are exposed and developed to form a wiring pattern on the photoresist 34a on one surface of the silicon substrate 11.

Next, as shown in FIGS. 54 and 55, the conductive film 2 is formed by using the photoresists 34a and 34b as masks.
When 7 is removed by etching, a wiring layer 17 having a predetermined wiring pattern is formed on one surface side of the silicon substrate 11. Further, the silicon oxide film 15 on one surface of the silicon substrate 11 is removed by etching using the silicon nitride film 16 and the photoresist 34a as a mask.

Further, for example, HF: HNO ₃ : CH ₃ CO
Using the solution of OH = 1: 3: 8 and using the silicon nitride film 16 and the photoresist 34a as a mask, the diffusion layer 14a on the one surface side of the silicon substrate 11 is isotropically etched to remove the diffusion layer 14a in this portion. To do. The silicon oxide film 19 on the other surface side of the silicon substrate 11 is also removed by etching using the silicon nitride film 16 and the photoresist 34a as a mask.

As a result, the opening 12 is formed in the central portion of the silicon substrate 11, and a plurality of beams 13 are formed in the opening. After this, photoresist 3
By peeling 4a and 34b, the probe of the present invention is completed.

As shown in FIG. 56, in the probe of the present invention, the beam 13 is curved to one surface side (the wiring layer 17 side) of the silicon substrate 11 at a temperature near room temperature. This is because the thermal expansion coefficient of the wiring layer 17 is smaller than that of the silicon substrate 11 and the silicon oxide films 15 and 19. Therefore, this beam 13 can be used as a needle of the probe.

According to the above manufacturing method, a probe that can be used for testing an IC such as an LCD driver or an ASIC having an electrode pad with a pitch narrower than 60 μm can be prepared with high accuracy.

[0090]

INDUSTRIAL APPLICABILITY As described above, according to the present invention,
According to Bu, the following effects are produced. That is, since the probe of the present invention is composed of a silicon semiconductor,
It can be formed using a conventional silicon LSI process. Therefore, it is possible to provide a probe needle with extremely high accuracy. Further, a probe card that can be used for an IC having a pad with a pitch of 60 μm or less can be provided at a low price. The beam according to the present invention is a silicon L
Since it is formed by the SI process, the thickness of each beam can be controlled with high accuracy. Therefore, the curvature of the beam can be made highly accurate with little variation among the beams.

[Brief description of drawings]

FIG. 1 is a diagram showing a probe according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a probe of the present invention and an IC for testing.

FIG. 3 is a diagram showing a probe according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a probe according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a probe according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a method of manufacturing a probe according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a method of manufacturing a probe according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a method of manufacturing a probe according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a method of manufacturing a probe according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 12 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 15 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 16 is a diagram showing a method of manufacturing a probe according to the first embodiment of the present invention.

FIG. 17 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 18 is a diagram showing a method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 19 is a view showing the method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 20 is a view showing the method of manufacturing the probe according to the first embodiment of the present invention.

FIG. 21 is a diagram showing a method of manufacturing a probe according to the second embodiment of the present invention.

FIG. 22 is a view showing a method for manufacturing a probe according to the second embodiment of the present invention.

FIG. 23 is a diagram showing a method of manufacturing a probe according to a second embodiment of the present invention.

FIG. 24 is a diagram showing a method of manufacturing a probe according to the second embodiment of the present invention.

FIG. 25 is a view showing the method of manufacturing the probe according to the second embodiment of the present invention.

FIG. 26 is a view showing a method of manufacturing a probe according to the second embodiment of the present invention.

FIG. 27 is a view showing the method of manufacturing the probe according to the second embodiment of the present invention.

FIG. 28 is a diagram showing a method of manufacturing a probe according to the second embodiment of the present invention.

FIG. 29 is a view showing the method of manufacturing the probe according to the second embodiment of the present invention.

FIG. 30 is a diagram showing a method of manufacturing the probe according to the second embodiment of the present invention.

FIG. 31 is a view showing a method for manufacturing a probe according to the second embodiment of the present invention.

FIG. 32 is a view showing a method for manufacturing a probe according to the third embodiment of the present invention.

FIG. 33 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 34 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 35 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 36 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 37 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 38 is a diagram showing a method of manufacturing a probe according to the third embodiment of the present invention.

FIG. 39 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 40 is a diagram showing a method of manufacturing a probe according to the third embodiment of the present invention.

FIG. 41 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 42 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 43 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 44 is a view showing the method of manufacturing the probe according to the third embodiment of the present invention.

FIG. 45 is a diagram showing a method of manufacturing a probe according to the third embodiment of the present invention.

FIG. 46 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 47 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 48 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 49 is a view showing the method for manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 50 is a view showing the method for manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 51 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 52 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 53 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 54 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 55 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 56 is a view showing the method of manufacturing the probe according to the fourth embodiment of the present invention.

FIG. 57 is a view showing a conventional probe card.

FIG. 58 is an enlarged view of the tip of the probe needle of the conventional probe card.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Opening, 13 ... Beam (beam-shaped projection), 14a, 14b ... Diffusion layer, 15, 18, 19 ... Silicon oxide film, 16 ... Silicon nitride film, 17 ... Wiring layer, 20 ... semiconductor chip, 21 ... pad, 22 ... conductive protrusion, 23, 25, 28a, 28b, 29, 30, 32, 34
a, 34b, 35, 36a, 36b ... Photoresist, 24, 26, 31, 33, 37 ... Opening, 27 ... Conductive film.

Claims (4)

[Claims] 1. A plurality of beams having two main surfaces and an opening formed in a central portion, projecting from one main surface side to the opening, and curved to the one main surface side. A semiconductor substrate having the same, a wiring layer formed on one main surface of the semiconductor substrate via a first insulating film, and extending from a tip portion of each beam to an outer peripheral portion of the semiconductor substrate; A second insulating film formed on the other main surface of the semiconductor substrate. 2. The plurality of beams are regularly arranged so that the tip portions thereof correspond to the arrangement of electrodes on the semiconductor chip, and the tip portions of the plurality of beams are arranged on the semiconductor chip. The probe according to claim 1, wherein the probe is capable of contacting the electrode. 3. The two main surface regions of the semiconductor substrate are formed with diffusion layers each containing a predetermined concentration of impurities and having a predetermined depth. Probe. 4. The probe according to claim 1, wherein conductive projections are formed at the tip ends of the plurality of beams.