JPH07141891A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the obtaining of high integration by adopting prescribed program realizing means respectively in a decoder part and a memory part in a semiconductor memory of a type programming both the decoder part and the memory part. CONSTITUTION:A semiconductor memory is classified into a decoder part 100 and a memory part 200. Transistors 101 constituting the decoder part are formed by a diffusion layer 150 and a polysilicon layer 160 and the layer 160 is extended to the upper part of the center part of the layer 150 to form gates 101a. Data lines 110 to 140 are formed on a substrate layer consisting of the layers 150, 160 and the layer 160 is connected with any one of lines 110 to 140 by hitting one of first contacts shown with rectangles. The decoder part 100 is programed by on which line of lines 110 to 140 a contact is hitted. Further, many transistors are provided in the memory part 200 and whether respective transistors are connected with bit lines 210 or not are programmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory of a type in which, at the time of manufacture, both the stored contents of the memory unit and the correspondence between input data and addresses of the memory unit are programmed based on, for example, specifications from a user. Regarding

[0002]

2. Description of the Related Art Conventionally, various semiconductor memories have been widely used. As one application example of the semiconductor memory, the applicant of the present application has proposed a first input section for inputting a bit pattern from the outside and the semiconductor memory. A second input unit is provided which has a latch circuit for latching a bit pattern forming a part of the read content and which inputs the latched bit pattern to the latch circuit. By decoding the bit pattern input from both the input unit 2 and the input unit 2, the memory area in which the content to be read next is stored from the predetermined memory area in which the predetermined content is stored. An encoding device provided with a decoder unit for selection has been proposed (Japanese Patent Application No. 4-87219).

The coding apparatus according to this proposal allows a plurality of texts to be re-appeared and is arranged in a tree structure in an ideal manner.
This is a device to which a semiconductor memory is applied, which obtains a code number that is predetermined according to the sequence order of the text. The background art of the present invention will be described below with reference to this encoding device.

[0004]

[Table 1]

[0005]

[Table 2]

Table 1 shows each text T0, T1, T2, T
3 is a correspondence table of 3 bits and a text code consisting of 2 bits which is equated with each of these texts T0, T1, T2 and T3. Table 2 shows a text chain in which the texts are arranged and the text chain. It is a correspondence table with the generated code numbers. The 10-bit chain code is a code number represented by a binary code.

Here, first, the data structure handled by the encoding apparatus according to the above proposal will be described. Figure 8
It is a figure showing an example of the text arranged in the tree structure. In this figure, the numbers in parentheses represent the node numbers given to each node. First, two branches extend from the node (vertex) with the node number (0) at the top of the figure,
Texts T0 and T1 are arranged at the nodes at the ends of the branches. Of these, the code number C1 is attached to the node of the node number (1) in which the text T0 is arranged,
On the other hand, no code number is given to the node having the node number (2) in which the text T1 is arranged. Three branches further extend from the node of the node number (1) where the text T0 is arranged among these nodes, and the texts T0, T1, and T3 are arranged at the nodes at the ends of these three branches, respectively. Has been done. Moreover, code numbers C3, C4, and C5 are assigned to the respective nodes. Two branches further extend from the node of the node number (3) in which the text T0 is arranged among these nodes, and
Texts T1 and T2 are arranged at the nodes with node numbers (8) and (9) at the end of the book branch, respectively, and code numbers C8 and C9 are given to these nodes, respectively. Two branches extend from the node of the node number (2) where the text T1 is arranged, and the texts T0 and T2 are arranged at the nodes at the ends of these two branches, respectively. Among these, the code number C is assigned to the node of the node number (7) where the text T2 is arranged.
7 is attached. Furthermore, these texts T0, T2
One and two branches respectively extend from the node in which the text T0 is arranged, and the text T0 is included in the node at the node number (10) at the end of the branch extending from the node in which the text T0 is arranged in the node number (6). Is placed, and the code number is C10.
Is attached to each node of node numbers (11) and (12) at the ends of the two branches extending from the node of node number (7) in which the text T2 is placed. T3 is arranged, and code numbers C11 and C12 are given to these respective nodes.

Here, the encoding method using the tree-structured data will be specifically described as follows. First, consider the case where the text chain T0 → T1 is input. At this time, the desired output chain code is '0000000100' as defined in Table 2.
Is.

To obtain this result, first the text T0
The text code '00' corresponding to is input. The text T0 on the tree structure is arranged at the node at the branch destination of the node number (0) (node number (0) is the first node number of encoding). Text T connected to the end of the branch extending from the node with node number (0)
Although there is only one 0, there are some other nodes in which the text T0 is arranged, which are connected to nodes other than the node with the node number (0).

Therefore, here, in order to recognize that the text input to this tree structure data is the first text T0 of the tree structure, this text data '00' is used.
In addition to that, node number (0) (data '000
0 ') is searched. The text T at the end of this branch
Although the code number C1 (chain code '0000000001') is given to the node in which 0 is arranged,
This time it is not the code number that should be requested.

Next, when the text data "01" corresponding to the text T1 is input, the node number (1) (data "0001") of the text T0 immediately before the text data "01" and the text data "01" input this time are input. The tree structure database is searched by both. As a result, it is possible to clearly distinguish the text T1 at the other branch end and the text T1 at the branch end of the node with the node number (1).

Thus, the branch of the text chain T0 → T1 is determined, and the code number C4 (chain code '00000000100') attached to the tip of this T1 branch is output as the code number to be obtained. Similarly, any chain code C1, ... Defined in Table 1
..., C12 can be obtained. The encoding device according to the above proposal is an effective device for handling tree-structured data as shown in FIG. 8. Each node of the tree structure is given a node number, and the input text and the current position are added. It is configured to obtain the node to be moved to the next based on the node number of the node that performs the process. For this reason, even if a large number of branches extend from the node currently located, unlike a case where these branches are searched sequentially, a node that should immediately advance to the next is found in one search operation, and therefore the text chain is extremely It has the feature of being converted into a code number in a short time.

FIG. 9 is a diagram showing an example of the encoding device according to the above-mentioned proposal. The decoder unit 20 of this encoding device has text data input terminals TD0, TD1 (first input unit) and node number input terminals ND0, ND1, ND.
2 and ND3 are provided. The data input from the node number input terminals ND0, ND1, ND2, ND3 are input to the node number setting circuit 22. Further, the node number data output 26 from the memory section 25 is also connected to the node number setting circuit 22, and the input is switched by the input switching terminal SW.

The number written at the leftmost end of the decoder unit 20 is the node number (1) of each node of the tree structure shown in FIG.
(2), (3), ..., (12) are represented. For example, the node number (1) in the bottommost row represents the node in which the text T0 is arranged in the upper row of the tree structure data in FIG. In the decoder unit 20, the text data input terminal TD extending in the left-right direction up to the match detection circuit 21 and the line segment corresponding to each node and extending in the vertical direction.
0, data line from TD1 and node number setting circuit 2
The data lines from 2 intersect. A black circle is displayed at this intersection when the data on the data line is the normal data "1", and when there is no black circle when the data on the data line is the inverted data "0". The output of the detection circuit 21 is configured to be "1" (active). That is, in the case of the node number (1), when all the outputs from the text data input terminals TD0 and TD1 and the node number setting circuit 22 are "0", the output of the match detection circuit 21 corresponding to the node number (1) is It becomes "1".

Here, in the node number setting circuit 22,
Node number (0) of the vertex node shown in (data '00
00 ') is set and the data' 00 'of the text T0 is inputted from the text data input terminals TD0 and TD1 in that state, the output of the coincidence detection circuit 21 corresponding to the node number (1) becomes'1'. Become. Then, the lowermost row of the memory unit 25 on the right side of the figure becomes active, and the output of the output circuit 28 connected to the intersection where the white circle 27 exists becomes "1". Specifically, from the node number data output 26 to '0
001 ', code valid bit output 29 to' 1 ',
And chain code data output 30 to '00000
00001 'is output. Here, the code valid bit output 29 indicates whether the data output from the chain code output 30 is valid or invalid, that is, the node with the node number output from the node number data output 26 has a code number It indicates whether or not it is attached. Here, this code valid bit output 29 is'
Since it is 1 ', the data output from the chain code data output 30 is valid, but the data output from the chain code output 30 is not used as the code number to be obtained here. The data “0001” output from the node number data output 26 is input to the node number setting circuit 22.

Next, the text data input terminals TD0, T
When the data '01' of the text T1 is input to D1,
Since the output of the node number setting circuit 22 is the value "0001" from the previous search result of the text T0, the input of the decoder unit 20 is "010001" this time.
The match in this pattern is the node number (4) in which the text T1 is arranged (see FIG. 8). As a result, the output of the match detection circuit 21 corresponding to the node number (4) is'
1 ', and the fourth row from the bottom of the memory section 25 becomes active. Therefore, the code valid bit output is'
1 ', chain code data output is'00000001'
00 ', and finally this chain code is obtained as a code number. At this time, node number data "0100" is obtained at the same time, but this is not used here.

As described above, by referring to both the input data and the node number, even when a large number of branches are branched from each node, high-speed search and match comparison are performed, and encoding is performed. The speedup of is realized. FIG. 10 is a circuit diagram showing a part of the encoding device shown in FIG.
1 is a circuit diagram in which the circuit shown in FIG. 10 is further embodied. 10 and 11, the output of the coincidence detection circuit 21 becomes "1" for the input data of "110111" (text data "11" and the output from the node number setting circuit 22 is "0111"). , The node number (1
It is a circuit diagram corresponding to 2).

As shown in FIG. 11, the decoder section 20 includes
6 transistors Tr connected to each other in series
The data lines DL1, DL2, DL3, DL4, DL are respectively connected to the gates of 1, Tr2, Tr3, Tr4, Tr5, Tr6.
5, DL6 or each data bar line DBL1, DBL
Any one of 2, DBL3, DBL4, DBL5 and DBL6 is connected. Further, precharging transistors Tr10 and Tr11 are provided at two locations, and the transistor Tr10 is a P-channel transistor for precharging the potential at the point A. The transistor Tr11 is an N-channel transistor provided between the transistor Tr1 and the ground line, and suppresses discharge of the potential at the point A during precharge. The coincidence detection circuit 21 includes an inverter 20 'and a feedback type P.
A channel transistor Tr12 is provided.

In the memory section 25, the inverter 2
The output of 0'is the memory transistors MTr1 and MTr.
2, the gates of MTr3 and MTr4 are connected.
These memory transistors MTr1, MTr2, MTr
One of the data output lines DOL3, DO
The other of L4, DOL5, and DOL6 is connected to the ground line.

Further, the respective data output lines DOL1, ...
, DOL15 has precharge channel transistors Tr1, ..., PTr15 at one end, and an inverter 21 'and a feedback P-channel transistor Tr13 at the other end. First, the precharge control terminal 31 for initialization is set to '
When 0'is applied, the potential at the point A is set to '1'.
Along with this, the output of the coincidence detection circuit 21, which is the inverter output of the point A potential, becomes "0". When the output of the coincidence detection circuit 21 becomes "0", the memory transistors MTr1, MTr2, MTr3, MTr4 are turned off, and when "0" is applied to the precharge control terminal 31, the precharge P The channel transistors PTr1, ..., PTr15 are turned on, the respective data output lines DOL1, ..., DOL15 maintain the state of "1", and the output of the inverter 21 ', which is an inverted output thereof, is "1".
Keep 0'state. At this time, the code valid bit output also outputs "0". By this signal output, it can be known that the output of the chain code data is invalid data.

Then, the text data input terminals TD0,
When desired input data is applied from TD1 and the output from the node number setting circuit 22 is determined, and then "1" is applied to the precharge control terminal 31, the search state is entered. By repeating the initialization state and the search state in synchronization with the application of each input data, a desired chain code data, that is, a code number can be obtained.

The above is an example of the encoding apparatus according to the above proposal.

[0023]

In the above encoding device,
The address of the input data and the memory unit, which of the coincidence detection circuits 21 is activated depending on the stored content of the memory unit 25 and the value of the input data (text data + node number) input to the decoder unit 20. Both of the correspondence relations with and will be programmed based on, for example, specifications from the user when manufacturing the encoding device.

By the way, in the case of an ordinary semiconductor memory, a so-called mask R is a generally used conventional method for programming the memory contents in the memory portion at the time of manufacture.
This is a method called OM. On the other hand, in the case of a normal semiconductor memory, it has been common sense that the decoder section has its wiring fixed because address data is input from the outside. Therefore, for example, in a semiconductor memory having a user-programmable decoder unit such as the above-mentioned encoding device, a program realizing means for determining a method for programming the storage contents of both the decoder unit and the memory unit has been established. Absent. It is preferable to adopt a program realizing means that is as highly integrated as possible. However, since the decoder section needs to detect the coincidence between the externally input data and the stored data, the content stored in the decoder section It is an absolute requirement that the program realizing means of (1) be capable of performing coincidence comparison, and the coincidence detection itself cannot be performed by the program realizing means employed in the mask ROM.

In view of the above circumstances, it is an object of the present invention to provide a highly integrated semiconductor memory of the type in which both the decoder section and the memory section are programmed during manufacturing.

[0026]

According to a first semiconductor memory of the present invention which achieves the above object, (1) a predetermined memory content is programmed according to whether or not a diffusion layer is formed under a gate. A memory unit having a large number of bits of memory cells and having a large number of memory areas to which respective addresses are added. (2) A predetermined address corresponding to input data from the large number of addresses to the large number of memory areas. The correspondence between the input data and the address is that the contact connecting between the plurality of wiring layers stacked via the insulating layer, the underlying layer on which the transistor is formed, and the insulating layer on the underlying layer are used. And a decoder section programmed by a predetermined contact selected from the contacts connecting between the first wiring layer and the stacked first wiring layer. That.

In addition, the second semiconductor memory of the present invention is, instead of the above-mentioned (1) of the first semiconductor memory, (3) forming an enhancement type transistor which turns on / off according to a gate potential, or has a source gate. Even if the voltage between them is 0 (V), the memory content is programmed by forming a depletion type transistor that maintains the ON state, and a large number of memory cells each having an address and having a predetermined number of bits are programmed. It is characterized by comprising a memory section having a memory area.

Further, the third semiconductor memory of the present invention is
In place of the above (1) of the first semiconductor memory, (4) forming an enhancement type transistor that turns on and off according to a gate potential, or always maintaining an off state even if the gate potential fluctuates within the power supply voltage. High V _TH
It is characterized by comprising a memory section having a predetermined number of bits of which memory contents are programmed by forming a type transistor and having a large number of memory areas to which respective addresses are assigned.

[0029]

The semiconductor memory of the present invention is a semiconductor memory of a type that is programmed by both the decoder section and the memory section. In the memory section, (a) depending on whether or not a diffusion layer is formed under the gate, Alternatively, (b) an enhancement type transistor that turns on and off according to the gate potential is formed, or the voltage between the source and gate is 0.
Depending on whether to form a depression type transistor that maintains the ON state even at (V), or (c)
The memory content is programmed by forming an enhancement type transistor that turns on and off according to the gate potential, or by forming a high V _TH type transistor that always maintains the off state even when the gate potential fluctuates within the power supply voltage. Therefore, high integration of the memory portion is achieved, and thus high integration of the entire semiconductor memory is achieved.

When the above (a) or (c) is adopted, the processing speed can be increased. Further, the semiconductor memory of the present invention is a semiconductor memory of a type in which both a decoder section and a memory section are programmed, and in the decoder section, a contact connecting a plurality of wiring layers laminated via an insulating layer, and a transistor. The above memory is programmed by a predetermined contact selected from the contacts connecting between the underlying layer on which is formed and the first wiring layer laminated on the underlying layer via an insulating layer. Although it is not as highly integrated as a part, a high speed coincidence comparison operation can be performed.

The semiconductor memory of the present invention is highly integrated as a whole by the combination of the program implementing means of the memory section and the decoder section described above, and can operate at a relatively high speed.

[0032]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 3 is a conceptual diagram of a semiconductor memory according to an embodiment of the present invention. The entire semiconductor memory is configured, for example, as shown in FIGS. 9 to 11, but here, only a part necessary for the following description is conceptually shown.

This semiconductor memory is roughly divided into a decoder section 100 and a memory section 200. A plurality of transistors 101 are connected in series to the decoder section 100, and four data lines 110, 120, 130, 140 extend to each transistor 101 in this embodiment. These four data lines 110, 120, 130, 14
Which data line of 0 is connected to the gate 101a is programmed. Further, the memory section 200 is provided with a large number (only two are shown in FIG. 1) of the cell transistors 201.
It is programmed whether or not each of them is connected to the bit line 210 extending vertically in FIG. Alternatively, the large number of cell transistors 201 are all connected to the bit line 210 and programmed by changing the threshold values of the cell transistors 201.

First, the program realizing means of the decoder section will be described below. FIG. 2 is a diagram showing a layout of transistors in the decoder section when programming is performed by the first contact. The transistor 101 forming the decoder section is formed by the diffusion layer 150 and the polysilicon layer 160 having the shape shown in FIG.
The polysilicon layer 160 extends above the center of the diffusion layer 150 to form the gate 101a.

Four data lines 110, 12 forming a first wiring layer are laminated on an underlying layer formed of the diffusion layer 150 and the polysilicon layer 160 with an insulating layer (not shown) interposed therebetween.
0, 130, 140 are formed so as to extend in the vertical direction in the figure, and by hitting one of the first contacts indicated by a rectangle in the figure, these four data lines 110, 12 are formed.
Any one of the data lines 0, 130 and 140 is connected to the polysilicon layer 160. Decoder section 10
0 (see FIG. 1), each of four data lines 110, 120, 13 extending to a large number of transistors 101.
The decoder unit 100 is programmed depending on which of 0 and 140 contacts are made.

FIG. 3 is a diagram showing a layout of transistors in the decoder section when programming is performed by the second contact. For ease of understanding, components corresponding to the components such as the transistor shown in FIG. 2 are denoted by the same reference numerals regardless of differences in shape, wiring layer, or the like. Transistor 10 that constitutes the decoder unit 100 (see FIG. 1)
1 is formed of a diffusion layer 150 and a polysilicon layer 160 which plays the role of the gate 101a. An insulating layer (not shown) is formed on the base layer composed of the diffusion layer 150 and the polysilicon layer 160. The first wiring layer 170 is laminated via the. The first wiring layer 170 and the polysilicon layer 160 are connected by a first contact indicated by a rectangle in the figure. On the first wiring layer 170, four data lines 110, 120, 130, through an insulating layer (not shown),
140 is formed as the second wiring layer. Any one of these four data lines 110, 120, 130, 140 is connected to the first wiring layer 170 by a second contact indicated by a circle in the figure according to the program.

Next, the program realizing means of the memory section will be described. FIG. 4 is a diagram showing a layout of transistors in the memory section when programming is performed depending on whether or not a diffusion layer is formed under the gate. The cell transistor 201 forming the memory portion shown in FIG. 4 includes a diffusion layer 250 extending in the left-right direction of the drawing and having a convex shape in the vertical direction of the drawing as necessary, a gate 201a of the cell transistor 201, and a word line. It is formed of a polysilicon layer 260 which also has a role to extend in the left-right direction in the drawing. A portion of the diffusion layer 250 extending in the left-right direction in the drawing is connected to the ground GND.

A bit line 210, which is a first wiring layer and is laminated on an underlying layer formed of the diffusion layer 250 and the polysilicon layer 260 with an insulating layer (not shown), extends in the vertical direction of the drawing. The first contact, which is formed and has a rectangular shape in the figure, electrically connects the bit line 210 to the convex portion of the diffusion layer 250. Here, of the four polysilicon layers 260 shown, the gates 20 of the two polysilicon layers 260 at the top and bottom are shown.
The diffusion layer 250 is formed in the lower layer of 1a, but the diffusion layer 250 is not formed in the lower layer of the gate 201a of the two polysilicon layers 260 in the center. Gate 201a
If the diffusion layer 250 is not formed under the gate,
Regardless of the potential of 01a, the diffusion layers 250 on both sides of the gate 201a are not electrically connected. As described above, in the example shown in FIG. 4, bit information of logic '0' and logic '1' is programmed in each cell transistor 201 depending on whether or not a diffusion layer is formed below the gate 201a.

FIG. 5 shows whether to form an enhancement type transistor which turns on and off according to the gate potential or a high V _TH type transistor which always maintains the off state even when the gate potential fluctuates within the power supply voltage. FIG. 6 is a diagram showing a layout of transistors in a memory section when programming is performed. For the sake of clarity, constituent elements corresponding to the constituent elements such as the transistors shown in FIG. 4 are denoted by the same reference numerals regardless of differences in shape and the like.

Under the gate 201a of the cell transistor 201 shown in FIG. 5, a diffusion layer 250 is formed for all the gates 201a. However, regarding some of those cell transistors 201, the other transistors 2
01, the concentration of ions implanted in the diffusion layer 250 below the gate 201a is different, and the threshold value V is set so that the gate 201a does not become conductive even when a voltage within the power supply voltage is applied.
_TH is set to a high value. As described above, in the example shown in FIG. 5, by controlling the ion concentration,
Depending on whether each cell transistor 201 is formed as an enhancement type transistor that turns on and off according to the gate potential or as a high V _TH type transistor that always maintains the off state even when the gate potential changes within the power supply voltage, each cell transistor 201 The transistor 201 has a logic "0",
Bit information of logic '1' is programmed.

FIG. 6 shows whether to form an enhancement type transistor which turns on / off according to the gate potential or a depletion type transistor which maintains an on state even when the voltage between source and gate is 0 (V). FIG. 6 is a diagram showing a layout of transistors in a memory section when programming is performed. The components corresponding to the components such as the transistors shown in FIGS.
For the sake of clarity, the same numbers are given and shown regardless of differences in shape and the like.

FIG. 7 is an equivalent circuit diagram of the transistor shown in FIG. A cell transistor 201 included in the memory section 200 (see FIG. 1) shown in FIG. 6 also serves as a diffusion layer 250 extending in a strip shape in the left, right, top and bottom of the drawing, a gate 201a of the cell transistor 201, and a word line. It is formed by a polysilicon layer 260 extending to the left and right in the figure. A portion of the diffusion layer 250 extending in a strip shape in the left-right direction in the drawing is connected to the ground GND. A bit line 210, which is a first wiring layer and is laminated via an insulating layer (not shown), is formed on the underlying layer including the diffusion layer 250 and the polysilicon layer 260 so as to extend in the vertical direction of the drawing. Therefore, the bit line 210 and the uppermost portion of the diffusion layer 250 shown in the drawing are electrically connected by the first contact shown by the rectangle in the drawing.

Here, as shown in FIG. 7, the diffusion layer 25
A plurality of cell transistors 201 are connected in series between a portion of 0, which is connected to the bit line 201 by the first contact, and the diffusion layer, which is the ground GND. By controlling the ion implantation concentration in the diffusion layer 250 below the gate 201a, those cell transistors 201
Is formed as an enhancement type transistor that is turned on / off according to the potential of the gate 201a, and the remaining cell transistor 201 is
It is formed as a depletion type transistor that maintains an on state even when the potential between the source and the source is 0 (V).

Therefore, of the plurality of word lines, when the selected word line 260 is set to logic "0" and the other unselected word lines 260 are set to logic "1", the unselected word line 26
The cell transistor 201 connected to 0 is turned on regardless of the depletion type or the enhancement type. However, when the cell transistor 201 connected to the selected word line 260 is the enhancement type, the cell transistor 201 does not conduct and the bit is turned on. The charge on line 210 is not discharged.

On the other hand, if the cell transistor 201 connected to the selected word line 260 is a depletion type, the cell transistor 201 becomes conductive and the bit line 2
10 is discharged. As described above, in the example shown in FIG. 6, depending on whether the cell transistor 201 is formed as an enhancement type transistor or a depletion type transistor, the bit information of logic “0” and logic “1” is given to each cell transistor 201. Programmed.

In the example shown in FIGS. 4 and 5, it is necessary to make 1/2 contacts for each word line 260, but in the example shown in FIG. 6, one contact is made for each bit line 210. Therefore, in the case of the example shown in FIG. 6, higher integration can be achieved as compared with the examples shown in FIGS. However, in the case of the example shown in FIG. 6, since the charge of the bit line 210 is discharged via the plurality of cell transistors 201 connected in series, it takes time to discharge, and therefore, in terms of high-speed operation, FIG. However, it does not reach the example shown in FIG.

As shown in each of the above embodiments, the decoder section is programmed by the first contact or the second contact for high-speed coincidence comparison, and the memory section is programmed with high integration. By adopting the realization means, the semiconductor memory as a whole can be highly integrated.

[0048]

As described above, the semiconductor memory of the present invention is a semiconductor memory of a type in which both the decoder section and the memory section are programmed, and the predetermined program realizing means is adopted for the decoder section and the memory section. Therefore, the semiconductor memory as a whole can be highly integrated.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a layout diagram of transistors in a decoder section when programming is performed by the first contact.

FIG. 3 is a layout diagram of transistors in a decoder section when programming is performed with a second contact.

FIG. 4 is a diagram showing a layout of transistors in a memory section when programming is performed depending on whether or not a diffusion layer is formed under a gate.

FIG. 5 shows a memory portion of a memory portion when programming is performed by forming an enhancement type transistor that turns on and off according to a gate potential or a high V _TH type transistor that maintains an off state regardless of a gate potential. It is the figure which showed the layout of the transistor.

FIG. 6 shows a case where programming is performed by forming an enhancement type transistor that turns on and off according to a gate potential or by forming a depletion type transistor that maintains an on state regardless of a gate potential.
FIG. 6 is a diagram showing a layout of transistors in a memory section.

FIG. 7 is an equivalent circuit diagram of FIG.

FIG. 8 is a diagram showing an example of text arranged in a tree structure.

FIG. 9 is a diagram showing an example of an encoding device according to a conventional proposal.

10 is a circuit diagram showing a part of the encoding device shown in FIG.

11 is a circuit diagram in which the circuit shown in FIG. 10 is further embodied.

[Explanation of symbols]

 100 Decoder Part 101 Transistor 101a Gate 110, 120, 130, 140 Data Line 150 Diffusion Layer 160 Polysilicon Layer 200 Memory Part 201 Cell Transistor 201a Gate 210 Bit Line 250 Diffusion Layer 260 Polysilicon Layer

Claims (3)

[Claims] 1. A memory unit comprising a memory cell having a predetermined number of bits, the memory content of which is programmed depending on whether or not a diffusion layer is formed under a gate, and having a large number of memory regions to which respective addresses are assigned. A plurality of wirings in which the correspondence between the input data and the address is specified by designating a predetermined address in accordance with the input data from among the plurality of addresses assigned to the respective memory areas. Contacts that connect the layers,
And a decoder section programmed by a predetermined contact selected from the contacts connecting between the underlying layer on which the transistor is formed and the first wiring layer laminated on the underlying layer via an insulating layer. A semiconductor memory comprising: 2. A memory content is stored depending on whether an enhancement type transistor which is turned on or off according to a gate potential is formed or a depletion type transistor which maintains an on state even when a voltage between source gates is 0 (V) is formed. A memory unit having a programmed number of memory cells of a predetermined number of bits and having a large number of memory regions to which respective addresses are assigned; and a plurality of addresses assigned to the respective plurality of memory regions according to input data. The correspondence between the input data and the address that specifies a predetermined address is a contact that connects a plurality of wiring layers stacked via an insulating layer,
And a decoder section programmed by a predetermined contact selected from the contacts connecting between the underlying layer on which the transistor is formed and the first wiring layer laminated on the underlying layer via an insulating layer. A semiconductor memory comprising: 3. A memory content is stored depending on whether an enhancement type transistor which is turned on or off according to a gate potential is formed or a high V _TH type transistor which is always maintained in an off state even when the gate potential fluctuates within a power supply voltage is formed. A memory unit having a programmed number of memory cells of a predetermined number of bits and having a large number of memory regions to which respective addresses are assigned; and a plurality of addresses assigned to the respective plurality of memory regions according to input data. The correspondence between the input data and the address that specifies a predetermined address is a contact that connects a plurality of wiring layers stacked via an insulating layer,
And a decoder section programmed by a predetermined contact selected from the contacts connecting between the underlying layer on which the transistor is formed and the first wiring layer laminated on the underlying layer via an insulating layer. A semiconductor memory comprising: