JPH07141214A - Data transfer error detecting device - Google Patents

Abstract

PURPOSE:To detect even an error due to word missing without increasing the quantity of data transfer, etc., as to a data transfer error detecting device which detects transfer errors of data in a computer system. CONSTITUTION:For respective 1-word data which are sequentially latched at a sent data latch part 13 of a transmission part 1 and transferred to a reception part 12 through a data transfer bus 16a, even parity bits and odd parity bits are generated alternately by a parity generation circuit 14 and added through the inverting operation of a 1-bit counter 15 synchronized with a sent data latch signal (a), and for respective 1-word data which are sequentially transferred to and latched at a received data latch part 17 of the reception part 12, errors in even parity and odd parity are detected alternately and repeated through the inverting operation of a 1-bit counter 19 synchronized with a received data latch signal (b).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer error detecting device for detecting a data transfer error in a computer system.

[0002]

2. Description of the Related Art In a conventional computer system, a parity check is carried out as one means for detecting a transfer error when transferring data consisting of a plurality of parallel bits.

That is, for example, to transfer 4-bit data "0101" as one word, whether the total number of "1" s is even parity which is defined as an even number or odd parity which is defined as an odd number. Depending on that 5
"0" or "1" is added as a parity bit at the bit position to perform data transfer. When the former, even parity is specified, even parity is added to each word on the data transmission side. Therefore, the receiving side can detect a data transfer error by determining whether or not the total number of “1” s included in each word is an even number.

When the latter is defined as odd parity, odd parity is added to each individual word on the data transmitting side, so that the total number of "1" contained in each word is on the receiving side. By determining whether the number is an odd number, the data transfer error can be detected in the same manner as in the case of the even parity.

That is, for example, when the parity bit "0" is added to the word "0101" defined as even parity and transferred as "01010", an error occurs in a bit in the transfer data due to a failure during the transfer. When a word "01000" is received, the total number of "1" s included in the received word changes to an odd number instead of an even number, which is detected as a transfer error.

However, since the above-mentioned conventional error detection means for data transfer by parity check detects an error only for a 1-bit error in each transfer word, for example, a plurality of sequentially transferred words are detected. If one word out of all is missing, there is a problem that it cannot be detected as a transfer error.

Therefore, conventionally, as error detecting means capable of detecting missing words in transfer data as an error, check data other than the above parity may be added based on a code theory based on a checksum or a CR set or an EC set. It has been implemented.

[0008]

However, in addition to error detection due to a 1-bit error in each word of the transfer data, error detection due to word loss is also performed, and check data other than the parity bit is added. However, there is a problem that the data transfer amount is increased and the processing function by the software is significantly increased, which hinders the speeding up of the data transfer.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a data transfer error detection device that can also detect an error due to a missing word without causing an increase in the amount of data transfer.

[0010]

That is, a first data transfer error detecting apparatus according to the present invention is a data transfer system for sequentially transferring 1-word data consisting of a plurality of parallel bits, and an even number for each transferred 1-word data. Alternatively, an odd number parity bit is added to form one unit of data transfer, and a parity generating unit for repeatedly generating and adding an even number parity bit and an odd number parity bit alternately for each sequentially transmitted one word data at the data transmission side. On the data receiving side, parity detection means for alternately and repeatedly performing error detection of even parity and error detection of odd parity for each word data sequentially transferred, and an initial generated parity by the parity generation means. The parity detected by the above-mentioned parity detection means is defined as the even parity or the odd parity. It is constructed by a initial parity setting means for unified or one.

The second data transfer error detecting apparatus according to the present invention is a data transfer system for converting one word data consisting of a plurality of parallel bits into an even number of words and transferring them in parallel, and an even number for each word data. Alternatively, an odd parity bit is added to form one unit of a plurality of words, and a parity generating means for alternately generating and adding an even parity bit and an odd parity bit for each sequentially supplied word data at a data supply source. And data conversion means for sequentially latching each one-word data to which the even parity bit and the odd parity bit are sequentially added by the parity generation means for a plurality of even-numbered words and performing parallel conversion, and the data supply means in the data conversion means. Every time 1 word data from the original is latched, even parity error detection and odd parity The parity switching detecting means for alternately switching the error detection of the priority and the parity generated by the parity generating means and the parity detected at the initial switching by the parity switching detecting means are set to either even parity or odd parity. It is configured by including an initial parity setting unit for unifying.

A third data transfer error detecting device according to the present invention is a data transfer system for transferring a plurality of words of one word data consisting of a plurality of parallel bits as one unit, and is provided on a data transmitting side, An n-bit counter having a count bit number n corresponding to the number n of words to be transferred as one unit and having a count value updated each time a plurality of words are transmitted and transferred. Parity generating means for generating and adding an even parity bit or an odd parity bit according to each bit count value of the n-bit counter for each 1-word data, and 1 for each of a plurality of words sequentially transferred at the data receiving side. Corresponding to the word data, each bit count value similar to that at the time of data transmission in the n-bit counter Te is constructed by a parity check means for performing error detection or error detection odd parity even parity.

A fourth data transfer error detecting apparatus according to the present invention is a data transfer system for sequentially transferring 1-word data consisting of a plurality of parallel bits, and an even or odd parity bit is added to each transferred 1-word data. Then, it is used as one unit of data transfer.
Parity generating means for switching and adding even parity bits and odd parity bits in accordance with a preset order for each sequentially transmitted word data, and even parity for each sequentially transmitted word data at the data receiving side. In the same manner as in the case of the above-mentioned parity generation means, the parity detection means for switching the error detection and the odd-numbered parity error detection are executed in accordance with a preset order.

[0014]

In other words, the first data transfer error detection device can detect an error when a 1-bit error occurs in each 1-word data and an error detection when a word omission occurs only by adding a parity bit. It will be.

Further, in the second data transfer error detecting apparatus, when one word data is converted in parallel into a plurality of even-numbered word data and transferred, a 1-bit error for each 1-word data is generated only by adding a parity bit. It is possible to detect an error when it occurs and an error when a word omission occurs.

Further, in the third data transfer error detecting apparatus, error detection and (n-1) word when a 1-bit error occurs for each 1-word data in a plurality of words simultaneously transferred by only adding a parity bit It is possible to detect an error when a word loss up to 1 occurs.

Further, in the fourth data transfer error detecting device, error detection and word omission are generated when a 1-bit error occurs for each 1-word data only by adding an even or odd parity bit which is switched aperiodically. When the error occurs, the error can be detected, and it is possible to perform the transfer with the confidentiality that the correct contents of the data cannot be obtained except the data transmitting side and the data receiving side.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first data transfer error detection device. The first data transfer error detection device is installed in a computer system that sequentially transfers 4-bit data as one word from the transmission unit 11 to the reception unit 12, and the transmission unit 11 includes a transmission data latch unit. 13, a parity generation circuit 14, and a 1-bit counter 15 are provided.

The transmission data latch unit 13 latches 4-bit data supplied via the data bus 16 as 1-word transmitted data in synchronization with the transmission data latch signal a having a predetermined cycle. The 1-word data latched by the data latch unit 13 is also given in parallel to the parity generation circuit 14 via the data bus 16.

The parity generation circuit 14 generates a parity bit for 1-word data supplied via the data bus 16. This parity generation circuit 14
Then, in accordance with the "1" or "0" signal repeatedly output from the 1-bit counter 15 in synchronization with the transmission data latch signal a, the even parity generation and the odd parity generation are alternately switched.

The 1-word data latched by the transmission data latch unit 13 is sent to the data transfer bus 16a while new 1-word data is latched according to the next transmission data latch signal a, and The even or odd parity bit generated by the parity generation circuit 14 is added and transferred to the reception unit 12.

That is, in the transmission section 11, for each 1-word data latched in the transmission data latch section 13 via the data bus 16, even parity and odd parity are sequentially alternated in the parity generation circuit 14. The data transfer bus 16a
The 1-word data sent to the receiver is transferred to the receiver 12.

Here, the initial parity bit generation processing in the parity generation circuit 14 is preset as, for example, even parity. The reception unit 12 includes a reception data latch unit 17, a parity check circuit 18, and a 1-bit counter 19.

The received data latch unit 17 determines only 4-bit data (data portion) of 1-word data to which a parity bit is added, which is transferred from the transmission unit 11 via the data transfer bus 16a. The data is latched in synchronization with the received data latch signal b of the cycle, and one word data transferred via the data transfer bus 16a is also provided in parallel to the parity check circuit 18 together with its parity bit. .

The parity check circuit 18 detects a parity error with respect to 1-word data given via the data transfer bus 16a. In the parity check circuit 18, the received data latch signal b is received.
The error detection of even parity and the error detection of odd parity are alternately switched in response to the "1" and "0" signals repeatedly output from the 1-bit counter 19 in synchronization with.

The 1-word data latched in the reception data latch unit 17 is latched with new 1-word data from the transmission unit 11 in response to the next reception data latch signal b, and also the data bus 16b. Sent out.

On the other hand, when a parity error is detected in the parity check circuit 18 with respect to 1-word data sent from the reception data latch section 17 to the data bus 16b, the error detection signal is also sent. It is sent to the data bus 16b.

That is, in the receiving section 12, the parity check circuit 18 sequentially and alternately detects the error detection of the even parity and the odd parity for each 1-word data transferred and received via the data transfer bus 16a. The error detection signal from the parity check circuit 18 is sent to the data transfer bus 16b together with the 1-word data in which the parity error latched in the reception data latch unit 17 has occurred.

The initial parity error detection processing in the parity check circuit 18 is performed by the transmitter 1
Corresponding to the initial parity bit generation processing in the parity generation circuit 14 in No. 1, it is preset as error detection of even parity, for example.

That is, in the first data transfer error detecting device having the above structure, the data bus 16 of the transmitting unit 11 is used.
1 word data “010
1 ”is latched by the transmission data latch unit 13 in synchronization with the transmission data latch signal a and is given to the parity generation circuit 14, the parity generation circuit 14 firstly transmits the transmitted 1-word data“ 0101 ”. An even parity bit "0" corresponding to "" is generated.

Then, the even parity bit "0" generated by the parity generation circuit 14 is added to the 1-word data "0101" latched by the transmission data latch unit 13, and the data is transferred via the data transfer bus 16a. It is transferred to the receiving unit 12.

After the initial transmitted 1-word data, for example, the second transmitted 1-word data "111" is transmitted.
When 1 ″ is latched by the transmission data latch unit 13 in synchronization with the second transmission data latch signal a and is given to the parity generation circuit 14, the parity generation circuit 14
Then, according to the inversion of the 1-bit counter 15, the odd parity bit "1" corresponding to the transmitted 1-word data "1111" is generated.

Then, the odd-numbered parity bit "1" generated by the parity generation circuit 14 is added to the 1-word data "1111" latched by the transmission data latch unit 13, and the data is transferred via the data transfer bus 16a. It is transferred to the receiving unit 12.

Thereafter, in the transmitting section 11, the third transmitted 1-word data “1100” and the fourth transmitted 1-word data “0011” are sequentially latched by the transmission data latch section 13. Then, each time, in response to the inversion of the 1-bit counter 15, for the third transmitted 1-word data “1100”, the even parity bit “0” and the fourth transmitted 1-word data “0011”. The odd-numbered parity bit “1” and the odd-numbered parity bit “1” are generated in the parity generation circuit 14 alternately and oddly and added, and are sequentially transferred to the reception unit 12.

In this way, 1-word data "0101 (0)""1111(1)""1" in which even parity bits and odd parity bits are alternately added from the transmitting unit 11 is obtained.
When 100 (0) ”,“ 0011 (1) ”... Are transferred via the data transfer bus 16a and sequentially latched by the reception data latch unit 17 in the reception unit 12 in synchronization with the reception data latch signal b. In each case, the parity check circuit 18 alternately repeats the even-parity error detection process and the odd-parity error detection process in response to the inversion of the 1-bit counter 19.

Here, for example, the data transfer bus 16 is added to the second 1-word data “1111 (1)” sent with the odd parity bit added in the transmitting section 11.
When an error that changes to “1011 (1)” occurs due to a failure on a and is transferred to the receiving unit 12, a parity error is detected by the odd parity error detection processing in the parity check circuit 18.

Then, an error detection signal is added from the parity check circuit 18 to the 1-word data "1011" in which an error has occurred, which is sent from the reception data latch unit 17 to the data bus 16b, and an error is notified.

That is, 1 for 1 word data to be transmitted.
The error detection by the bit error comes to be performed. On the other hand, the second 1-word data “1111” added with the odd parity bit and transmitted by the transmitting unit 11 is transmitted.
(1) ”is omitted due to, for example, a failure on the data transfer bus 16a, and the receiving unit 12 omits the second 1-word data to which the odd parity bit is added and adds the even parity bit. When the third 1-word data “1100 (0)” is transferred, a parity error is detected by the odd parity error detection process in the parity check circuit 18.

Then, the parity check is performed on the third 1-word data "1100" actually sent out from the reception data latch unit 17 to the data bus 16b as the 1-word data transferred second. An error detection signal is added from the circuit 18 to notify the error.

In other words, when data transfer of a plurality of words is performed, an error is detected by missing one word. Therefore, according to the first data transfer error detection device having the above configuration, the transmission data latch unit 13 of the transmission unit 11 is
In accordance with the inversion operation of the 1-bit counter 15 synchronized with the transmission data latch signal a, each of the 1-word data sequentially latched by the And odd parity bits are alternately generated by the parity generation circuit 14 and added, and for each 1-word data sequentially transferred and latched by the reception data latch unit 17 of the reception unit 12, the reception data latch signal b is added. Synchronized 1-bit counter 19
Depending on the inversion operation of, the even parity error detection and the odd parity error detection are repeatedly executed alternately.
As a data amount, a parity bit is simply added, so that not only can an error be detected when a 1-bit error occurs in each 1-word data, but also an error can be detected when a missing word occurs. it can.

In this case, not only the increase in the data transfer amount is suppressed, but also the hardware can be configured, so that the function of the data transfer error detection can be improved without impeding the speeding up of the data transfer process. it can.

FIG. 2 is a block diagram showing the configuration of the second data transfer error detection device. The second data transfer error detection device is installed in a computer system that converts, for example, 4-bit 1-word data into a data width of 4 times (16 bits) and transfers the data. A transmission data latch unit 13, a parity generation circuit 14, and a 1-bit counter 15 are provided in the same manner as the transmission unit 11 in the first data transfer error detection device.

That is, in the data supply section 21, for each 1-word data latched by the transmission data latch section 13 via the data bus 16, even parity and odd parity are sequentially generated in the parity generation circuit 14. The 1-word data to which the parity bits are added is sent to the data width conversion unit 22.

Here, the initial parity bit generation processing in the parity generation circuit 14 is preset as, for example, even parity. The data width converter 22 includes two data latch / even parity check circuits 2
3a and 23b and two data latch / odd parity check circuits 24a and 24b are alternately arranged in parallel in the order of even / odd / even / odd.

The data latch / parity check circuits 23a, 24a, 23b and 24b are provided in the data supply unit 2.
Each 1-word data sent from 1 is sequentially latched, and even-numbered or odd-numbered corresponding parity error detection processing is performed on the latched 1-word data.
These four data latch / parity check circuits 23
a, 24a, 23b, 24b are the data supply unit 21
In response to the switching signal c from the latch switching circuit 25 in synchronization with the transmission data latch signal a, the switching signal is sequentially and selectively switched.

That is, the 1-word data sent from the data supply unit 21 with the even parity bits and the odd parity bits sequentially added alternately are data latch / even parity check circuit 23a → data latch / odd parity check circuit 24a → The data latch / even parity check circuit 23b is sequentially latched in the order of the data latch / odd parity check circuit 24b, and after a parity error detection process is performed in each of them, it is sent to the data transfer bus 16a as 16-bit 4-word data. To be done.

That is, in the second data transfer error detecting device having the above-mentioned structure, first, the data supply unit 21 sends the first 1-word data "1010 (0)" to which the even parity bit is added. The first 1-word data “1010 (0)” is the data latch / even parity check circuit 23a of the data width converter 22.
The even parity error is detected.

Further, the second 1-word data "111" to which the odd parity bit is added is supplied from the data supply unit 21.
When 1 (1) "is transmitted, the second 1-word data" 1111 (1) "is latched by the data latch / odd parity check circuit 24a of the data width conversion unit 22,
Presence or absence of odd parity errors is detected.

Further, the third 1-word data "110" to which the even parity bit is added is supplied from the data supply unit 21.
When "0 (0)" is transmitted, the third 1-word data "1100 (0)" is latched by the data latch / even parity check circuit 23b of the data width conversion unit 22,
Presence or absence of an even parity error is detected.

Further, the fourth 1-word data "001" to which the odd parity bit is added is supplied from the data supply unit 21.
When 1 (1) ”is transmitted, the fourth 1-word data“ 0011 (1) ”is latched by the data latch / odd parity check circuit 24b of the data width conversion unit 22,
Presence or absence of odd parity errors is detected.

When no parity error is detected in the data latch / parity check circuits 23a, 24a, 23b, 24b, each 1-word data is converted into parallel 16-bit 4-word data. It is sent to the transfer bus 16a.

On the other hand, for example, "1011 (1)" is added to the second 1-word data "1111 (1)" sent with the odd parity bit added from the data supply section 21.
When an error that changes from 0 to 1 occurs and the data is latched by the data latch / odd parity check circuit 24a of the data conversion unit 22, the parity error is detected by the odd parity error detection process there.

That is, 1 for 1 word data to be transmitted.
The error detection by the bit error comes to be performed. On the other hand, the second 1-word data “1111” added with an odd parity bit from the data supply unit 21 and transmitted.
(1) ”is omitted due to a failure on the bus, and the data latch / odd parity check circuit 24a in the data conversion unit 22 omits the second 1-word data to which the odd parity bit is added. Third 1-word data "1100" with an even parity bit added
When (0) ”is latched, a parity error is detected by the odd parity error detection process there.

In other words, when data transfer of a plurality of words is performed, an error is detected due to one word missing. Therefore, according to the second data transfer error detection device having the above-mentioned configuration, when the 1-word data is converted into 4-word data in parallel and transferred, a parity bit is simply added as each word data amount, Not only can an error be detected when a 1-bit error occurs in each 1-word data, but an error can be detected when a word omission occurs.

FIG. 3 is a block diagram showing the configuration of the third data transfer error detecting apparatus. The third data transfer error detection device is installed in a computer system that sequentially transfers, for example, 2-word 4-bit 1-word data in parallel to two words from the transmission unit 11 to the reception unit 12.
Is provided with two transmission data latch units 13a and 13b, two parity generation circuits 14a and 14b, and a two-bit counter 31.

Each of the transmission data latch units 13a and 13b described above
Are two 4's provided in parallel via the data bus 16.
Bit data is latched as 1-word transmitted data in synchronization with a transmission data latch signal a of a predetermined cycle. The 1-word data latched by the transmission data latch sections 13a and 13b is the above-mentioned data. Each corresponding parity generation circuit 14a via the bus 16,
14b is also given in parallel.

Each parity generation circuit 14a, 14b
Generates a parity bit for each 1-word data supplied in parallel via the data bus 16. In the parity generation circuits 14a and 14b, the 2-bit counter 31 is synchronized with the transmission data latch signal a. The generation of the even parity and the odd parity is switched according to the upper digit and the lower digit of the 2-bit signal sequentially output from.

Here, each parity generation circuit 14a, 14
If the counter value given to b is "0", an even parity bit is generated, and if it is "1", an odd parity bit is generated.

Then, each of the above-mentioned transmission data latch units 13
The 1-word data latched in a and 13b are
Each corresponding new 1-word data is latched in accordance with the next transmission data latch signal a, and is sent out in parallel to the data transfer bus 16a, so that each parity generation circuit 1
The even or odd parity bits generated by 4a and 14b are added and transferred to the receiving unit 12.

That is, in the transmitting section 11, the transmission data latch sections 13a, 13a and 13b are connected via the data bus 16.
For each 1-word data latched in b, even parity or odd parity according to the 2-bit counter value is generated by each parity generation circuit 14a, 14b and added in parallel and transferred. Each 1-word data sent in parallel to 16 a is transferred to the receiving unit 12.

Here, the initial counter value of the 2-bit counter 31 starts from "00" and becomes "01".
It is set in advance as changing to "10" and "11". The reception unit 12 includes two reception data latch units 1
7a, 17b, two parity check circuits 18a, 1
An 8b, 2-bit counter 32 is provided.

Each of the reception data latch units 17a and 17b described above.
Is a reception data latch signal of a predetermined cycle for only 4-bit data (data portion) of each 1-word data to which each parity bit is added, which is transferred in parallel from the transmission unit 11 via the data transfer bus 16a. The data is latched in synchronism with b, and each 1-word data transferred in parallel via the data transfer bus 16a has its corresponding parity bit and its corresponding parity check circuit 1.
It is also given to 8a and 18b.

Parity check circuits 18a and 18b
Detects the parity error for each 1-word data supplied via the data transfer bus 16a. In the parity check circuits 18a and 18b, the 2-bit counter 32 is synchronized with the received data latch signal b. The error detection of even parity and odd parity is switched according to the upper digit and the lower digit of the 2-bit signal sequentially output from.

Here, each parity check circuit 18a,
If the counter value given to 18b is "0", even parity error detection is performed, and if it is "1", odd parity error detection is performed.

Then, each received data latch section 17
The 1-word data latched in a and 17b are
In response to the next received data latch signal b, each corresponding new 1-word data from the transmitter 11 is latched and sent in parallel to the data bus 16b.

On the other hand, the received data latch sections 17a, 17a
For each 1-word data sent from 7b to the data bus 16b, the corresponding parity check circuit 18 is provided.
If a parity error is detected at a and 18b, the error detection signal is also sent to the data bus 16b.

In other words, in the receiving unit 12, error detection of even parity or odd parity according to the 2-bit counter value is performed for each parity with respect to each 1-word data transferred in parallel via the data transfer bus 16a. The error detection signals from the parity check circuits 18a and 18b are implemented by the check circuits 18a and 18b.
The data is sent to the data transfer bus 16b together with the 1-word data in which the parity error is latched in b.

Here, the initial counter value in the 2-bit counter 32 corresponds to the initial counter value in the 2-bit counter 31 in the transmitter 11 and is "0".
It is preset to start from 0 "and change to" 01 "," 10 ", and" 11 ".

That is, in the third data transfer error detecting device having the above configuration, the data bus 16 of the transmitting unit 11 is
Initial 1-word data “0101” “1111” given in parallel via the transmission data latch signal a
Corresponding to the transmission data latch unit 13 in synchronization with the
When it is latched by a and 13b and is given to the corresponding parity generation circuits 14a and 14b, respectively, the counter value of the 2-bit counter 31 is "00" at this time. The even parity bit "0" corresponding to the data "0101" is generated, and the parity generation circuit 14b generates the even parity bit "0" corresponding to the transmitted 1-word data "1111".

Then, with respect to the 1-word data "0101" latched by the transmission data latch section 13a,
The even parity bit "0" generated by the parity generation circuit 14a is added, and the 1-word data "111" latched by the transmission data latch unit 13b is added.
The even parity bit "0" generated by the parity generation circuit 14b is added to 1 "and transferred in parallel to the reception unit 12 via the data transfer bus 16a.

Following the initial two transmitted 1-word data, for example, the second set of transmitted 1-word data "0011" and "1100" are respectively synchronized with the second transmission data latch signal a. Then, when they are latched by the corresponding transmission data latch units 13a and 13b and are given to the parity generation circuits 14a and 14b, at this time, the counter value of the 2-bit counter 31 is "01", so that the parity generation circuit 14a , The transmitted 1-word data “0”
The even parity bit “0” corresponding to 011 ”is generated, and the parity generation circuit 14b generates the odd parity bit“ 1 ”corresponding to the transmitted 1-word data“ 1100 ”.

Then, with respect to the 1-word data "0011" latched by the transmission data latch section 13a,
The even parity bit "0" generated by the parity generation circuit 14a is added, and the 1-word data "110" latched by the transmission data latch unit 13b is added.
An odd parity bit "1" generated by the parity generation circuit 14b is added to 0 "and transferred in parallel to the reception unit 12 via the data transfer bus 16a.

Thereafter, in the transmitter 11, the third set of transmitted 1-word data "0000""0" is further transmitted.
110 ", 4th set of transmitted 1-word data" 1001 "
"1010" and the corresponding transmission data latch units 1 in sequence
2 is updated each time it is latched by 3a and 13b
Odd parity bit “1” and even parity bit “0”, 4 sets for each 1-word transmitted data “0000” “0110” of the 3rd set according to the bit counter value “10” “11” For each of the transmitted 1-word data “1001” and “1010” of the eye, the odd parity bit “1” and the corresponding parity generation circuit 14 are used.
It is generated and added in a and 14b, and is sequentially transferred in parallel to the receiving unit 12.

In this way, the first set data "0101 (0)""111 to which the even or odd parity bits are added according to the combination of the 2-bit counter values from the transmitting unit 11 is obtained.
1 (0) ", 2nd set data" 0011 (0) "" 110 "
0 (1) ", 3rd set data" 0000 (1) "" 011 "
0 (0) ”, 4th set data“ 1001 (1) ”“ 101
0 (1) "are sequentially transferred in parallel via the data transfer bus 16a and sequentially latched by the corresponding reception data latch units 17a and 17b in the reception unit 12 in synchronization with the reception data latch signal b. In each of the corresponding parity check circuits 18a and 18b, the counter value "00" of the 2-bit counter 32 updated each time
In response to “01” → “10” → “11”, even parity error detection processing is 2 for the first set of data.
Even-parity and odd-parity error detection processing is performed for the third group of data, and odd-parity and even-parity error detection processing is performed for the third-group data.
Odd parity error detection processing is performed on the fourth set of data.

Here, the 2
Of the group data, the lower 1-word data “1100 (1)” added with an odd parity bit is
For example, due to a failure on the data transfer bus 16a, "110
When an error that changes to 1 (1) ″ occurs and is transferred to the receiving unit 12, the parity error is detected by the odd parity error detection process in the corresponding parity check circuit 18b.

Then, the parity check circuit 18b is added to the 1-word data "1101" in which an error has occurred, which is sent from the reception data latch section 17b to the data bus 16b.
The error detection signal is added from the device to notify the error.

That is, in a computer system in which 4-word 1-word data is transferred in parallel with 2 words in parallel, error detection is performed by a 1-bit error for each transmitted 1-word data.

On the other hand, in the transmitter 11, the even-numbered parity bit and the odd-numbered parity bit are added according to the 2-bit counter value "01" and transmitted, and the second set of data "0011 (0)""1100(1)" is sent. "Is lost due to, for example, a failure on the data transfer bus 16a, and the receiving unit 12 displays the next 2-bit counter value" 10 ".
The third set of data “0000 (1)” and “0110” to which an odd parity bit and an even parity bit are added according to
When (0) ”is transferred, even parity error detection processing in the parity check circuit 18a and odd number in the parity check circuit 18b according to the 2-bit counter value“ 01 ”accompanying the second data latch operation are performed. A parity error is detected by the parity error detection process.

Then, the reception data latch units 17a, 17
b is actually sent to the data bus 16b as the second set of data, the third set of data "0000""011.
An error detection signal is added to 0 "from each of the parity check circuits 18a and 18b to notify the error.

That is, when parallel data transfer of a plurality of words is performed, error detection due to missing words can be performed. Therefore, according to the third data transfer error detecting device having the above-mentioned configuration, when the parallel data transfer of a plurality of words is performed, the parity bit is simply added as the amount of each word data, and each word data is added. Not only can error detection be performed when a 1-bit error occurs, but error detection can also be performed when a word omission occurs.

In the third data transfer error detecting apparatus, the parity bit for each 1-word data is sequentially added and received in accordance with the four combinations of the 2-bit count values by the 2-bit counter 31 of the transmitter 11. Since the parity error is detected for each 1-word data transferred according to the same combination of 2-bit count values by the 2-bit counter 32 of the unit 12, in this case, error detection due to up to three parallel transfer word omissions is performed at the same time. Can be done.

FIG. 4 is a block diagram showing the configuration of the fourth data transfer error detection device. The fourth data transfer error detection device is installed in a computer system that sequentially transfers 4-bit data as one word from the transmission unit 11 to the reception unit 12, and the transmission unit 11 includes a transmission data latch unit. 13, a parity generation circuit 14, a ROM 41,
An address counter 42 is provided.

The transmission data latch unit 13 latches 4-bit data supplied via the data bus 16 as 1-word transmitted data in synchronization with the transmission data latch signal a having a predetermined cycle. The 1-word data latched by the data latch unit 13 is also given in parallel to the parity generation circuit 14 via the data bus 16.

The parity generation circuit 14 generates a parity bit for 1-word data supplied via the data bus 16. The parity generation circuit 14
Then, the ROM 4 is synchronized with the transmission data latch signal a.
According to the parity switching information d sequentially read from 1,
Generation of even parity and generation of odd parity are switched.

The ROM 41 is addressed by the address counter 42 in synchronism with the transmission data latch signal a. The ROM 41 stores even parity designation information "0" and odd parity designation information "1". , Are changed and stored in an arbitrary order set in advance.

The 1-word data latched by the transmission data latch unit 13 is sent to the data transfer bus 16a while new 1-word data is latched according to the next transmission data latch signal a, and The even or odd parity bit generated by the parity generation circuit 14 is added and transferred to the reception unit 12.

That is, in the transmitter 11, the parity generation circuit 14 presets even parity and odd parity for each 1-word data latched by the transmission data latch 13 via the data bus 16. The one-word data sent to the data transfer bus 16a is sequentially generated in the order in which they are added and transferred.
2 is transferred.

The reception section 12 is provided with a reception data latch section 17, a parity check circuit 18, a ROM 43, and an address counter 44. The reception data latch unit 17 includes the data transfer bus 16a from the transmission unit 11.
1 with a parity bit transferred via
Only 4-bit data (data portion) of the word data is latched in synchronization with the reception data latch signal b having a predetermined cycle, and one word data transferred via the data transfer bus 16a has its parity. It is also provided in parallel to the parity check circuit 18 together with the bits.

The parity check circuit 18 detects a parity error with respect to 1-word data supplied via the data transfer bus 16a. In the parity check circuit 18, the received data latch signal b is received.
The error detection of even parity and the error detection of odd parity are switched according to the parity switching information d sequentially read from the ROM 43 in synchronization with the above.

The ROM 43 is addressed by the address counter 44 in synchronism with the received data latch signal b, and the ROM 43 stores the designation information "0" for even parity and the designation information "1" for odd parity. , Are changed and stored in the set order in the same manner as the ROM 41 in the transmitting unit 11.

The 1-word data latched by the reception data latch section 17 is latched with new 1-word data from the transmission section 11 in response to the next reception data latch signal b, and at the same time, is transferred to the data bus 16b. Sent out.

On the other hand, if a parity error is detected in the parity check circuit 18 with respect to the 1-word data sent from the reception data latch section 17 to the data bus 16b, the error detection signal is also sent. It is sent to the data bus 16b.

That is, in the receiving section 12, the parity check circuit 18 presets error detection of even parity and odd parity for each 1-word data transferred and received via the data transfer bus 16a. This parity check circuit 1
The error detection signal from 8 is sent to the data transfer bus 16b together with the 1-word data in which the parity error is latched in the reception data latch unit 17.

That is, in the fourth data transfer error detecting device having the above structure, the data bus 16 of the transmitting unit 11 is
1 word data “010
When 1 ″ is latched by the transmission data latch unit 13 in synchronization with the transmission data latch signal a and is given to the parity generation circuit 14, the parity generation circuit 14 first reads from the ROM 41 by the first address. Was
For example, an odd parity bit "1" corresponding to the transmitted 1-word data "0101" is generated according to the odd parity designation information d.

Then, the odd-numbered parity bit "1" generated by the parity generation circuit 14 is added to the 1-word data "0101" latched by the transmission data latch section 13, and the data is transferred via the data transfer bus 16a. It is transferred to the receiving unit 12.

Following the initial transmitted 1-word data, for example, the second transmitted 1-word data "111"
When 1 ″ is latched by the transmission data latch unit 13 in synchronization with the second transmission data latch signal a and is given to the parity generation circuit 14, the parity generation circuit 14
In this case, the even parity bit "0" corresponding to the transmitted 1-word data "1111" is generated according to the even parity designation information d read from the ROM 41 at the second address.

Then, the even parity bit "0" generated by the parity generation circuit 14 is added to the 1-word data "1111" latched by the transmission data latch unit 13, and the data is transferred via the data transfer bus 16a. It is transferred to the receiving unit 12.

Thereafter, in the transmitting section 11, the third transmitted 1-word data “1100”, the fourth transmitted 1-word data “0011”, and the transmission data latch section 13 are sequentially latched. Then, each time, ROM
For example, according to the odd parity designation information d and the even parity designation information d read from 41, an odd parity bit “1” and a fourth transmission are performed for the third transmitted 1-word data “1100”. An even parity bit “0” is generated for 1-word data “0011”, added by the parity generation circuit 14, and sequentially transferred to the reception unit 12.

In this way, 1-word data “0101 (1)” “11” to which the even parity bit and the odd parity bit are added in the preset order from the transmitting unit 11 is obtained.
11 (0) "" 1100 (1) "" 0011 (0) "...
Are transferred via the data transfer bus 16a, and the receiving unit 1
When the reception data latch unit 17 in 2 is sequentially latched in synchronization with the reception data latch signal b, the parity check circuit 18 outputs the parity designation information d read from the ROM 43 in the preset order each time. Accordingly, even parity error detection processing or odd parity error detection processing is performed.

Here, for example, the data transfer bus 16 is added to the second 1-word data “1111 (0)” sent with the even parity bit added in the transmitting section 11.
If an error that changes to “1011 (0)” occurs due to a failure on a and is transferred to the receiving unit 12, the ROM 43
A parity error is detected by the even parity error detection processing in the parity check circuit 18 according to the second parity designation information d from.

Then, an error detection signal is added from the parity check circuit 18 to the 1-word data "1011" in which an error has occurred, which is sent from the reception data latch section 17 to the data bus 16b, and an error is notified.

That is, 1 for 1 word data to be transmitted.
The error detection by the bit error comes to be performed. On the other hand, the second 1-word data “1111” added with an even parity bit and transmitted by the transmitting unit 11
(0) ”is omitted due to, for example, a failure on the data transfer bus 16a, and the odd number parity bit is added to the receiving unit 12 by removing the second 1-word data to which the even parity bit is added. When the third 1-word data “1100 (1)” is transferred, the ROM 43
A parity error is detected by the even parity error detection processing in the parity check circuit 18 according to the second parity designation information d from.

Then, the parity check is performed on the third 1-word data "1100" actually sent from the reception data latch unit 17 to the data bus 16b as the 1-word data transferred second. An error detection signal is added from the circuit 18 to notify the error.

That is, when data transfer of a plurality of words is performed, error detection due to missing words is performed. Therefore, according to the fourth data transfer error detecting device having the above-mentioned configuration, the 1-word data of each word which is sequentially latched by the transmission data latching section 13 of the transmitting section 11 and transferred to the receiving section 12 via the data transfer bus 16a. For each
Based on the even parity designation information or the odd parity designation information read from the ROM 41 in a preset order, an even parity bit and an odd parity bit are switched and generated by the parity generation circuit 14 and added.
For each 1-word data sequentially transferred and latched to the reception data latch unit 17 of No. 2, the even parity designation information or the odd parity designation information read out from the ROM 43 in the order preset to the same specifications as the transmission ROM 41 is used. On the basis of this, since the even parity error detection and the odd parity error detection are switched and executed, the parity bit is simply added as the data amount, and the error detection is performed when a 1-bit error occurs for each 1-word data. Not only can it be performed, but error detection can be performed when a word omission occurs.

In this case, it is possible to detect an error caused by the simultaneous omission of a plurality of words depending on the combination of the order of the even parity designation information and the odd parity designation information in the ROMs 41 and 43.

In the fourth data transfer error detecting device, the order of adding the even and odd parity bits and the order of detecting the parity error are both ROMs 41 and 43.
Since it is set in advance, confidentiality of transfer data can be secured.

[0107]

As described above, according to the present invention, in any of the first to fourth data transfer error detection devices, a 1-bit error occurs for each 1-word data only by adding a parity bit. In this case, the error detection in the case and the error detection in the case where the word omission occurs can be performed. Therefore, it is possible to detect the error due to the word omission without causing an increase in the data transfer amount.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first data transfer error detection apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a second data transfer error detection apparatus according to the second embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a third data transfer error detection apparatus according to the third embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a fourth data transfer error detection apparatus according to the fourth embodiment of the present invention.

[Explanation of symbols]

11 ... Transmission unit, 12 ... Reception unit, 13, 13a, 13b ...
Transmission data latch unit, 14, 14a, 14b ... Parity generation circuit, 15 ... Transmission side 1-bit counter, 16, 16
b ... data bus, 16a ... data transfer bus, 17, 17
a, 17b ... Received data latch section, 18, 18a, 18
b ... Parity check circuit, 19 ... Reception side 1-bit counter, 21 ... Data supply section, 22 ... Data width conversion section, 2
3a, 23b ... Data latch / even parity check circuit, 24a, 24b ... Data latch / odd parity check circuit, 25 ... Latch switching circuit, 31 ... Transmission side 2-bit counter, 32 ... Reception side 2-bit counter, 41 ...
Sending side ROM, 42 ... Sending side address counter, 43 ...
Receiving side ROM, 44 ... Receiving side address counter, a ... Transmission data latch signal, b ... Reception data latch signal, c ...
Latch switching signal, d ... Parity designation information.

Claims (4)

[Claims] 1. A data transfer system for sequentially transferring 1-word data composed of a plurality of parallel bits, wherein an even or odd parity bit is added to each transferred 1-word data and added to a data transfer device as one unit of data transfer. In the error detecting device, the data transmitting side sequentially transfers the parity generating means for repeatedly generating and adding the even parity bit and the odd parity bit for each word data sequentially transmitted, and the data receiving side sequentially transfers the parity generating means. Parity detecting means for alternately repeating even parity error detection and odd parity error detection for each 1-word data, and an even generated parity by the parity generation means and an initial detected parity by the parity detection means are even numbers. Initial parity to unify to either parity or odd parity A data transfer error detecting device comprising a setting means and performing error detection when a 1-bit error occurs in each 1-word data and error detection when a word omission occurs only by adding a parity bit. . 2. A data transfer system for converting 1-word data composed of a plurality of parallel bits into an even-numbered plurality of words and transferring them in parallel and adding an even or odd parity bit to each word data to form a unit of a plurality of words. In the error detection device to be added to the data transfer device, a parity generation means for alternately and repeatedly generating and adding an even parity bit and an odd parity bit for each sequentially supplied word data at the data supply source, and the parity generation means. Data conversion means for sequentially latching each one-word data to which an even parity bit and an odd parity bit are sequentially added by a plurality of even-numbered words and performing parallel conversion, and each word from the data supply source in this data conversion means. Each time data is latched, even parity error detection and odd parity error detection The parity switching detection means for alternately switching the error detection and the parity generation detection means, and the parity generated initially by the parity generation means and the detection parity initially detected by the parity switching detection means are unified to either even parity or odd parity. An initial parity setting means is provided to detect an error when a 1-bit error occurs in each 1-word data only by adding a parity bit when parallel-converting 1-word data into an even number of plural-word data and transferring the data. A data transfer error detection device characterized by performing an error detection when a word omission occurs. 3. An error detecting device to be added to a data transfer device of a data transfer system for transferring a plurality of words of one word data composed of a plurality of parallel bits as one unit, the word being provided on the data transmitting side and transferred as one unit. An n-bit counter having a count bit number n corresponding to the number n and having a count value updated every transmission of the plurality of words, and for each 1-word data in the plurality of words sequentially transmitted on the data transmission side Parity generating means for generating and adding an even parity bit or an odd parity bit according to each bit count value of the n-bit counter, and for each 1-word data in a plurality of words sequentially transferred at the data receiving side, Depending on each bit count value, which is the same as when sending data from the n-bit counter, Parity detection means for performing error detection of parity or odd parity, and error detection when a 1-bit error occurs for each 1-word data in a plurality of words simultaneously transferred only by adding a parity bit. n-1) A data transfer error detection device characterized by performing an error detection when a word omission up to a word occurs. 4. A data transfer system for sequentially transferring 1-word data composed of a plurality of parallel bits, which is added to a data transfer device in which an even or odd parity bit is added to each transferred 1-word data as one unit of data transfer. In the error detection device, the data transmission side sequentially generates and adds the even parity bit and the odd parity bit for each word data sequentially transmitted in accordance with the preset order, and the data reception side sequentially. The parity detection means is provided for switching the even parity error detection and the odd parity error detection for each transferred one word data in the same order as in the case of the parity generation means, and aperiodically. 1 word data only by adding an even or odd parity bit that can be switched to A data transfer error detection device characterized by performing error detection when a 1-bit error occurs in a data, error detection when a word omission occurs, and concealing data contents.