JPH0713964B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0713964B2 JPH0713964B2 JP2094433A JP9443390A JPH0713964B2 JP H0713964 B2 JPH0713964 B2 JP H0713964B2 JP 2094433 A JP2094433 A JP 2094433A JP 9443390 A JP9443390 A JP 9443390A JP H0713964 B2 JPH0713964 B2 JP H0713964B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- insulating film
- sample
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は、LSI等の半導体装置における多層配線構造
の改良に関するものである。The present invention relates to an improvement in a multilayer wiring structure in a semiconductor device such as an LSI.
［発明の概要］ この発明は、多層配線構造において、下層配線の最上層
及び上層配線の最下層をそれぞれシリサイド層及び高融
点金属層で構成すると共にコンタクト孔内で該高融点金
属層を該シリサイド層にオーミック接触させることによ
り歩留り及び信頼性の向上を図ったものである。SUMMARY OF THE INVENTION According to the present invention, in a multilayer wiring structure, the uppermost layer of the lower wiring and the lowermost layer of the upper wiring are respectively composed of a silicide layer and a refractory metal layer, and the refractory metal layer is formed in the contact hole. By making ohmic contact with the layer, the yield and reliability are improved.
［従来の技術］ 従来、LSIの多層配線構造としては、第３図に示すもの
が知られている（例えば、NIKKEIMICRODEVICES,1988年
６月号，第36〜39頁参照）。第３図において、10はシリ
コン等からなる半導体基板、12は基板表面に形成された
SiO2等からなる絶縁膜、14は第１の配線層W1を構成する
Al又はAl合金層、18はCVD法等により絶縁膜12及び配線
層W1を覆って形成されたSiO2膜、20は配線段差を軽減す
べく回転塗布法等によりSiO2膜18を覆って形成されたス
ピンオンガラス（SOG）膜、22はCVD法等によりSOG膜20
を覆って形成されたSiO2膜である。[Prior Art] Conventionally, as a multilayer wiring structure of an LSI, a structure shown in FIG. 3 is known (see, for example, NIKKEI MICRODEVICES, June 1988, pages 36 to 39). In FIG. 3, 10 is a semiconductor substrate made of silicon or the like, and 12 is formed on the substrate surface.
An insulating film made of SiO 2 or the like, and 14 constitutes the first wiring layer W 1 .
Al or Al alloy layer, 18 is a SiO 2 film formed to cover the insulating film 12 and the wiring layer W 1 by a CVD method, and 20 is a SiO 2 film 18 formed by a spin coating method or the like to reduce a wiring step. The formed spin-on-glass (SOG) film, 22 is the SOG film 20 by the CVD method, etc.
Is a SiO 2 film formed to cover the.
SiO2膜18,22及びSOG膜20は、層間絶縁膜ILを構成するも
ので、層間絶縁膜ILには、配線層W1の一部に対応したコ
ンタクト孔が設けられる。そして、層間絶縁膜ILの上に
は、第２の配線層W2を構成するAl又はAl合金層26が形成
され、配線層W2はコンタクト孔を介して配線層W1と電気
的に接続される。The SiO 2 films 18 and 22 and the SOG film 20 form an interlayer insulating film IL, and the interlayer insulating film IL is provided with a contact hole corresponding to a part of the wiring layer W 1 . Then, on the interlayer insulating film IL is, Al or Al alloy layer 26 constituting the second wiring layer W 2 is formed, the wiring layer W 2 is electrically connected to the wiring layer W 1 via the contact hole To be done.
［発明が解決しようとする課題］ 上記した従来技術によると、ホトリソグラフィ技術によ
り層間絶縁膜ILにコンタクト孔を形成する際、コンタク
ト孔の側壁に相当する部分にSOG膜20の一部が露出し、
その露出部分から水分が放出される。このため、コンタ
クト孔内でAl又はAl合金層14の上面にはアルミナ（Al2O
3）膜15が形成され、配線層W1及びW2間でコンタクト抵
抗を増大させたり、導通不良を惹起したりする不都合が
あった。[Problems to be Solved by the Invention] According to the above-mentioned conventional technique, when the contact hole is formed in the interlayer insulating film IL by the photolithography technique, a part of the SOG film 20 is exposed at a portion corresponding to the side wall of the contact hole. ,
Water is released from the exposed portion. Therefore, alumina (Al 2 O 2) is formed on the upper surface of the Al or Al alloy layer 14 in the contact hole.
3 ) The film 15 is formed, and there are inconveniences of increasing the contact resistance between the wiring layers W 1 and W 2 and causing conduction failure.
また、エレクトロマイグレーション耐性が低い欠点もあ
った。すなわち、配線層W1及びW2のコンタクト部に高密
度の電流を高温で長時間にわたって流すと、例えば第４
図に示すようにコンタクト部にボイドVDが生じ、コンタ
クト抵抗の増大又は断線を招くことがあった。In addition, there is a drawback that electromigration resistance is low. That is, when a high-density current is applied to the contact portions of the wiring layers W 1 and W 2 at high temperature for a long time, for example, the fourth
As shown in the figure, a void VD may be generated in the contact portion, which may cause an increase in contact resistance or disconnection.
この発明の目的は、上下配線層間のコンタクト部におい
て導通性及びエレクトロマイグレーシヨン耐性を向上さ
せた新規な多層配線構造を提供することにある。An object of the present invention is to provide a novel multi-layer wiring structure having improved conductivity and electromigration resistance in a contact portion between upper and lower wiring layers.
この発明による多層配線構造は、 （ａ）第１の絶縁膜と、 （ｂ）この第１の絶縁膜の上に形成され、最上層にシリ
サイド層を有する第１の配線層と、 （ｃ）この第１の配線層及び前記第１の絶縁膜を覆って
形成され、該第１の配線層の一部に対応したコンタクト
孔を有する第２の絶縁膜と、 （ｄ）この第２の絶縁膜の上に形成され、最下層に高融
点金属層を有する第２の配線層とをそなえ、 前記コンタクト孔内で前記高融点金属層を前記シリサイ
ド層にオーミック接触させることにより前記第１及び第
２の配線層を電気的に接続したことを特徴とするもので
ある。The multilayer wiring structure according to the present invention includes: (a) a first insulating film; (b) a first wiring layer formed on the first insulating film and having a silicide layer as an uppermost layer; (c) A second insulating film formed to cover the first wiring layer and the first insulating film and having a contact hole corresponding to a part of the first wiring layer; and (d) the second insulating film. A second wiring layer formed on the film and having a refractory metal layer as a lowermost layer, the ohmic contact of the refractory metal layer with the silicide layer in the contact hole; It is characterized in that the two wiring layers are electrically connected.
［作用］ この発明の構成によれば、第１の配線層の最上層にシリ
サイド層を配置したので、コンタクト孔形成時にコンタ
クト孔側壁にSOG膜等が露出してもシリサイド層表面に
酸化物等が生成されない。そして、第２の配線層の最下
層に高融点金属層を配置してこの高融点金属層を第１の
配線層のシリサイド層（最上層）にオーミック接触させ
るようにしたので、第１及び第２の配線層の間には、安
定した低抵抗のコンタクト部が得られる。また、このコ
ンタクト部は、後述するように良好なエレクトロマイグ
レーション耐性を示すものである。[Operation] According to the structure of the present invention, since the silicide layer is arranged in the uppermost layer of the first wiring layer, even if the SOG film or the like is exposed on the side wall of the contact hole during formation of the contact hole, oxide or the like is formed on the surface of the silicide layer. Is not generated. Then, the refractory metal layer is arranged as the lowermost layer of the second wiring layer, and this refractory metal layer is brought into ohmic contact with the silicide layer (uppermost layer) of the first wiring layer. A stable low-resistance contact portion can be obtained between the two wiring layers. Further, this contact portion exhibits good electromigration resistance as described later.
［実施例］ 第１図は、この発明の一実施例による多層配線構造を示
すもので、第３図と同様の部分には同様の符号を付して
詳細な説明を省略する。[Embodiment] FIG. 1 shows a multilayer wiring structure according to an embodiment of the present invention. The same parts as those in FIG. 3 are designated by the same reference numerals and their detailed description will be omitted.
第１図の実施例の特徴は、第１の配線層W1の最上層及び
第２の配線層W2の最下層をそれぞれシリサイド層16及び
高融点金属層24で構成すると共に、コンタクト孔内で高
融点金属層24をシリサイド層16にオーミック接触させる
ようにしたことである。層16を構成するシリサイドとし
ては、WSix、MoSix等を用いることができ、層24を構成
する高融点金属としては、Ti等を用いることができる。The feature of the embodiment shown in FIG. 1 is that the uppermost layer of the first wiring layer W 1 and the lowermost layer of the second wiring layer W 2 are composed of a silicide layer 16 and a refractory metal layer 24, respectively, and That is, the refractory metal layer 24 is brought into ohmic contact with the silicide layer 16. WSix, MoSix, or the like can be used as the silicide forming the layer 16, and Ti or the like can be used as the refractory metal forming the layer 24.
第２図は、この発明による上下配線層間の配線抵抗（こ
れにはコンタクト抵抗も含まれる）の低減効果を確認す
るために用いらる比較試料のコンタクト部配置を示すも
ので、この比較試料では、下方の第１配線層W1及び上方
の第２配線層W2に関するコンタクト部C1,C2…Cn-1,Cnが
直列接続された形で基板上面に配置され、コンタクト部
C1及びCnにそれぞれ接続された端子T1及びT2の間の電気
抵抗を測定するようになっている。上下配線層間のコン
タクト抵抗（通称ビア抵抗）は、数10mΩと低いので、
１個当りのビア抵抗としてではなく、第２図に示すよう
にビアチェーン抵抗として測定するのが通常である。FIG. 2 shows an arrangement of contact portions of a comparative sample used for confirming the effect of reducing the wiring resistance (including contact resistance) between the upper and lower wiring layers according to the present invention. , The contact portions C 1 , C 2 ... C n-1 , C n relating to the lower first wiring layer W 1 and the upper second wiring layer W 2 are arranged in series on the substrate upper surface,
The electrical resistance between the terminals T 1 and T 2 connected to C 1 and Cn, respectively, is measured. Since the contact resistance (commonly called via resistance) between the upper and lower wiring layers is as low as several 10 mΩ,
It is usual to measure not as the via resistance per piece but as the via chain resistance as shown in FIG.
比較に当っては、C1〜Cnの各コンタクト部が第１図に示
すような構成の比較試料（サンプルＡと称する）と、第
１図の構成からシリサイド層16を省略した構成の比較試
料（サンプルＢと称する）と、第１図の構成からシリサ
イド層16及び高融点金属層24を省略した構成の比較試料
（第３図に示した従来例相当のもので、サンプルＣと称
する）とを用意した。サンプルＡ〜Ｃについて具体的な
配線構成を示すと、次の通りである。In comparison, a comparison sample (referred to as sample A) in which each contact portion of C 1 to C n has a configuration as shown in FIG. 1 and a configuration in which the silicide layer 16 is omitted from the configuration of FIG. 1 are compared. A sample (referred to as sample B) and a comparative sample in which the silicide layer 16 and the refractory metal layer 24 are omitted from the structure shown in FIG. 1 (corresponding to the conventional example shown in FIG. 3 and referred to as sample C). And prepared. The specific wiring configuration of Samples A to C is as follows.
ここで、層14、16、24、26の厚さは、それぞれ0.6μ
ｍ、50nm、15nm、１μｍであり、コンタクト部の平面寸
法は、1.0μｍ×1.0μｍであった。 Here, the thickness of each of the layers 14, 16, 24, and 26 is 0.6 μm.
m, 50 nm, 15 nm, 1 μm, and the plane dimension of the contact portion was 1.0 μm × 1.0 μm.
Ａ〜Ｃの各サンプル毎に１チップ当りのコンタクト数を
10万個として400チップ分のサンプルを作成し、良品率
（全サンプル数に占める導通良好サンプル数の割合）を
求めた結果を次に示す。サンプル 良品率［％］ Ａ 100 Ｂ 40 Ｃ 0 サンプルＣのように良品率０％では全く実用にならな
い。また、サンプルＢのように40％程度の良品率では実
用上不十分である。これに対し、この発明によるサンプ
ルＡでは、良品率100％であり、最高の歩留りが得られ
た。The number of contacts per chip for each sample of A to C
Samples for 400 chips were prepared as 100,000, and the non-defective rate (the ratio of the number of samples with good continuity to the total number of samples) was calculated. Sample non- defective rate [%] A 100 B 40 C 0 Like sample C, non-defective rate 0% is not practical. Further, a good product rate of about 40% as in Sample B is not practically sufficient. On the other hand, in sample A according to the present invention, the yield rate was 100%, and the highest yield was obtained.
一方、エレクトロマイグレーション耐性の評価も実施し
た。すなわち、Ａ〜Ｃの各サンプルとしてコンタクト数
3000のものを用意し、各サンプル毎に温度190℃、コン
タクト部電流密度３×106A／cm2なる条件で通電を行な
うことにより50％累積不良時間（MTF）を測定した。こ
の場合の測定結果をサンプルＣのMTFを１として示すと
次の通りである。サンプル MTF Ａ 20 Ｂ 10 Ｃ 1 この発明によるサンプルＡでは、従来例によるサンプル
Ｃに比べてMTFで20倍の改善効果が得られた。On the other hand, the electromigration resistance was also evaluated. That is, the number of contacts for each sample of A to C
3000 samples were prepared, and 50% cumulative failure time (MTF) was measured for each sample by energizing the sample at a temperature of 190 ° C. and a current density of the contact part of 3 × 10 6 A / cm 2 . The measurement result in this case is as follows when the MTF of sample C is shown as 1. Sample MTF A 20 B 10 C 1 In sample A according to the present invention, an improvement effect of 20 times in MTF was obtained as compared with sample C according to the conventional example.
［発明の効果］ 以上のように、この発明によれば、コンタクト孔内にお
いて下層配線の最上層としてのシリサイド層に対して上
層配線の最下層としての高融点金属層をオーミック接触
させるようにしたので、コンタクト抵抗を低減すると共
に導通不良発生を回避することができ、製造歩留りが向
上する効果が得られる。As described above, according to the present invention, the refractory metal layer as the lowermost layer of the upper wiring is brought into ohmic contact with the silicide layer as the uppermost layer of the lower wiring in the contact hole. Therefore, it is possible to reduce the contact resistance and avoid the occurrence of defective conduction, and it is possible to obtain the effect of improving the manufacturing yield.
その上、コンタクト部でのエレクトロマイグレーション
耐性の改善により信頼性が向上する効果も得られる。In addition, the effect of improving reliability by improving the electromigration resistance at the contact portion can be obtained.
第１図は、この発明の一実施例による多層配線構造を示
す基板断面図、 第２図は、比較試料のコンタクト部配置を示す上面図、 第３図及び第４図は、従来の多層配線構造におけるアル
ミナ生成状態及びボイド発生状態をそれぞれ示す基板断
面図である。 10……半導体基板、12……絶縁膜、16……シリサイド
層、24……高融点金属層、W1,W2……配線層、IL……層
間絶縁膜。FIG. 1 is a sectional view of a substrate showing a multilayer wiring structure according to an embodiment of the present invention, FIG. 2 is a top view showing a contact portion arrangement of a comparative sample, and FIGS. 3 and 4 are conventional multilayer wiring. It is a board sectional view showing an alumina generation state and a void generation state in a structure, respectively. 10 ...... semiconductor substrate, 12 ...... insulating film, 16 ...... silicide layer, 24 ...... refractory metal layer, W 1, W 2 ...... wiring layers, IL ...... interlayer insulating film.
Claims (1)
て、該多層配線構造は、 （ａ）第１の絶縁膜と、 （ｂ）この第１の絶縁膜の上に形成され、最上層にシリ
サイド層を有する第１の配線層と、 （ｃ）この第１の配線層及び前記第１の絶縁膜を覆って
形成され、該第１の配線層の一部に対応したコンタクト
孔を有する第２の絶縁膜と、 （ｄ）この第２の絶縁膜の上に形成され、最下層に高融
点金属層を有する第２の配線層とをそなえ、 前記コンタクト孔内で前記高融点金属層を前記シリサイ
ド層にオーミック接触させることにより前記第１及び第
２の配線層を電気的に接続したことを特徴とする半導体
装置。1. In a semiconductor device having a multi-layer wiring structure, the multi-layer wiring structure comprises: (a) a first insulating film; and (b) a first insulating film formed on the first insulating film, and a silicide layer as an uppermost layer. A second wiring layer having a contact hole corresponding to a part of the first wiring layer and (c) the first wiring layer and the first insulating film. An insulating film; and (d) a second wiring layer formed on the second insulating film and having a refractory metal layer as a lowermost layer, wherein the refractory metal layer is silicided in the contact hole. A semiconductor device, wherein the first and second wiring layers are electrically connected by making ohmic contact with the layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2094433A JPH0713964B2 (en) | 1990-04-10 | 1990-04-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2094433A JPH0713964B2 (en) | 1990-04-10 | 1990-04-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03292756A JPH03292756A (en) | 1991-12-24 |
| JPH0713964B2 true JPH0713964B2 (en) | 1995-02-15 |
Family
ID=14110114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2094433A Expired - Fee Related JPH0713964B2 (en) | 1990-04-10 | 1990-04-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0713964B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62241373A (en) * | 1986-04-11 | 1987-10-22 | Mitsubishi Electric Corp | Semiconductor device |
| JPH02144921A (en) * | 1988-11-28 | 1990-06-04 | Hitachi Ltd | Semiconductor device |
-
1990
- 1990-04-10 JP JP2094433A patent/JPH0713964B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62241373A (en) * | 1986-04-11 | 1987-10-22 | Mitsubishi Electric Corp | Semiconductor device |
| JPH02144921A (en) * | 1988-11-28 | 1990-06-04 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03292756A (en) | 1991-12-24 |
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