JPH07134166A - Ic failure analyzing device - Google Patents

Abstract

PURPOSE:To automatically impart the net name imparted to a circuit chart to the observed image and waveform chart obtained form the measurement data, in an IC failure analyzing device in which CAD data are inputted, the net list data by the CAD data are collated with mask rate data and circuit chart data in a collating part, whereby the net list, mask layout and circuit chart corresponding to the specified part designated by an input means can be displayed, and the observed image and waveform can be also displayed by the measurement data form an IC internal analyzing device. CONSTITUTION:A circuit chart-to-measurement data collating part 33 is provided, measurement data are conformed to a specified part designated in a circuit chart display part 31 by the circuit chart-to measurement data collating part 33, stored in a collating data B memory part 34, and the net name imparted to the specified part is imparted to the observed image or waveform chart.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC failure analysis apparatus used when designing and developing a semiconductor integrated circuit (hereinafter referred to as "IC").

[0002]

2. Description of the Related Art In general, when manufacturing an IC, automation is achieved by automatically determining a mask layout such as a wiring pattern by using circuit netlist CAD data and mask layout CAD data. On the other hand, in order to find a defective portion of a prototype IC, conventionally, the circuit netlist CAD data used at the time of manufacturing the IC and the mask layout CAD data are used to associate the circuit netlist with the mask layout. The IC internal analyzer is operated to refer to the waveform of the current or voltage flowing through each part of the prototyped device to identify the defective portion.

The applicant of the present invention previously filed Japanese Patent Application No. 5-18405.
No. 5 discloses a display device for IC failure analysis. FIG. 3 shows the IC defect analysis display device. 10, 11 and 1 in the figure
Reference numeral 2 denotes an external storage device such as a floppy disk or a fixed disk. The external storage device 10 stores, for example, circuit netlist CAD data used for manufacturing an IC, the external storage device 11 stores mask layout CAD data, and the external storage device 12 stores pin input / output attribute information. There is. Since the pin input / output attribute information is fixed data as described later, it may be constantly stored in the internal storage device. The data read from these external storage devices 10, 11 and 12 is an IC configured by a computer.
It is input to the failure analysis display device 20. The IC defect analysis display device 20 includes a netlist data conversion unit 21, a mask layout data conversion unit 22, a netlist-to-mask layout collation unit 23, a netlist-circuit diagram generation unit 24, and a circuit diagram-to-mask layout. The collating unit 25,
The netlist data storage unit 26, the circuit diagram data storage unit 27, the mask layout data storage unit 28, the matching data storage unit 29, the netlist display unit 30, the circuit diagram display unit 31, and the mask layout display unit 32. And is configured.

The netlist data conversion unit 21 and the mask layout data conversion unit 22 each perform an operation of converting the CAD data into a format that can be used by the IC defect analysis display device 20. These data conversion units 2
The netlist data converted in 1 and 22 and the mask layout data are stored in the netlist data storage unit 2 respectively.
6 and the mask layout data storage unit 28.
In the netlist-to-mask layout matching unit 23, the netlist and the mask layout are associated with each other.

On the other hand, the pin input / output attribute information 12 is input to the netlist-circuit diagram generation unit 24, and circuit diagram data is generated with the netlist data from the netlist data conversion unit 21. Here, the pin input / output attribute information is the type of element and the name of the terminal of each element,
For example, R is a resistor, L is an inductance, D is a diode, AND21 is a 2-input 1-output AND gate, and other types are C, J, V, I, Q, P, N, NAND, and the like. In the case of the resistor R, the 1st pin represents the input side with A, and the 2nd pin represents the output side with Z. In the case of the junction field effect transistor J, it is specified that the first pin is G (gate), the second pin is S (source), and the third pin is D (drain). By thus defining the pin input / output attribute of each element, the netlist-circuit diagram generation unit 24 reads out the graphic pattern of each element from the element name added to the netlist data, and The terminals can be defined.

That is, from the net list shown in FIG.
The circuit diagram shown in can be drawn. Cell X1 has 2 inputs 1
The output AND gate connects the wiring IN1 to the first pin A, connects the wiring IN2 to the second pin B, and connects the wiring OUT1 to the output terminal Z. The cell X2 is a 2-input 1-output AND gate, and the wiring IN3 is connected to the 1st pin A.
Wiring IN4 is connected to No. pin B, and wiring O is to No. 3 pin Z
UT2 is connected. The cell X3 is a 2-input 1-output NAND gate, and the wiring OUT1 is connected to the first pin A, the wiring OUT2 is connected to the second pin B, and the wiring OUT is connected to the output terminal Z.
3 are connected.

The circuit diagram data thus generated is stored in the circuit diagram data storage unit 27 and, at the same time, is associated with the circuit diagram, the mask layout and the net list by the circuit diagram vs. mask layout collating unit 25. Then, the circuit diagram, the mask layout, and the netlist of the same portion which are associated by the circuit diagram-to-mask layout collating unit 25 are displayed on the respective display units 31, 32, and 30. 29
Indicates a collation data storage unit that stores the collation data necessary for the association.

With all the circuit diagram data stored in the circuit diagram data storage unit 27, the circuit diagram display unit 31 displays a circuit diagram of the entire area by the initial menu. The position of which part of the entire circuit diagram to analyze is designated by the input means 13 such as a mouse. By inputting the analysis position, the circuit diagram of the designated one area is displayed on the circuit diagram display unit 31, as shown in FIG. The display is the display unit 30,
31 and 32 are displayed on the same screen by the multitask function.

That is, by inputting a portion to be analyzed in the circuit diagram of the circuit diagram display unit 31, the collation data storage unit 29
Sends a control signal to the netlist display unit 30 and the mask layout display unit 32 to display the netlist and the mask layout corresponding to the displayed circuit diagram on the netlist display unit 30 and the mask layout display unit 32.
Further, by designating a specific wiring portion from the input means 13, the netlist and the mask layout corresponding to the wiring portion are displayed in a blinking manner or are highlighted by a method such as brightly shining, and the correspondence between the circuit and the mask layout is obtained. Is displayed. Not only the circuit diagram display section 31 designates a specific portion from the input means 13, but also a specific portion is designated from the net list display section 30 or the mask layout display section 32 designates a specific portion. May be designated so that the corresponding portions of the respective display units 30, 31 and 32 are displayed in a blinking manner, brightly shining, or in bold lines.

At the same time, the mask layout display section 32 is displayed.
The position information added to the mask layout data is sent to the IC internal analysis device 40 from the IC internal analysis device 4
When the value is 0, the designated area of the circuit wiring portion of the IC under test designated on the circuit diagram display section 31 is operated as an observation target. IC
The internal analyzer 40 is, for example, an electron beam tester (EB).
Tester) and an ion beam tester mainly composed of a charged particle beam tester, and one mainly composed of an optical microscope. For example, in a charged particle beam tester, an IC under test is placed in a vacuum chamber, and when the IC under test placed in the vacuum chamber is swept irradiated (irradiated while scanning) with a charged particle beam, the potential of the wiring portion is changed. Since the amount of secondary electrons emitted changes depending on the vertical direction, the amount of secondary electrons generated from each irradiation point is measured for each irradiation point, and the measured amount is captured as an electrical signal and processed in the IC. Potential contrast image (SEM image: Sc
anning Electron Microscope and SIM image: Scanning
Ion Microscope) and waveform data are obtained and stored in the observation image data storage unit and the waveform data storage unit, respectively.

The IC internal analysis device 40 also has an observation display section for displaying an observation image of image data and a waveform diagram of waveform data. The position information sent from the mask layout display unit 32 to the IC internal analysis device 40 is coordinate data and magnification data (corresponding to the measurement area), and the irradiation position of the IC under test can be specified by this position information. The mask layout and the observed image do not match perfectly at the time of manufacturing or because of accuracy problems in the analysis device.
Therefore, the measurer finely adjusts the X and Y coordinate positions of the IC to be measured while comparing the mask layout and the observed image, and after completely matching them, observes the observed image and the signal waveform to measure the IC to be measured.
Determines whether is operating normally.

[0012]

As described above, the conventional I
The C failure analysis device includes an IC failure analysis display device 20 for analyzing and displaying information obtained from CAD data for IC manufacturing,
Since it was developed with a concept different from that of the IC internal analyzer 40 mainly including the charged particle beam tester and the optical microscope, the interface between the two was insufficient. In particular, the transmission of information was the minimum necessary. Therefore, it is difficult to make correspondence between the mask layout of printed-out figures after observation and measurement, the netlist, the observed image and the waveform diagram. Enter the net name from the keyboard one by one,
Alternatively, it is necessary to take notes in a notebook and fill in a recording sheet after the measurement, which is time-consuming and complicated.

The present invention relates to an IC defect analysis display device and an IC.
An object of the present invention is to provide an IC failure analysis device that integrates an observation display unit of an internal analysis device and can mutually exchange and display data, and can automatically attach a net name to an observation image or a waveform diagram. .

[0014]

In order to achieve the above object, the present invention integrates the display unit and the operation unit of the entire system of the IC failure analysis device and newly adds necessary parts to form a workstation. Therefore, the conventional IC failure analysis display device 20 and the waveform data storage unit, the waveform diagram display unit, the observation image data storage unit and the observation image display unit, which are present in the IC internal analysis device 40, are integrated, A circuit diagram-to-measurement data collating unit is provided to collect net names from the conventional circuit diagram display unit, collate the observed image data with the waveform data, and store the result in the collation data B storage unit. The configuration.

According to the configuration of the present invention, the circuit diagram is displayed on the circuit diagram display portion, and the mask layout, netlist, observation image and waveform diagram of the circuit portion displayed on the circuit display portion are displayed on the respective display portions. To be done. In the circuit diagram of the circuit diagram display part, net names are given to the respective lines of the wiring. Then, by designating a specific wiring of the circuit diagram with the input means, the net name is highlighted in the net list display section and the section designated in the mask layout display section, and the waveform is displayed in the designated section in the observed image display section. The waveform display is displayed with the net name attached, and is also printed when printed out. As described above, according to the present invention, by designating a target wiring portion from the circuit diagram, the portion is highlighted or printed on both the display unit and the print paper, which facilitates the analysis of the defective portion. Complexity is eliminated and defect analysis can be done in a short time.

[0016]

FIG. 1 shows an embodiment of the present invention. Portions corresponding to those in FIG. 3 are designated by the same reference numerals. In the present invention, the conventional display device 2 for IC failure analysis is installed in the workstation 50.
0 and the observation image data storage unit 3 in the IC internal analysis device 40
6, the observation image display unit 38, the waveform data storage unit 35, and the waveform diagram display unit 37 are integrated, and a circuit diagram pair measurement data collating unit 33 and a collation data B storing unit 34 are newly provided.

The circuit-diagram-to-measurement-data collating unit 33 receives the observation image data and the waveform data from the IC internal analyzer 40, and the circuit diagram display unit 31 designates the data of the designated wiring portion (the designated portion of the mask layout). Receives the coordinate data of and the specified net name). Then, the net name is given to the corresponding portion of the observed image data by collating with the observed image data, and the net name is also given to the corresponding waveform diagram. The collation data required for the association are stored in the collation data B storage unit 34.

The observation image data storage unit 36 receives the observation image data from the IC internal analyzer 40 and stores it. The waveform data storage unit 35 receives the waveform data from the IC internal analysis device 40 and stores it. The arithmetic control unit 41 performs necessary arithmetic and control in the IC failure analysis device.

The observation image display section 38 receives and displays the observation image data from the observation image data storage section 36, and
X of the mask layout corresponding to the specified wiring part,
The Y coordinate data and the net name are received from the collation data B storage unit 34, and the net name is superimposed and displayed at the X and Y coordinate positions. Alternatively, the net name may be displayed at a specific position such as the upper right of the display surface. The waveform display unit 37 is the waveform data storage unit 3
5, the waveform data is received and displayed, and the net name corresponding to the designated wiring portion is received from the collation data B storage unit 34, and the net name is displayed at the designated position in an overlapping manner. As described above, displaying the net name on the display units 37 and 38 is more convenient for measurement, but the display screen is the same as the conventional one due to problems with the display screen, and can be added only in the case of printout.

When printing out, each display unit 3
The graphic and waveform data displayed at 0, 31, 32, 37, and 38 are printed as they are, or with the necessary data added, and the data from the respective display units 30, 31, 32, 37, and 38 are printed.

It should be noted that, in the above description, for easy understanding, the data is displayed in all display parts, that is, the net list display part 30, the circuit diagram display part 31, the mask layout display part 32, the waveform diagram display part 37 and the observation. Although it is described that the image is displayed on the image display unit 38, the minimum required display unit is only the mask layout display unit 32 and the observation image display unit 38, and the others may be only the printout.

[0022]

As described above, according to the present invention, the net name defined by the circuit netlist CAD data 10 is automatically added to the observation image or the measurement waveform diagram which is the figure of the measurement result measured by the IC internal analyzer 40. Since it is displayed and printed on the screen, human error is prevented, and especially when the net name is long, the complexity is eliminated and the operability is greatly improved, so that the effect is great.

[Brief description of drawings]

FIG. 1 is a diagram of an embodiment of the present invention.

FIG. 2 is an example of a display state of the embodiment shown in FIG.

FIG. 3 is a block diagram for explaining a conventional technique.

4 is a diagram showing an example of a netlist used in the conventional example shown in FIG.

5 is a connection diagram showing an example of a circuit diagram drawn in the conventional example shown in FIG.

FIG. 6 is a diagram showing a display state of the conventional example shown in FIG.

[Explanation of symbols]

 10, 11 and 12 External storage device 13 Input means 20 IC defect analysis display device 21 Netlist data conversion unit 22 Mask layout data conversion unit 23 Netlist pair mask layout collation unit 24 Netlist-circuit diagram generation unit 25 Circuit diagram pair Mask layout collation unit 26 Netlist data storage unit 27 Circuit diagram data storage unit 28 Mask layout data storage unit 29 Collation data storage unit 30 Netlist display unit 31 Circuit diagram display unit 32 Mask layout display unit 33 Circuit diagram vs. measurement data collation unit 34 collation data B storage unit 35 waveform data storage unit 36 observation image data storage unit 37 waveform diagram display unit 38 observation image display unit 40 IC internal analysis device 41 arithmetic control unit 50 workstation

Claims (1)

[Claims] 1. CAD data is input, netlist data, mask layout data, and circuit diagram data based on the CAD data are collated by a collating unit, and a mask layout corresponding to a specific portion designated by an input means can be displayed. On the other hand, in the IC failure analysis device capable of displaying an observation image with the measurement data from the IC internal analysis device, the circuit diagram vs. measurement data matching in which the measurement data is associated with the specific portion specified in the circuit diagram display section (31). And a collation data B storage unit (34) for attaching the net name attached to the specific portion to the specific portion of the observation image displayed on the observation image display unit (38). An IC failure analysis device characterized by: