JPH07134165A - Ic failure analyzing device - Google Patents

Abstract

PURPOSE:To automatically display and print out the mask layout of a specified part designated by an input means on a mask layout display part, in a failure analyzing device in which CAD data are inputted, the net list data by the CAD data is collated with mask rate data in a collating part, whereby the mask layout corresponding to the designated specified part can be displayed, and the observed image can be also displayed by the measurement data from an IC internal analyzing device, by designating a failure position of the observed image by the input means. CONSTITUTION:A CAD data-to-measurement data collating part 33 are provided, the observation coordinate data of measurement data conformed to the X,Y coordinate data of a mask layout by the CAD data-to-measurement data collating part 11, and stored in a collating data B memory part 34, and a specified part of the observed image in an observation image display part 38 is designated, whereby the X,Y coordinate data are imparted to a mask layout display part 32, so that the mask layout of the specified part can be displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC failure analysis apparatus used when designing and developing a semiconductor integrated circuit (hereinafter referred to as "IC").

[0002]

2. Description of the Related Art In general, when manufacturing an IC, automation is achieved by automatically determining a mask layout such as a wiring pattern by using circuit netlist CAD data and mask layout CAD data. On the other hand, in order to find a defective portion of a prototype IC, conventionally, the circuit netlist CAD data used at the time of manufacturing the IC and the mask layout CAD data are used to associate the circuit netlist with the mask layout. The IC internal analyzer is operated to refer to the waveform of the current or voltage flowing through each part of the prototyped device to identify the defective portion.

The applicant of the present invention previously filed Japanese Patent Application No. 5-18405.
No. 5 discloses a display device for IC failure analysis. FIG. 3 shows the IC defect analysis display device. 10, 11 and 1 in the figure
Reference numeral 2 denotes an external storage device such as a floppy disk or a fixed disk. The external storage device 10 stores, for example, circuit netlist CAD data used for manufacturing an IC, the external storage device 11 stores mask layout CAD data, and the external storage device 12 stores pin input / output attribute information. There is. Since the pin input / output attribute information is fixed data as described later, it may be constantly stored in the internal storage device. The data read from these external storage devices 10, 11 and 12 is an IC configured by a computer.
It is input to the failure analysis display device 20. The IC defect analysis display device 20 includes a netlist data conversion unit 21, a mask layout data conversion unit 22, a netlist-to-mask layout collation unit 23, a netlist-circuit diagram generation unit 24, and a circuit diagram-to-mask layout. The collating unit 25,
The netlist data storage unit 26, the circuit diagram data storage unit 27, the mask layout data storage unit 28, the matching data storage unit 29, the netlist display unit 30, the circuit diagram display unit 31, and the mask layout display unit 32. And is configured.

The netlist data conversion unit 21 and the mask layout data conversion unit 22 each perform an operation of converting the CAD data into a format that can be used by the IC defect analysis display device 20. These data conversion units 2
The netlist data converted in 1 and 22 and the mask layout data are stored in the netlist data storage unit 2 respectively.
6 and the mask layout data storage unit 28.
In the netlist-to-mask layout matching unit 23, the netlist and the mask layout are associated with each other.

On the other hand, the pin input / output attribute information 12 is input to the netlist-circuit diagram generation unit 24, and circuit diagram data is generated with the netlist data from the netlist data conversion unit 21. Here, the pin input / output attribute information is the type of element and the name of the terminal of each element,
For example, R is a resistor, L is an inductance, D is a diode, AND21 is a 2-input 1-output AND gate, and other types are C, J, V, I, Q, P, N, NAND, and the like. In the case of the resistor R, the 1st pin represents the input side with A, and the 2nd pin represents the output side with Z. In the case of the junction field effect transistor J, it is specified that the first pin is G (gate), the second pin is S (source), and the third pin is D (drain). By thus defining the pin input / output attribute of each element, the netlist-circuit diagram generation unit 24 reads out the graphic pattern of each element from the element name added to the netlist data, and The terminals can be defined.

That is, from the net list shown in FIG.
The circuit diagram shown in can be drawn. Cell X1 has 2 inputs 1
The output AND gate connects the wiring IN1 to the first pin A, connects the wiring IN2 to the second pin B, and connects the wiring OUT1 to the output terminal Z. The cell X2 is a 2-input 1-output AND gate, and the wiring IN3 is connected to the 1st pin A.
Wiring IN4 is connected to No. pin B, and wiring O is to No. 3 pin Z
UT2 is connected. The cell X3 is a 2-input 1-output NAND gate, and the wiring OUT1 is connected to the first pin A, the wiring OUT2 is connected to the second pin B, and the wiring OUT is connected to the output terminal Z.
3 are connected.

The circuit diagram data thus generated is stored in the circuit diagram data storage unit 27 and, at the same time, is associated with the circuit diagram, the mask layout and the net list by the circuit diagram vs. mask layout collating unit 25. Then, the circuit diagram, the mask layout, and the netlist of the same portion which are associated by the circuit diagram-to-mask layout collating unit 25 are displayed on the respective display units 31, 32, and 30. 29
Indicates a collation data storage unit that stores the collation data necessary for the association.

With all the circuit diagram data stored in the circuit diagram data storage unit 27, the circuit diagram display unit 31 displays a circuit diagram of the entire area by the initial menu. The position of which part of the entire circuit diagram to analyze is designated by the input means 13 such as a mouse. By inputting the analysis position, the circuit diagram of the designated one area is displayed on the circuit diagram display unit 31, as shown in FIG. The display is the display unit 30,
31 and 32 are displayed on the same screen by the multitask function.

That is, by inputting a portion to be analyzed in the circuit diagram of the circuit diagram display unit 31, the collation data storage unit 29
Sends a control signal to the netlist display unit 30 and the mask layout display unit 32 to display the netlist and the mask layout corresponding to the displayed circuit diagram on the netlist display unit 30 and the mask layout display unit 32.
Further, by designating a specific wiring portion from the input means 13, the netlist and the mask layout corresponding to the wiring portion are displayed in a blinking manner or are highlighted by a method such as brightly shining, and the correspondence between the circuit and the mask layout is obtained. Is displayed. Not only the circuit diagram display section 31 designates a specific portion from the input means 13, but also a specific portion is designated from the net list display section 30 or the mask layout display section 32 designates a specific portion. May be designated so that the corresponding portions of the respective display units 30, 31 and 32 are displayed in a blinking manner, brightly shining, or in bold lines.

At the same time, the mask layout display section 32 is displayed.
The position information added to the mask layout data is sent to the IC internal analysis device 40 from the IC internal analysis device 4
When the value is 0, the designated area of the circuit wiring portion of the IC under test designated on the circuit diagram display section 31 is operated as an observation target. IC
The internal analyzer 40 is, for example, an electron beam tester (EB).
Tester) and an ion beam tester mainly composed of a charged particle beam tester, and one mainly composed of an optical microscope. For example, in a charged particle beam tester, an IC under test is placed in a vacuum chamber, and when the IC under test placed in the vacuum chamber is swept irradiated (irradiated while scanning) with a charged particle beam, the potential of the wiring portion is changed. Since the amount of secondary electrons emitted changes depending on the vertical direction, the amount of secondary electrons generated from each irradiation point is measured for each irradiation point, and the measured amount is captured as an electrical signal and processed in the IC. Potential contrast image (SEM image: Sc
anning Electron Microscope and SIM image: Scanning
Ion Microscope) and waveform data are obtained and stored in the observation image data storage unit and the waveform data storage unit, respectively.

The IC internal analysis device 40 also has an observation display section for displaying an observation image of image data and a waveform diagram of waveform data. The position information sent from the mask layout display unit 32 to the IC internal analysis device 40 is coordinate data and magnification data (corresponding to the measurement area), and the irradiation position of the IC under test can be specified by this position information. The mask layout and the observed image do not match perfectly at the time of manufacturing or because of accuracy problems in the analysis device.
Therefore, the measurer finely adjusts the X and Y coordinate positions of the IC to be measured while comparing the mask layout and the observed image, and after completely matching them, observes the observed image and the signal waveform to measure the IC to be measured.
Determines whether is operating normally.

[0012]

As described above, the conventional IC
The defect analysis device has a different idea from the IC defect analysis display device 20 that analyzes and displays information obtained from CAD data for IC manufacturing and the IC internal analysis device 40 that mainly includes a charged particle beam tester and an optical microscope. Since it was being developed, the interface between the two was insufficient. In particular, the transmission of information is the minimum necessary, and conventionally, the information obtained from the CAD data is transmitted to the observation image display unit or the like that displays the SEM image or the SIM image on the measurement side, for example, and only one way is used. Information transfer from CAD to CAD data side, so-called reverse CA
D information could not be transmitted. However, in reality, the measurer often found a defective portion of the IC from the image while observing the observed image or the waveform diagram of the measurement result. Therefore, conventionally, the defective part of the observed image is estimated by looking at the mask layout and the circuit diagram, and then the position information is sent from the mask layout side to check again, which makes the method of checking the defective part complicated and inconvenient. there were.

The present invention relates to an IC defect analysis display device and an IC.
By integrating with the observation display section of the internal analysis device so that data can be exchanged and displayed mutually, and by specifying a specific portion of the observation image or waveform diagram to be displayed on the measurement side display section, the CAD data side can be specified. It is an object of the present invention to provide an IC failure analysis apparatus that automatically displays a specific portion on the circuit diagram, mask layout, or netlist and promptly finds a defective portion of the IC.

[0014]

In order to achieve the above object, the present invention integrates the display unit and the operation unit of the entire system of the IC failure analysis device and newly adds necessary parts to form a workstation. Therefore, the conventional IC failure analysis display device 20 and the waveform data storage unit, the waveform diagram display unit, the observation image data storage unit and the observation image display unit, which are present in the IC internal analysis device 40, are integrated, A CAD data-to-measurement data collating unit is provided in the CAD data exchange unit to exchange data between the CAD data-to-measurement data collating unit and the conventional mask layout display unit and between the observed image display unit and the circuit diagram-to-mask layout collation unit. The work station will be configured to enable mutual exchange of information.

According to the structure of the present invention, the entire circuit diagram is initially displayed on the circuit diagram display unit, and the entire mask layout and the entire netlist are displayed on the respective display units. By designating a specific wiring of the mask layout display section with the input means, the net name is highlighted in the net list display section and the designated circuit section is highlighted in the circuit diagram display section. After that, the mask layout display section sends position information to the IC internal analysis device, and the IC internal analysis device starts to take an observation image. The observation image and the mask layout are compared and finely adjusted to match. Match three or more points on the entire screen with the mask layout and the observed image, and collate and store the observed coordinate data with the X and Y coordinate data of the mask layout. Other points are calculated by observing the coordinate on both screens. The data is made to match the X and Y coordinate data of the mask layout.

Therefore, after that, by designating a specific portion of the observation image or waveform diagram on the measurement side, the CAD data side circuit diagram, mask layout, and netlist display are displayed only on the specific portion designated on the measurement side. Can be done. As described above, according to the present invention, by designating a specific portion of the observation image or the waveform diagram on the measurement side, CA
The part is highlighted or printed on the D data side circuit diagram, mask layout, and netlist display.
The analysis of the defective part becomes easy, the complexity is eliminated, and the defect analysis can be performed in a short time.

[0017]

FIG. 1 shows an embodiment of the present invention. Portions corresponding to those in FIG. 3 are designated by the same reference numerals. In the present invention, the conventional display device 2 for IC failure analysis is installed in the workstation 50.
0 and the observation image data storage unit 3 in the IC internal analysis device 40
6, the observation image display unit 38, the waveform data storage unit 35, and the waveform diagram display unit 37 are integrated, and a CAD data / measurement data collation unit 33, a collation data B storage unit 34, and a switch circuit 39 are newly provided.

As a preparation step, the switch terminal of the switch circuit 39 is connected to the A side, and the input means 13 is connected to the mask layout display section 32. First, when all the circuit diagram data is stored in the circuit diagram data storage unit 27, the circuit diagram of the entire area is displayed on the circuit diagram display unit 31 by the initial menu, and the entire mask layout is displayed on the mask layout display unit 32. The net list display section 30 displays all net lists. Next, when a specific wiring portion of the mask layout display unit 32 is designated, the specified circuit portion is displayed on the circuit diagram display unit 31 based on the data of the collation data storage unit 29.
The specified netlist is displayed on the netlist display unit 30. At the same time, the mask layout display unit 32 sends the position information of the specific portion to the IC internal analysis device 40, and the IC internal analysis device 40 starts the analysis and displays the observation image on the observation image display unit 38. As described above, the observed image and the mask layout do not match at least once due to accuracy problems. Therefore, the measurer must check the X, Y of the IC to be measured.
Fine-tune the axes to get a perfect match.

At the end of the preparatory stage, the mask layout and the observed image are perfectly matched at coordinates of three or more points, preferably four corners, out of all the mask layouts, and the observation position data on the measurement side and the CAD side are measured for each point. And the coincidence with the X and Y coordinate data of is acquired and stored. That is, the X and Y coordinate data of the mask layout are fetched from the mask layout display section 32 to the CAD data vs. measurement data collating section 33 and stored in the collation data B storage section 34 in correspondence with the current observation position data. The matching data is transmitted from the observed image display unit 38 to the circuit-to-mask layout matching unit 25 and stored in the matching data storage unit 29. Then, the other observation position coordinates are calculated based on the reference point so that the front surface coincidence can be obtained.

In the measuring stage, the switch terminal of the switch circuit 39 is switched to the B side, and the input means 13 and the observation image display section 38 are connected. At this time, if the positions of the observed image and the mask layout do not match, the X and Y coordinate axes of the IC to be measured are finely adjusted to achieve perfect matching. After that, IC to be measured
The X and Y coordinates of are moved and the defective portion of the IC to be measured is observed. The amount of movement is transmitted from the observed image display unit 38 to the circuit diagram-to-mask layout collation unit 25, and the data is transmitted to the mask layout display unit 32, the circuit diagram display unit 31, and the net list display unit 30 to form an observed image. Followed and displayed. When a defective portion is found in the observation image, the observation image and the mask layout are matched again if necessary. Then, as shown in FIG. 2, when a specific portion of the image of the observation image display unit 38 is designated by the input means 13,
The net name is displayed in the designated portion, and a specific portion within a certain range is displayed on the screens of the other display units. And
The designated part is displayed in a blinking manner, brightly shining, or in bold lines so that it can be easily understood.

The observation image data storage unit 36 receives and stores the observation image data from the IC internal analysis device 40, and sends the data to the observation image display unit 38 for display. The waveform data storage unit 35 receives and stores the waveform data from the IC internal analysis device 40, and sends the data to the waveform diagram display unit 37 for display. The arithmetic control unit 39 performs necessary arithmetic and control in the IC failure analysis device.

It should be noted that, in the above description, for easy understanding, the data is displayed in all the display parts, that is, the net list display part 30, the circuit diagram display part 31, the mask layout display part 32, the waveform diagram display part 37 and the observation. Although it is described that the image is displayed on the image display unit 38, the minimum required display unit is only the mask layout display unit 32 and the observation image display unit 38, and the others may be only the printout.

[0023]

As described above, according to the present invention, a defective portion is found in an observation image or a measurement waveform diagram which is a graphic of a measurement result measured by the IC internal analysis device 40, and a specific portion of the observation position is input means. By specifying from 13, the specified portion is automatically displayed with the mask layout on the CAD data side, the circuit diagram and the net name, and can be printed out. That is, the so-called reverse CAD information can be transmitted and displayed for the first time, the defective portion can be found and resolved quickly, human error can be prevented, complexity can be eliminated, and operability is greatly improved. The economic effect is great.

[Brief description of drawings]

FIG. 1 is a diagram of an embodiment of the present invention.

FIG. 2 is an example of a display state of the embodiment shown in FIG.

FIG. 3 is a block diagram for explaining a conventional technique.

4 is a diagram showing an example of a netlist used in the conventional example shown in FIG.

5 is a connection diagram showing an example of a circuit diagram drawn in the conventional example shown in FIG.

FIG. 6 is a diagram showing a display state of the conventional example shown in FIG.

[Explanation of symbols]

 10, 11 and 12 External storage device 13 Input means 20 IC defect analysis display device 21 Netlist data conversion unit 22 Mask layout data conversion unit 23 Netlist pair mask layout collation unit 24 Netlist-circuit diagram generation unit 25 Circuit diagram pair Mask layout collation unit 26 Netlist data storage unit 27 Circuit diagram data storage unit 28 Mask layout data storage unit 29 Collation data storage unit 30 Netlist display unit 31 Circuit diagram display unit 32 Mask layout display unit 33 Circuit diagram vs. measurement data collation unit 34 collation data B storage unit 35 waveform data storage unit 36 observation image data storage unit 37 waveform diagram display unit 38 observation image display unit 39 switch circuit 40 IC internal analysis device 41 arithmetic control unit 50 workstation

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshimichi Iwai 1-32-1, Asahimachi, Nerima-ku, Tokyo Within Advantest, Inc.

Claims (1)

[Claims] 1. CAD data is input, netlist data based on the CAD data and mask layout data are collated by a collating unit, and a mask layout corresponding to a specific portion designated by the input means can be displayed. On the other hand, inside the IC. An observation image can be displayed with the measurement data from the analyzer I
In a C failure analysis device, a CAD data-to-measurement data collating unit (33) that associates the measurement data with the mask layout data, and an input that specifies a specific portion of the observation image to be displayed on the observation image display unit (38). An IC failure analysis apparatus comprising: a means (13); and a mask layout display section (32) for displaying the mask layout corresponding to the specified portion from the measurement data of the specified specified portion.