JPH07131738A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To suppress reduction in an intermediate frequency automatic gain control voltage for a pattern period and to increase a rate of rise of the intermediate frequency automatic gain control voltage for a synchronization period. CONSTITUTION:Switches SW1, SW2 are turned off and on respectively for a horizontal synchronization period and the switches SW1, SW2 are turned on and off respectively for a pattern period in a horizontal synchronizing signal detection circuit 25. A hold voltage setting terminal of a hold circuit 22 is connected to a reference potential point via a parallel connection of a buffer amplifier 24 and a capacitor C2 for the horizontal synchronization period and connected to a reference potential point via a parallel connection of a resistor R1 and a capacitor C4 for the pattern period. Thus, the reduction in the intermediate frequency automatic gain control voltage is suppressed for the pattern period and the rate of rise of the intermediate frequency automatic gain control voltage is increased for the synchronization period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for controlling the gain of an intermediate frequency signal input to a video detection circuit, and more particularly to an automatic gain control circuit capable of preventing line tilt during a picture period.

[0002]

2. Description of the Related Art In recent years, satellite broadcast receivers for receiving satellite broadcasts (hereinafter referred to as BS broadcasts) have become widespread in general households. In such BS broadcasting, there is also a scramble broadcasting system in which a broadcasting station encrypts (scrambles) a television signal so that only a receiving contractor can decipher the code and view it. As such a scrambling method, there are a line rotation method in which a break is made in each video signal line and the left and right are switched, a line permutation method in which the video signal line is switched, and the like. JSB (Japan Satellite Broadcasting inc) The line rotation system is adopted in.

FIG. 10 is a circuit diagram showing a video signal processing circuit for performing video signal processing on the intermediate frequency signal scrambled by the line rotation method.

In FIG. 10, reference numeral 81 is an input terminal to which an intermediate frequency signal (hereinafter referred to as an IF signal) a8 from a satellite broadcast tuner is guided. The IF signal a8 guided to the input terminal 81 is an IF amplifier circuit. 82. IF
The amplifier circuit 82 receives the IF signal a8 guided to the input terminal 81.
In contrast, an automatic gain control circuit (AGC circuit) 90 described later
The gain is controlled on the basis of the IFAGC voltage Va8 from and is supplied to the video detection circuit 83 as an IF signal b8.
The video detection circuit 83 receives the IF signal b from the AGC circuit 82.
8 is subjected to AM detection, converted into a composite video signal c8 and supplied to the video amplifier circuit 84. The image amplification circuit 84 is
The composite video signal c8 from the video detection circuit 83 is amplified at a predetermined amplification factor and guided to the output terminal 85 as a composite video signal d8 and also to the automatic gain control circuit (hereinafter referred to as AGC circuit) 90. The AGC detection circuit 90 creates the IFAGC voltage Va8 based on the composite video signal d8 from the video amplification circuit 83 and supplies it to the IF amplification circuit 82.

The composite video signal d8 led to the output terminal 85
When the line rotation type scramble is performed by the descrambler, it is descrambled, converted into a normal composite video signal, displayed on a video display means such as a cathode ray tube, and scrambled. If it does not exist, it is converted into a normal composite video signal as it is and displayed on a video display means such as a cathode ray tube.

The AGC circuit 90 will be described in more detail below.

The AGC detection circuit 91 of the AGC circuit 90 is
The peak value of the horizontal synchronizing signal of the composite video signal d8 from the video amplifying circuit 84 is detected, the amplitude of the pulse is inversely proportional to the leading value, and the AGC becomes a pulse signal synchronized with the horizontal synchronizing signal of the composite video signal d8. The detection voltage Vb8 is created and supplied to the hold circuit 92.

The hold circuit 92 has a resistor R8 and a capacitor C8 whose hold voltage setting terminals form a time constant circuit.
Is connected to the reference potential point via a parallel connection of
When the C detection voltage Vb8 is in a pulse period (horizontal synchronization period), a voltage is applied to the hold voltage setting terminal based on the pulse amplitude of the AGC detection voltage Vb8, and the capacitor C
8 is charged, and when the AGC detection voltage Vb8 is in a period other than the pulse (pattern period), the application of the voltage to the hold voltage setting terminal is stopped, and the discharge of the electric charge accumulated in the capacitor C8 is released by the resistor R8, The emission is performed via the discharge paths of the AGC detection circuit 91 and the AGC amplification circuit 93. Then, the hold circuit 92 sets the IFAGC voltage Vc8 similar to the voltage generated at the hold voltage generating terminal to A
It is supplied to the GC amplifier circuit 93. The AGC amplifier circuit 93
The IFAGC voltage Vc8 from the hold circuit 92 is amplified and supplied to the control signal input terminal of the AGC circuit 82 as the IFAGC voltage Va8.

FIG. 11 is a timing chart showing the operation of such a conventional video signal processing circuit.
11A shows the composite video signal d8, and FIG. 11B shows AG
The C detection voltage Vb8 is shown, and FIG. 11C shows the IFAGC voltage Vc8.

First, the IF signal a led to the input terminal 81
8 is converted into a composite video signal d8 shown in FIG. 11A through the IF amplification circuit 82, the video detection circuit 83, and the video amplification circuit 84. Composite video signal d in this case
The AGC detection circuit 91 detects the peak value of the horizontal synchronizing signal 8, and the amplitude is inversely proportional to the leading value and is converted into a pulse signal synchronized with the horizontal synchronizing signal. As a result, the AGC detection circuit 91 causes the AGC detection circuit 91 shown in FIG.
The detection voltage Vb8 is created and supplied to the hold circuit 92.

The hold circuit 92 has an AG during the horizontal synchronization period.
By charging the capacitor C8 based on the amplitude of the pulse of the C detection voltage Vb8 and discharging the charge accumulated in the capacitor C8 during the pattern period through the resistor R8, the discharge path of the AGC detection circuit 91 and the AGC amplification circuit 93, Figure 11
As shown in (c), a constant voltage is generated during the horizontal synchronizing period, and during the picture period, an IFAGC voltage Vc8 whose voltage value decreases with a slope based on the time constants of the capacitor and the resistance is created and provided to the IF amplifier circuit 82. Supply. As a result, FIG.
The phenomenon (line tilt) in which the level of the video signal component of the composite video signal d8 shown in (a) in the picture period is inclined more than the original video signal component shown by the broken line occurs.

FIG. 12 is a waveform diagram showing a case where descrambling processing is performed on the composite video signal d8 in which such a line tilt has occurred, and FIG. 12A shows the composite video signal d8 and FIG. b) shows a composite video signal that has been descrambled.

In FIG. 12A, the composite video signal d8
Indicates that the left and right sides of the video signals A8 and B8 have been swapped with the timing T8 set on the broadcast station side as a break, and when they are displayed on the screen as they are, the left and right sides of the video signals are swapped. . Where timing T
Since 8 is set individually for each line, when such a composite video signal d8 is displayed on one screen, the video has almost no shape. Here, the video signal component of the composite video signal d8 is inclined more than the original video signal component shown by the broken line by the AGC operation shown in FIG. When descrambling such composite video signal d8, the left and right video signals A8 and B8 are interchanged.
As a result, the descrambled composite video signal causes the restoration error shown in FIG. Such a restoration error appears as a sharp increase in brightness on the screen, and is considerably conspicuous in the case of a flat image such as a clear sky or a wall. In order to solve such a problem, it is conceivable to change the time constant of the hold circuit 92 by changing the capacitances of the capacitor C8 and the resistor R8 of FIG.

FIG. 13 is an explanatory diagram showing a change in the IFAGC voltage Va8 when the amplitude of the composite video signal d8 is lowered due to a change in the reception state. In FIG. 13A, the time constant of the hold circuit 92 is set small. FIG. 13 shows the case.
(B) shows the case where the time constant of the hold circuit 92 is set large.

When the time constant of the hold circuit 92 is set small, the capacitance of the capacitor C8 is set small and the voltage change due to charging and discharging of the capacitor C8 is increased. In the AGC circuit 90 in which the time constant is set in this way, when the amplitude of the composite video signal d8 decreases due to a change in the reception state (for example, a disturbance such as a helicopter passing between a broadcasting satellite and a parabolic antenna). , IFAGC voltage V
As shown in FIG. 13A, a8 sharply rises at the rising timing of the horizontal synchronizing period, and the voltage value decreases with a slope based on the time constant of the capacitor C8 and the resistor R8 during the picture period, and as a whole. Will increase by V81 in three horizontal scanning periods. In this case, since the inclination of the pattern period becomes large, the restoration error shown in FIG. 12 becomes large.

When the time constant of the hold circuit 92 is set large, the capacitance of the capacitor C8 is set large, and the voltage change due to charging and discharging of the capacitor C8 is made small. In the AGC circuit 90 in which the time constant is set in this way, when the amplitude of the composite video signal d8 decreases, the IFAGC
As shown in FIG. 13B, the voltage Va8 gradually rises at the rising timing of the horizontal sync signal, and the voltage value decreases with a slope based on the time constant of the capacitor C8 and the resistor R8 during the picture period, As V in three horizontal scanning periods
It will rise by 82. In this case, the inclination of the picture period can be reduced to reduce the restoration error shown in FIG. 12, but the rate of increase in the voltage value during the horizontal synchronization period is low, and the voltage value rises in three horizontal scanning periods as a whole. V82 becomes lower than V81 in FIG. 13 (a), and as a result, the follow-up to disturbance is lowered.

[0017]

In the conventional automatic gain control circuit described above, when the time constant of the hold circuit is set small, the slope of the intermediate frequency automatic gain control voltage during the pattern period becomes large, and When the time constant of the hold circuit is set small, the recovery error of the scrambled composite video signal will be large, and the increase in the intermediate frequency automatic gain control voltage during the horizontal synchronization period will be low, and the composite video signal Therefore, the followability of the intermediate frequency automatic gain control voltage with respect to the change of is decreased.

The present invention eliminates the above problems, suppresses the decrease of the intermediate frequency automatic gain control voltage during the picture period, and increases the rate of increase of the intermediate frequency automatic gain control voltage during the synchronization period. The purpose is to provide a gain control circuit.

[0019]

The automatic gain control circuit of the present invention determines the gain of an intermediate frequency signal input to the video detection circuit based on the level of the synchronizing signal of the composite video signal detected by the video detection circuit. An automatic gain control circuit for controlling, wherein the automatic gain control detection is a pulse signal whose amplitude is set on the basis of the synchronization signal of the composite video signal, in synchronization with the synchronization signal of the composite video signal from the video detection circuit. An automatic gain control detection circuit that creates a voltage, and holds the automatic gain control detection voltage from the automatic gain control detection circuit based on a set time constant, and inputs the voltage to the video detection circuit based on the held voltage. A hold circuit for controlling the gain of the intermediate frequency signal and a time constant of the hold circuit for the first time when the composite video signal from the video detection circuit is in the synchronization period. And a time constant switching means for setting the time constant of the hold circuit to a second time constant larger than the first time constant when the composite video signal is in the picture period. Is characterized by.

[0020]

According to this structure, the time constant of the hold circuit is set to the first time constant when the time constant switching means is in the synchronizing period, and the time constant of the hold circuit is set in the case of the picture period. Since it is set by switching to the second time constant which is larger than the first time constant, the decrease of the intermediate frequency automatic gain control voltage during the picture period is suppressed, and the increase rate of the intermediate frequency automatic gain control voltage during the synchronization period is suppressed. Can be increased.

[0021]

The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 is a block diagram showing a case where an embodiment of the automatic gain control circuit according to the present invention is applied to a video signal processing circuit.

In FIG. 1, the I input to the input terminal 11
The F signal a1 is supplied to the IF amplification circuit 12 and the AGC circuit 2 described later.
The gain is controlled based on the IFAGC voltage Va1 from 0, and is supplied to the video detection circuit 13 as the IF signal b1. The video detection circuit 13 converts the IF signal b1 from the AGC circuit 12 into a composite video signal c1 and converts the IF signal b1 into a composite video signal c1.
Supply to. The video amplification circuit 14 amplifies the composite video signal c1 from the video detection circuit 13 at a predetermined amplification rate and guides it to the output terminal 15 as a composite video signal d1 and also to the AGC circuit 20. The AGC detection circuit 20 outputs an IF signal based on the composite video signal d1 from the video amplification circuit 13.
The AGC voltage Va1 is created and supplied to the control signal input terminal of the IF amplifier circuit 12.

The AGC circuit 20 will be described in more detail below.

The AGC detection circuit 21 of the AGC circuit 20 is
The peak value of the horizontal synchronizing signal of the composite video signal d1 from the video amplifier circuit 14 is detected, the amplitude of the pulse is inversely proportional to this leading value, and the AGC becomes a pulse signal synchronized with the horizontal synchronizing signal of the composite video signal d1. The detection voltage Vb1 is created and supplied to the hold circuit 22.

The hold circuit 22 has a hold voltage setting terminal connected to a reference potential point through a parallel connection of a resistor R1 and a capacitor C1 similar to the resistor R1 and the capacitor C1 of the conventional example shown in FIG. In addition to this, the hold voltage setting terminal of the hold circuit 22 is connected to one terminal of the switch SW1 and also connected to one terminal of the switch SW2 via the buffer amplifier 24. Switch S
The other terminals of W1 and SW2 are connected to a reference potential point via a capacitor C2. On the other hand, the horizontal sync signal detection circuit 25 detects the horizontal sync signal of the composite video signal d1 and turns off the switch SW1 and switches S during the horizontal sync period.
The switch control signals e1 and f1 for turning on W2 are supplied to the switches SW1 and SW2, respectively, and the switch control signals e1 and f1 for turning on the switch SW1 and turning off the switch SW2 are supplied to the switches SW1 and SW1 during the picture period, respectively.
Supply to 2. As a result, the resistor R1 and the capacitor C
1, C2, switches SW1 and SW2, buffer amplifier 2
4 and the horizontal synchronizing signal detecting circuit 25 constitute a time constant switching means.

The hold circuit 22 uses the AGC detection voltage Vb.
When 1 is the horizontal synchronization period, a voltage is applied to the hold voltage setting terminal based on the pulse amplitude of the AGC detection voltage Vb1, and when the AGC detection voltage Vb1 is the pattern period, the voltage is applied to the hold voltage setting terminal. The application is stopped, and the IFAGC voltage Vc1 similar to the voltage generated at the hold voltage generating terminal is supplied to the AGC amplifier circuit 23. The AGC amplifier circuit 23 receives the IFAGC voltage V from the hold circuit 22.
c1 is amplified and the AGC is set as the IFAGC voltage Va1.
Supply to the circuit 12.

FIG. 2 is a timing chart showing the operation of such a conventional video signal processing circuit. FIG. 2 (a) shows a composite video signal d1 and FIG. 2 (b) shows a switch SW1.
2 (c) shows the state of the switch SW2, FIG. 2 (d) shows the AGC detection voltage Vb1, and FIG.
(E) shows the IFAGC voltage Vc1.

First, the IF signal a led to the input terminal 11
1 is converted into a composite video signal d1 shown in FIG. 2A through the IF amplifier circuit 12, the video detection circuit 13, and the video amplifier circuit 14. Horizontal sync signal detection circuit 25
Controls the switches SW1 and SW2 based on the detection result of the horizontal synchronizing signal of the composite video signal d1 in this case.
As a result, the switch SW1 is turned off during the horizontal synchronizing period and turned on during the pattern period as shown in FIG. Also,
The switch SW2 is turned on during the horizontal synchronization period and turned off during the pattern period as shown in FIG. On the other hand, this allows
During the horizontal synchronizing period, the hold voltage setting terminal of the hold circuit 22 is connected to the reference potential point via the parallel connection of the resistor R1 and the capacitor C1, and is connected to the reference potential point via the buffer amplifier 24 and the capacitor C2. Connected. In the picture period. The hold voltage setting terminal of the hold circuit 22 is connected to the reference potential point through the parallel connection of the resistor R1 and the capacitors C1 and C2. On the other hand, the AGC detection circuit 21 creates the AGC detection voltage Vb1 shown in FIG. Hold circuit 2
2 charges the capacitor C1 based on the amplitude of the pulse of the AGC detection voltage Vb1 during the horizontal synchronization period, and
The capacitor C2 is charged via the buffer amplifier 24,
By discharging the charge accumulated in the capacitors C1 and C2 during the pattern period through the resistor R1, the discharge path of the AGC detection circuit 21 and the AGC amplification circuit 23,
As shown in (e), the IF is a constant voltage during the horizontal synchronizing period, and the voltage value decreases with a gentle slope based on the time constant of the capacitors C1 and C2 and the resistor R1 during the picture period.
The AGC voltage Vc1 is created and supplied to the IF amplifier circuit 12.

Here, during the horizontal synchronizing period, the capacitor C2 is charged through the buffer amplifier 24, so the time constant of the hold circuit 22 is low, and during the picture period, the capacitors C1 and C2 are accumulated. The electric charge remains as it is, the resistor R1, the AGC detection circuit 21 and the AGC.
Since it is discharged through the discharge path of the amplifier circuit 23, the time constant of the hold circuit 22 becomes high. This allows
The difference between the video signal component in the picture period of the composite video signal d1 shown in FIG. 2A and the original video signal component is reduced. That is,
The line tilt will be reduced.

FIG. 3 is an explanatory diagram showing changes in the IFAGC voltage Va1 when the amplitude of the composite video signal d1 is lowered due to changes in the reception state.

In the AGC circuit 20 of the present embodiment, the time constant is low during the horizontal synchronizing period, and the time constant is high during the picture period. Therefore, the amplitude of the composite video signal d1 is lowered due to the change in the receiving state. IFAG
The C voltage Va1 sharply rises at the rising timing of the horizontal synchronizing signal, the voltage value decreases with a gentle slope at a low time constant during the picture period, and V11 rises as a whole in three horizontal scanning periods. . In this case, V1 in this case
1 is equal to or higher than V81 in FIG.
The GC circuit 20 keeps the followability of the IFAGC voltage high. According to such an embodiment, it is possible to suppress the decrease of the IFAGC voltage during the picture period and increase the rate of increase of the IFAGC voltage during the horizontal synchronization period. Against IFAG
It is possible to reduce the restoration error of the descrambled composite video signal while keeping the followability of the C voltage high.

FIG. 4 is a block diagram showing another embodiment of the automatic gain control circuit according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof is omitted.

In FIG. 4, the horizontal sync signal detection circuit 35 of the AGC circuit 30 detects the horizontal sync signal of the composite video signal d1, and the switch control signal e similar to the embodiment of FIG.
1 and f1 are supplied to the switches SW1 and SW2, respectively, and the horizontal synchronization detection signal g1 which becomes a high level pulse during the horizontal synchronization period is supplied to the horizontal synchronization signal abnormality detection circuit 36. The switches SW1 and SW2 are turned off when the switch control signals e1 and f1 are high level, respectively.

The horizontal sync signal abnormality detection circuit 36 determines whether or not there is an abnormality such as fluttering caused by an external factor by detecting whether or not the cycle of the horizontal sync signal indicated by the horizontal sync detection signal g1 is normal. When it is determined that there is no abnormality, the switches SW1 and SW2 are not supplied with voltage and the switch is caused to operate based on the control of the horizontal synchronization signal detection circuit 35, and it is determined that there is abnormality. In this case, a high level voltage is supplied to the switches SW1 and SW2 to forcibly turn them off for 200 msec.

The other structure is similar to that of the embodiment shown in FIG.

FIG. 5 shows the horizontal sync signal abnormality detection circuit 3 of FIG.
FIG. 6 is a circuit diagram showing 6 in more detail.

In FIG. 5, reference numeral 21 is an input terminal to which the horizontal sync detection signal g1 is guided. The horizontal sync detection signal g1 guided to this input terminal 21 is a 4-bit counter 42.
Of the clock signal input terminal CLK IN and the clear terminal CLR of the 4-bit counter 43.

The clock signal generating circuit 44 supplies the clock signal h1 having a frequency of 1/16 of the normal horizontal synchronizing signal to the clear terminal CLR of the 4-bit counter 42. As a result, the 4-bit counter 42 has the horizontal sync detection signal g1.
Overflows when the frequency exceeds the normal horizontal synchronizing signal, and a high level voltage indicating overflow is supplied from the overflow terminal OVER to the input terminal of the monomulti 46.

The clock signal generation circuit 45 supplies the clock signal i1 having a frequency 16 times that of the normal horizontal synchronizing signal to the clock signal input terminal CLK IN of the 4-bit counter 43. As a result, the 4-bit counter 43 overflows when the frequency of the horizontal sync detection signal g1 falls below the normal horizontal sync signal, and the overflow terminal OVE
A high level voltage indicating overflow is supplied from R to the input terminal of the monomulti 46.

When the voltage supplied to the input terminal of the monomulti 46 becomes high level, the switch SW is switched from the output terminal to the switch SW for 200 msec after the voltage becomes high level.
1, SW2 is supplied with a high level voltage to forcibly turn off.

According to such an embodiment, the same effect as the embodiment of FIG. 1 is obtained, and the horizontal synchronizing signal detecting circuit 3 is also provided.
5 does not detect the normal horizontal synchronizing signal, that is, when the footer ringing occurs due to an external factor such as a channel selection transition period or fading, the hold circuit 22 is compared with the conventional resistor R1 and capacitor C1. It is possible to prevent circuit runaway by operating with a time constant at a relatively low level.

FIG. 6 is a block diagram showing another embodiment of the automatic gain control circuit according to the present invention.

In FIG. 6, the AGC detection voltage abnormality detection circuit 56 of the AGC circuit 50 detects the abnormality of the composite video signal d1 by detecting the voltage fluctuation range of the AGC detection voltage Vb1 and causes fluttering due to external factors. It is determined whether or not there is an abnormality such as, and when it is determined that there is no abnormality, the voltage is not supplied to the switches SW1 and SW2,
When the switches are caused to operate under the control of the horizontal synchronizing signal detection circuit 35 and it is determined that there is an abnormality, a high level voltage is supplied to the switches SW1 and SW2 to forcibly turn them off.

FIG. 7 is a circuit diagram showing the AGC detection voltage abnormality detection circuit 56 of FIG. 6 in more detail.

In FIG. 7, reference numeral 61 is an input terminal to which the AGC detection voltage Vb1 is introduced.
Is an amplifier 62, a capacitor C6 and resistors R61, R6
It is connected to the reference potential point via two series connections. Resistance R
The connection point of 61 and R62 is connected to the base of the transistor Tr6.

On the other hand, the DC voltage V6 is led to the input terminal 61. The input terminal 61 is connected to the reference potential point via the resistor R63 and the collector-emitter path of the transistor Tr6. The collector of the transistor Tr6 is guided to the input terminal of the monomulti 64. When the voltage supplied to the input terminal of the mono-multi 64 changes from high level to low level, 200
During msec, a high-level voltage is supplied from the output terminal to the control signal input terminals of the switches SW1 and SW2 to forcibly turn off.

Such an AGC detection voltage abnormality detection circuit 5
The operation of No. 6 will be described below.

When the voltage fluctuation range of the AGC detection voltage Vb1 exceeds a predetermined value due to the occurrence of footing, the transistor Tr6 is turned on and the monomulti 64 switches the voltage supplied to its input terminal from the high level to the low level. Instead, switch SW from the output terminal for 200 msec.
A high-level voltage is supplied to the control signal input terminals of SW1 and SW2 to forcibly turn off. As a result, the hold circuit 2
2 can be operated with a relatively low level time constant by the resistor R1 and the capacitor C1 as in the conventional case, and runaway of the circuit can be prevented.

According to such an embodiment, the same effect as that of the embodiment of FIG. 5 is obtained, and since an expensive circuit such as a 4-bit counter is not required, the manufacturing cost is reduced as compared with the embodiment of FIG. it can.

FIG. 8 is a block diagram showing still another embodiment of the automatic gain control circuit according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof is omitted. .

In FIG. 8, the abnormality detection circuit 66 of the AGC circuit 60 includes an AGC detection voltage Vb1 and a hold circuit 22.
Of the composite video signal d1 is detected by comparing the difference between the hold voltage setting terminal voltage Vd1 and the hold voltage setting terminal voltage Vd1. If the comparison result exceeds a predetermined value, the switches SW1, SW
A high-level voltage is supplied to the control signal input terminal 2 to forcibly turn off.

According to such an embodiment, the same effect as that of the embodiment of FIG. 7 can be obtained.

FIG. 9 is a block diagram showing still another embodiment of the automatic gain control circuit according to the present invention.

In FIG. 9, the scramble flag judging circuit 76 of the AGC circuit 70 judges whether or not the composite video signal d1 is scrambled by judging the scramble flag from the scramble day coder. When scrambling is performed, a high level voltage is supplied to the control signal input terminals of the switches SW1 and SW2 to forcibly turn off the switches SW1 and SW2.

According to such an embodiment, when the scramble is performed on the composite video signal d1, the same effect as that of the embodiment of FIG. 1 can be obtained, and when the scramble is not performed. Is the same resistance R1 as the conventional one.
It is possible to prevent runaway of the circuit by operating with a relatively low level time constant by the capacitor C1 and the capacitor C1. In addition, this embodiment has an effect that it is possible to reduce the chances of charging the capacitor C2 and to use an inexpensive capacitor C2 having low durability.

In the embodiment shown in FIGS. 1 to 9, the horizontal sync signal of the decoding sync signal d1 is detected and the time constant is switched. The time constant may be switched by detecting both of the synchronization signals. Further, although the embodiments shown in FIGS. 1 to 9 are applied to the AGC circuit that performs AGC of the scrambled IF signal by the line rotation method, the IF signal by the line permutation method is applied. It may be applied to an AGC circuit that performs AGC.
In this case, the followability of the IFAGC voltage can be made high while the line tilt of the screen is kept low, so that the restoration error between the upper and lower lines can be reduced. Further, the embodiments shown in FIGS. 1 to 8 may be applied to an AGC circuit that performs AGC of an IF signal that is not likely to be scrambled. Also in this case, there is an effect that the line tilt can be reduced. Furthermore, FIG.
In the embodiment shown in FIG. 8, the switches SW1 and SW2 are
Although the time for forcibly turning off is set to 200 msec as a time when the viewer does not feel uncomfortable, it may be set to another time. Further, in the embodiment shown in FIG. 9, the scramble flag determination circuit 76 is used to generate the composite video signal d1.
Although the present invention is applied to the one for determining whether or not the video signal component is scrambled, it may be applied to the one for determining whether or not the synchronization signal is scrambled.

[0058]

According to the present invention, the decrease of the intermediate frequency gain control voltage during the picture period can be suppressed and the rate of increase of the intermediate frequency automatic gain control voltage during the synchronization period can be increased. While maintaining the high followability of the IFAGC voltage with respect to the signal change, the restoration error of the descrambled composite video signal can be reduced and the line tilt can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic gain control circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

FIG. 3 shows I when the amplitude of a composite video signal is lowered.
Explanatory drawing which shows the change of FAGC voltage.

FIG. 4 is a block diagram showing another embodiment of the automatic gain control circuit according to the present invention.

5 is a circuit diagram showing the horizontal sync signal abnormality detection circuit of FIG. 4 in more detail.

FIG. 6 is a block diagram showing another embodiment of the automatic gain control circuit according to the present invention.

7 is a circuit diagram showing the AGC detection voltage abnormality detection circuit of FIG. 6 in more detail.

FIG. 8 is a block diagram showing still another embodiment of the automatic gain control circuit according to the present invention.

FIG. 9 is a block diagram showing still another embodiment of the automatic gain control circuit according to the present invention.

FIG. 10 is a circuit diagram showing a conventional video signal processing circuit.

11 is a timing chart showing the operation of the video signal processing circuit of FIG.

12 is a waveform diagram showing a case where descramble processing is performed on the composite video signal output from the video signal processing circuit of FIG.

13 is an explanatory diagram showing changes in the IFAGC voltage when the amplitude of the composite video signal output from the video signal processing circuit in FIG. 10 is reduced.

[Explanation of symbols]

 12 IF amplification circuit 13 Video detection circuit 20 AGC circuit 21 AGC detection circuit 22 Hold circuit 23 AGC amplification circuit 24 Buffer amplifier 25 Horizontal sync signal detection circuit C1, C2 Capacitor R1 Resistor SW1, SW2 switch

Claims (4)

[Claims] 1. An automatic gain control circuit for controlling the gain of an intermediate frequency signal input to said video detection circuit based on the level of a synchronizing signal of a composite video signal detected by said video detection circuit, said video detection circuit comprising: An automatic gain control detection circuit that is synchronized with the synchronization signal of the composite video signal from the circuit and creates an automatic gain control detection voltage that becomes a pulse signal whose amplitude is set based on the synchronization signal of the composite video signal. A hold circuit for holding the automatic gain control detection voltage from the automatic gain control detection circuit based on the time constant, and controlling the gain of the intermediate frequency signal input to the video detection circuit based on the held voltage; When the composite video signal from the video detection circuit is in the synchronizing period, the time constant of the hold circuit is set to the first time constant, and when the composite video signal is in the picture period. In this case, the automatic gain control circuit further comprises a time constant switching means for switching and setting the time constant of the hold circuit to a second time constant larger than the first time constant. 2. The holding circuit determines whether the cycle of the sync signal of the composite video signal from the video detection circuit is normal or not, and if the judgment indicates that the cycle is not normal, 2. The automatic gain control circuit according to claim 1, wherein the time constant switching means is provided with a synchronization signal abnormality detection circuit for forcibly switching the constant to a constant third time constant. 3. A voltage fluctuation range of the automatic gain control detection voltage from the automatic gain control detection circuit is detected, and when the voltage fluctuation range exceeds a predetermined value, the time constant of the hold circuit is kept constant. 2. The automatic gain control circuit according to claim 1, wherein the time constant switching means is provided with an automatic gain control detection voltage abnormality detection circuit for forcibly switching to the time constant. 4. The composite video signal from the video detection circuit is determined whether or not scrambled, and when it is determined that the scramble is not performed, the time constant of the hold circuit is set to a constant value. 2. The automatic gain control circuit according to claim 1, wherein the time constant switching means is provided with a scramble determination circuit for forcibly switching to a time constant of 3.