JPH07131314A - Arranging method for switching element of high frequency inverter - Google Patents

Abstract

PURPOSE:To provide the arranging method for elements unnecessitating a snubber circuit or the like concerning a high frequency inverter provided with plural switching elements respectively on the respective arms of a full bridge. CONSTITUTION:Respective switching elements Ai and Di of arms (a) and (d) of a DC input bus 1 and respective switching elements Bi and Ei of arms (b) and (e) connected to a DC input bus 3 are connected one by one. At the same time, bypass capacitors Ci are connected near those elements between the DC input buses one by one, the junction of the switching elements Ai and Bi of the arms (a) and (b) is connected to an AC output bus 5, and the junction of the switching elements Di and Ei of the arms (d) and (e) is connected to an AC output bus 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging switching elements of a high frequency inverter.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional full-bridge circuit in which each arm a, b, d, e has one FET element A,
It is a circuit diagram of the high frequency inverter provided with B, D, and E.
The upper ends of the FET elements A and D of the arms a and d are connected to the DC input busbar 1, the lower ends of the FET elements B and E of the arms b and e are connected to the DC input busbar 3, and the FET elements A and B are connected in series. The connection point is connected to the AC output bus bar 5. Similarly, the FET elements D and E are connected in series, and the connection point is connected to the AC output bus bar 7. Further, in order to protect the FET elements by absorbing the spike voltage generated by the switching of each FET element, the bypass capacitor C is
It is connected between DC busbars near the FET element.

When the output current required for the inverter exceeds the rated current of one FET element, several FET elements (three in the figure) are used in parallel as shown in FIG. 3 (a). . A mounting example in which the three FET elements A1, A2, A3 and B1, B2, B3 of each of the arms a and b and the bypass capacitor C are arranged on the printed board is shown in FIG.
It is shown in (b).

[0004]

In parallel operation of the FET elements as described above, each element A1, A2, A3, B
When 1, B2 and B3 are arranged as shown in FIG. 3B, the distance between each FET element and the bypass capacitor C is sequentially increased, and the inductance of the wiring connecting each FET element and the bypass capacitor C is increased. This inductance causes resonance with the bypass capacitor C, and the voltage may jump up. Since this jump-up voltage may damage the FET element, a snubber circuit or the like is required to suppress it.

The snubber circuit is formed by connecting a parallel circuit of a diode and a resistor to a capacitor, and is connected in parallel with the FET element. In this circuit, the electric charge absorbed in the capacitor is discharged each time the FET element is turned on, so that the power loss cannot be ignored even if the capacitance of the capacitor is small. Further, there is a problem that the mounting space becomes large due to the cooling of the resistance.

The present invention has been made in view of such a problem, and an object thereof is to provide a method for arranging a switching element of a high-frequency inverter with a small voltage jump by appropriately arranging a switching element and a bypass capacitor. And

[0007]

In order to achieve the above object, a method of arranging a switching element of a high frequency inverter according to the present invention is provided with arms a, b, and a full bridge circuit.
In a high-frequency inverter having a plurality of switching elements in d and e, one end of each switching element in arm a and arm d is connected to one of the DC input buses,
One end of each switching element of arm b and arm e is connected to another one of the DC input buses, and the other end of each switching element of arm a and one end of each switching element of arm b are respectively connected. At the same time, a bypass capacitor is connected between the DC input buses one by one in the vicinity thereof, and similarly, the other end of each switching element of the arm d and the other end of each switching element of the arm e are connected one by one. By-pass capacitors are connected one by one between the DC input busbars in the vicinity thereof, and each connection point of the switching element of the arm a and the switching element of the arm b is connected to one of the AC output busbars. Each of the connection points of the switching element of No. 1 and the switching element of the arm e is connected to another one of the AC output busbars.

[0008]

With this structure, the arms a and b are
The switching elements connected in series to the arms d and e are protected by absorbing the spike voltage generated by switching by the bypass capacitors arranged in the vicinity. Since this bypass capacitor is arranged near the switching element as described above, the reactance of the wiring is small. Therefore, resonance does not occur with the bypass capacitor. Further, since the bypass capacitor is connected between the DC input buses and does not discharge, there is no power loss.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1A, switching elements (M0S FETs) A1 and A2 of the arms a and d are provided.
, A3, D1, D2, and D3 are connected at their upper ends to the DC input bus bar 1, and the switching elements B1 of the arm b and the arm e,
The lower ends of B2, B3, E1, E2, and E3 are connected to the DC input bus bar 3
Connected to. Further, each switching element A1, A2
, A3 and switching elements B1, B2, B3 are connected in series one by one, and by-pass capacitors C1, C2, C3 are connected in the vicinity of the DC input buses 1, 3 respectively.
Connected in between.

Similarly, each switching element D1, D2,
D3 and each switching element E1, E2, E3 are connected in series one by one, and bypass capacitors C4, C5, C6 are connected between the DC input buses 1 and 3 one by one in the vicinity thereof. Further, the switching elements A1, A2, A
3 and switching elements B1, B2, and B3 are connected to the AC output bus bar 5, and similarly switching element D
1, D2, D3 and switching elements E1, E2, E3
Is connected to the AC output bus bar 7.

By-pass capacitors C1, C2, C3 between the switching elements A1, A2, A3, B1, B2, B3 and the DC input buses 1, 2 of the arms a, b of FIG. 1 (a).
FIG. 1 (b) shows a mounting example in which is mounted on the printed board.

As described above, since the bypass capacitor is arranged near the switching element, the inductance of the connection wiring is small and the jump voltage due to the switching of each element is small. Moreover, since the plurality of bypass capacitors are not discharged, there is no power loss as in the snubber circuit.

[0013]

As can be understood from the above description, since the present invention has the configurations described in the claims,
Since the inductance of the wiring of the bypass capacitor arranged in the vicinity of the switching element becomes small, the jump voltage generated by the switching element becomes small, and the snubber circuit or the like becomes unnecessary. Therefore, there is no need for the power loss due to the snubber circuit and the cooling space for the mounting portion as in the conventional case.

[Brief description of drawings]

FIG. 1A is a circuit diagram of an embodiment of the present invention. (B) It is explanatory drawing of arrangement | positioning of some elements of FIG. 1 (a) attached to the printed board.

FIG. 2 is a circuit diagram of a conventional high frequency inverter.

FIG. 3A is a circuit diagram of a conventional high frequency inverter in which each arm has three FET elements. (B) It is explanatory drawing of arrangement | positioning of some elements of FIG. 3 (a) attached to the printed board.

[Explanation of symbols]

1, 3 DC bus 5, 7 AC bus A1, A2, A3, B1, B2, B3 MOS FET
Element D1, D2, D3, E1, E2, E3 MOS FET
Element C1 to C6 bypass capacitor

Claims (1)

[Claims] 1. Arms a, b, of a full bridge circuit
In a high-frequency inverter having a plurality of switching elements in d and e, one end of each switching element in arm a and arm d is connected to one of the DC input buses,
One end of each switching element of arm b and arm e is connected to another one of the DC input buses, and the other end of each switching element of arm a and one end of each switching element of arm b are respectively connected. At the same time, a bypass capacitor is connected between the DC input buses one by one in the vicinity thereof, and similarly, the other end of each switching element of the arm d and the other end of each switching element of the arm e are connected one by one. By-pass capacitors are connected one by one between the DC input busbars in the vicinity thereof, and each connection point of the switching element of the arm a and the switching element of the arm b is connected to one of the AC output busbars. The switching element of the high-frequency inverter is characterized in that each connection point of the switching element of the arm and the switching element of the arm e is connected to another one of the AC output buses. Arranging method of ring elements.