JPH07130986A - Electric-charge detection apparatus and its driving method - Google Patents

Abstract

PURPOSE:To increase the sensitivity of an electric-charge detection apparatus and to prevent a noise from being mixed with an output signal by reducing a parasitic capacity and to obtain a stable output signal by reducing a leakage current. CONSTITUTION:A P-well 3 is not depleted, it does not come into contact with an n<+> region in a stray-capacity diffused region FD100, and it does not come into contact with an n<+> region in a reset-drain region RD99. Consequently, since a P-well 102 whose concentration is lower than that of the P-well 3 comes into contact with the FD100, a P-N junction capacitance is lowered as compared with that in conventional cases. That is to say, the P-well 102 which has been depleted is sandwiched. As a result, the thickness of a depletion layer is changed due to a change in the P-well 3, its change rate becomes small as compared with that in conventional cases. In addition, regarding a phiR which is applied from a reset gate RG98, the mixture of the phiR becomes very small because the RD99 (the n<+> region) does not come into contact with a P-region such as the P-well 3 or the like and comes into contact with a P<-> region (the P-well 102).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (hereinafter referred to as C
(Hereinafter referred to as CD), the present invention relates to a charge detection device that performs charge-voltage conversion and a driving method thereof.

[0002]

2. Description of the Related Art In CCDs, it is required to detect and amplify signal charges with low noise. Typical CCD charge detection devices include a floating diffusion amplifier (Floating Diffusion Amplifier, hereinafter abbreviated as FDA) and a floating gate amplifier (Floating Gate Amplifier, hereinafter abbreviated as FGA). It was The former FDA is the most popular one, and FIG. 10 shows an overall view of a conventional CCD device using the FDA. Photons incident on the PD (photodiode) 90 are
It is converted into electric charge and stored in PD90. After a certain period of time, the signal charge is read out to the VCCD 91, and passes through the HCCD 92 to F
It is input to DA93 and detected as a voltage. Such an FDA has a problem that reset noise is generated. On the other hand, the latter FGA has a feature that an amplifier which is nondestructive and has no reset noise can be realized.

Regarding FGA, ISC SCI, Digest of Technical Papers
(1973) pp.154-155 (ISSCC Digest of Technical Pa
pers (1973) p.154-155). Also, ARCA Review 36 (September 1975), pages 566-59.
Page 3 (RCA REVIEW 36 (SEPTEMBER, 1975) p.566-593) describes FDA and FGA.

FIG. 11 is a diagram for explaining the parasitic capacitance of a conventional FGA, and shows a cross section when a signal charge Q is input under a floating gate (hereinafter abbreviated as FG) 95. Si
FG95 is formed of polysilicon with the gate oxide film 96 sandwiched on the substrate.

After forming an insulating film with SiO ₂ , a bias gate (hereinafter abbreviated as BG) 94 is formed with aluminum or tungsten. At this time, the capacitance C1 is the capacitance between the signal charge Q and FG95, the capacitance C2 is the capacitance between FG95 and BG94, the capacitance C3 is the depletion layer capacitance between the signal charge Q and the P-type substrate,

[0006]

[Outer 1]

The capacitor C5 is a MOS transistor (hereinafter, Tr
Input capacity). The MOSTr constitutes a source follower (not shown), which converts the signal voltage into a low output impedance and outputs it. That is, the FG 95 serves as both the charge detection gate and the gate of the first stage Tr. In the presence of such parasitic capacitance, when the signal charge Q is input under the FG95, the FG95 has ΔV according to (Equation 1).
Only the voltage change appears. The operating point potential of FG95 is BG
It is determined by controlling the potential of 94. The FGA described above operates by replacing the FDA 93 shown in FIG.

[0008]

[Equation 1]

[0009]

However, in the conventional charge detection device provided with the FDA described above, φH1 and φH
2 and reset pulse φR (signal applied to RG98 ... Fig. 1
(See 3) jumped into the output signal.

FIG. 12 is a waveform diagram of a conventional FDA, (a)
Is the ideal waveform, and (b) is the actual waveform. However, the actual φH1, φH2 (not shown) and φR signals have ringing or the like as shown in (b) and are mixed as noise in the output signal. Therefore, in (b), since the sampling cannot be performed accurately, the noise reduction circuit in the subsequent stage did not function sufficiently.

FIG. 13 is a cross-sectional view around the conventional FDA.
96 is a gate oxide film, 97 is an output gate OG, 98 is a reset gate RG, and 99 is a reset drain RD. The P well 102 (P region) is thinner than the P well 101 (P region) concentration and is almost depleted. The noise mixing is caused by that φH1, φH2, and φR are transmitted to the P well 101 having high resistance through the gate oxide film 96.

[0012]

[Outside 2]

In general, since the power source of RD99 and the source follower is common, φH1, φH2 and φR are RD.
It was also transmitted to the source follower power supply via 99 and mixed into the output signal.

Further, the conventional charge detection device having the FGA has a problem that the charge detection sensitivity is low. (Equation 1)
Considering from the above, the detection sensitivity improves as C1 increases and C3 decreases. However, since both C1 and C3 have their limits and the FG95 needs to be extended to the first stage Tr of the source follower, the parasitic capacitance cannot be significantly reduced. Further, in the actual FGA, the parasitic capacitance of (Equation 1) or more was added.

FIG. 14 is a plan view (a) and a sectional view (b) around the conventional FGA. Signal charges are transferred by applying φH1 and φH2 to the gate formed on the HCCD 92 shown in FIG. To be done. Signal charge is output gate OG
It is transferred below 97 and under FG95, and charge-voltage conversion is performed. The signal charge Q detected by the FG95 is applied to the reset drain RD by the reset gate RG98 as in the FDA.
Emitted to 99.

As is clear from FIG. 14, FG95 and OG9
7, RG98 is overlapping. This is HCCD9
This is because the FG95 was placed in the same way as in 2, and FG95 and OG9
The capacity of C6 is added between 7 and the capacity of C7 is newly added between FG95 and RG98. As a result, the sensitivity of FGA is FDA.
It was 40 to 50% lower than

Further, as its name implies, the FG 95 is in an electrically floating state, and if there is even a slight leak current, the potential will fluctuate. This fluctuation in potential becomes a fluctuation in the operating point of the source follower and appears as a fluctuation in the output signal. At present, it is impossible to reduce the leak current to zero with any insulating film, and there is a tendency that the leak current increases especially when the potential of FG95 increases. Also, in FIG.
In such a structure, the end portion of aluminum (BG94) is formed on the Si substrate. In other words, when the etching boundary was formed on the Si substrate, stress was applied to the vicinity of this boundary, and the phenomenon that the leak current of the FG95 increased was also observed.

In view of the above points, the present invention has an object to provide a charge detection device which has low noise, high charge detection sensitivity, and little influence of leak current, and a driving method thereof.

[0019]

The present invention is achieved by the following means in order to solve the above problems.

First, the first of the charge detection devices of the present invention is to store signal charges in a first well formed on a semiconductor substrate, a second well having a higher concentration than the first well, and a second well. It is composed of a charge-voltage converting means for converting into a signal voltage and a reset drain for discharging the signal charges accumulated in the charge-voltage converting means, and the second well is not in contact with the charge-voltage converting means and the reset drain. And

Second, a charge-voltage converting means for accumulating signal charges and converting them into a signal voltage, a reset drain for discharging the signal charges accumulated in the charge-voltage converting means, and a source for reducing the impedance of the signal voltage. It is characterized by comprising a follower, and a low-pass filter is inserted into the power source to be supplied to the source follower or a separate power source.

Thirdly, a charge transfer means composed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the rearmost part of the charge transfer means, and formed on the floating gate via an insulating film. The charge storage area of the floating gate is smaller than the charge storage area of the charge transfer means.

Fourth, the first well formed on the semiconductor substrate, the second well having a higher concentration than the first well, and the second well are formed and separated at the same time. It is characterized by comprising a third well, a bias gate formed on the third well via an insulating film, and a source follower connected to the third well.

Fifth, a charge transfer means formed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the end of the charge transfer means, and a source in which the floating gate also serves as a first stage transistor. A follower, a field oxide film separating the source follower from the charge transfer means, and a bias gate formed on the floating gate via an insulating film, wherein the bias gate and the floating gate are on the field oxide film. It is characterized by overlapping in.

Sixth, a charge transfer means composed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the rearmost part of the charge transfer means, and formed on the floating gate via an insulating film. And a reset gate which gives a discharge signal of the signal charge accumulated under the floating gate, and the floating gate does not overlap with the charge transfer means and the reset gate.

Seventh, a buried channel formed on a semiconductor substrate, a charge transfer means composed of a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. A floating gate, a source follower for lowering the impedance of the signal voltage of the floating gate, and a bias gate formed on the floating gate via an insulating film. The floating gate is formed only on the buried channel. It is characterized by being done.

Eighth, a buried channel formed on a semiconductor substrate, a charge transfer means composed of a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. Floating gate, a source follower for lowering the impedance of the signal voltage of the floating gate, and a bias gate formed under the floating gate via an insulating film, and the floating gate is formed only on the buried channel. The source follower is formed only in the transistor active region.

Ninth, a buried channel formed on the semiconductor substrate, a charge transfer means composed of a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. And a bias gate formed on the floating gate via an insulating film, and N-type impurities are implanted under the floating gate.

Next, the first method of driving the charge detection device of the present invention is to drive the bias gate with different voltages in the horizontal and vertical blanking periods and in the operation period in the charge detection device having the bias gate in each of the above means. It is characterized by

Secondly, in the charge detection device having the bias gate and the reset gate in each of the above means, the bias gate and the reset gate are driven in opposite phases.

[0031]

According to the present invention, by the charge detecting device and the driving method thereof, it is possible to reduce noise mixing in the FDA output signal,
It is possible to significantly reduce the parasitic capacitance that hinders the FGA sensitivity from being improved. Further, even if a leak current occurs, the FG potential hardly changes due to the reset operation.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the FDA in the first embodiment of the present invention.
It is a cross-sectional view of the periphery and a connection diagram of a source follower power supply.
The feature of the first embodiment is that the P well 101 shown in FIG.
Is reduced to P well 3.

[0033]

[Outside 3]

Therefore, since the P well 102 having a lower concentration than the P well 3 is in contact with the FD 100, the PN junction capacitance is lower than in the conventional case. In addition, since the depletion layer spreads between the P well 3 and the FD 100, even if the potential of the P well 3 fluctuates (noise mixes), the fluctuation of the PN junction capacitance becomes much smaller than in the conventional case. That is, since the depleted P well 102 is sandwiched between them, the P well 3
Even if the depletion layer thickness fluctuates due to the fluctuation of, the fluctuation ratio becomes smaller than before.

[0035]

[Outside 4]

Further, φH1, φH2, φ transmitted to RD99
The R noise enters the power source of the source follower 1 through the power source V _RD . Therefore, in the first embodiment, the power source V _RD of the source follower 1 is provided with a low-pass filter (hereinafter abbreviated as LPF) composed of R1 and C10. As a result,
The fluctuation of the power supply voltage is also eliminated, and the noise mixing in the output signal V _o is further reduced. The same result can be obtained even if only the source follower 1 is used as a separate power source.
By providing, the noise mixing is further reduced.

FIG. 2 shows an FG according to the second embodiment of the present invention.
It is the top view (a) of A periphery, and its BB 'sectional drawing (b). The feature of the second embodiment is that the area of the charge detection portion is smaller than that of the charge transfer portion. If the charge transfer area is L × W and the charge detection area is L ′ × W ′, then L × W> L ′ ×
W'applies. The amount of charge that can be stored under FG95 is OG
It is determined by the relationship of the OFF potentials of 97, FG95 and RG98. If OG97 and RG98 are the same as before, FG
It is possible to operate by applying a potential of 95, that is, a voltage higher than the conventional voltage to BG94. In the case of the second embodiment, since the area of the FG 95 of the charge detecting portion is reduced, C1, C2 and C3 are smaller than in the conventional case. Also, F
Since the overlapping area of G95, OG97 and RG98 is also reduced, the capacitances C6 and C7 are also reduced. If C _FG is the conventional parasitic capacitance obtained by adding C6 and C7 to the denominator of (Equation 1) and C _N is the parasitic capacitance of the second embodiment, then C _N <C _FG . The parasitic capacitance can be reduced and the charge detection sensitivity can be improved.

FIG. 3 shows an FG according to the third embodiment of the present invention.
FIG. 4 is a plan view (a) around A, a CC ′ cross-sectional view (b) and an enlarged DD ′ cross-sectional view (c) of FIG. The feature of the third embodiment is that the floating gate FG is connected to the P well 4 (P region),
The bias gate BG5 is formed of polysilicon.

[0039]

[Outside 5]

The P well 4 is manufactured at the same time as the peripheral P well 101, but they are not in contact with each other. Further, since the P well 102 (P ~ region) is almost depleted, the P well 4 is in a floating state.

Further, the shorter the distance between the bias gate BG5 and the floating gate FG (P well 4), the lower the voltage applied to the bias gate BG5 may be. Therefore, in the third embodiment, the bias gate BG5 is made of polysilicon. The bias gate is made of metal as before.
Even if it is formed of (aluminum, tungsten), there is no particular problem because the applied voltage only increases. Since the P well 4 is a P layer, it is connected to the source follower by diffusing P-type impurities (such as As) into the contact hole 7 and using aluminum wiring. As a result, the distance between the floating gate FG (P well 4) and the signal charge (in the n layer) becomes short, and C1 in (Equation 1) increases. Therefore, the parasitic capacitance can be reduced and the charge detection sensitivity can be improved.

FIG. 4 shows an FG according to the fourth embodiment of the present invention.
It is the top view (a) of A periphery, and its EE 'sectional drawing (b). The feature of the fourth embodiment resides in that BG8 and FG95 are overlapped on the field oxide film 9. Reference numeral 6 denotes the first-stage Tr of the source follower, which is the same as the source follower 1 shown in the first embodiment. The field oxide film 9 is a thick film of SiO ₂ formed by thermal oxidation. As described in the problem, when the etching end portion of aluminum is formed on the Si substrate, the leak current of FG95 increases. In the fifth embodiment, since the aluminum etching end portion is formed on the field oxide film 9, the leak current of FG95 is reduced. At this time, if the overlap area is the same as the conventional one, FG
The parasitic capacitance and potential of 95 do not change.

FIG. 5 shows an FG according to the fifth embodiment of the present invention.
It is the top view (a) of A periphery, and its FF 'sectional drawing (b). The fifth embodiment is characterized in that the FG10 and the OG97 and RG98 are not overlapped with each other, and the gaps D1 and D2 are provided, respectively, and HCC to which φH1 and φH2 are applied.
The gates of section D are at the point where they overlap. In the FGA operating state of the fifth embodiment, the potential of FG10 is set higher than the OFF potential of OG97 and RG98 by controlling the BG94 potential. Since a fringing electric field is applied to the gaps D1 and D2, this portion has an intermediate potential between FG10, OG97 and RG98. Although the charge transfer efficiency is lowered by providing the gaps D1 and D2, it is 0.1% or less. Also, by raising the potential of BG94,
The decrease in charge transfer efficiency is almost eliminated. However, in the HCCD unit, an increase in applied voltage causes a significant increase in power consumption. Even if the number of transfer stages is decreased by 0.1%, it becomes unusable if the number of transfer stages is 500 or more. Therefore, the gap is set only for FG10, OG97, and RG98. As a result, the parasitic capacitance can be reduced and the charge detection sensitivity can be improved.

FIG. 6 shows an FG according to the sixth embodiment of the present invention.
It is the top view (a) of A periphery, and its GG 'sectional drawing (b). The feature of the sixth embodiment is that the FG 20 is formed only in the buried channel (region where the signal charges are transferred). 6
Is the first stage Tr of the source follower and is the same as the source follower 1 shown in the first embodiment. The FG20 is formed only on the n region to which the signal charge is transferred, and
By providing a contact hole 21 on the top, it is in contact with aluminum. The gate 23 is the gate portion of the first stage Tr, and has the same potential as the FG 20 through the contact hole 22. Further, BG8 overlaps with the gate 23 on the field oxide film 9 and gives an operating potential to the FG20 and the gate 23.

[0045]

[Outside 6]

FIG. 7 shows an FG according to the seventh embodiment of the present invention.
It is the top view (a) of A periphery, and its HH 'sectional drawing (b). The feature of the seventh embodiment is that BG27 is made of polysilicon,
The FG20 is overlapped on the field oxide film 9.

[0047]

[Outside 7]

The FG 20, the gate 25, and the BG 27 are made of polysilicon, and the BG 27 is arranged on the field oxide film 9. This also reduces most of the capacitance C4 of the wiring portion shown in the conventional problem. As a result, the parasitic capacitance is significantly reduced and the charge detection sensitivity is also improved.

FIG. 8 shows an FG according to the eighth embodiment of the present invention.
It is each sectional drawing (a), (b), (c) of the A periphery. The feature of the eighth embodiment is that N-type impurities are injected again into the lower portion of FG10,
The point is that the storage unit 11 is provided.

[0050]

[Outside 8]

The potential of the storage section 11 becomes deeper than before, and the transferred signal charges are stored here. Further, since the potential of the storage section 11 is deep, the charge transfer efficiency does not decrease even if the FG10 potential is set lower than in the conventional case. In addition, the reduction of the FG10 potential also makes it possible to reduce the leakage current.

FIG. 8B shows an FGA provided with a P well 3 similar to that of the first embodiment. Similarly, FIG. 8 (c) shows a structure in which the P well 3 is provided in the eighth embodiment, and
Since 11 is not in contact with the P well 3, the parasitic capacitance is smaller than that in (a). For the same reason as in the first embodiment, φH
Mixing of 1, φH2 and φR into the output signal is reduced. In this embodiment, the case where the storage unit 11 is provided in the fifth embodiment has been described, but the floating gate potential can be lowered even if the floating gate and other gates overlap as in the conventional case. Is.

FIG. 9 shows drive waveforms of the FGA of the present invention.
This is a driving method applied to the charge detection devices of Examples 1 to 8 of the present invention. The drive waveform of the bias gate BG is φBG
And the drive waveform during one scanning period corresponds to FIG. Example 7 (FIG. 7) will be described as an example. Φ27 to BG27
By applying G, the potential of FG20 is also set to a value proportional to φBG. During the operation period, the signal charge flows under the FG20 and the signal charge is detected, so that the BG27 is set to the positive constant potential V1. The blanking period is a horizontal and vertical blanking period, and is a period in which signal charges are not transferred below FG20. Therefore, the potential of FG20 in this period may be any value.

The leakage current tends to increase as the FG20 potential increases. Therefore, in this driving method, the leak current is prevented by driving the BG27 with different voltages in the blanking period and the operation period. In particular,
BG27 during the blanking period is set to the negative potential V2. As described above, not only the leak current is reduced, but also the result is that the charge moved by the leak current during the operation period is almost reset (the FG20 potential does not change). As a result, a charge detection device having a stable output signal can be obtained.

FIG. 9B shows the case where φBG is modulated for each signal charge, and shows the relationship between φH1, φR, and φBG. In FIG. 9B, the leakage current is reduced by modulating φBG during the operation period. Since the signal charge is not below FG20 when φR is in the ON state, φBG does not need to be V1 shown in FIG. 9A. Therefore, φR
By driving φBG and φBG in opposite phases, the H period of BG27 is shortened. In other words, FG20 during the period when there is no output signal
It is intended to reduce the leak current by lowering the potential. In this case, it is not always necessary to apply a negative voltage to φBG, and a voltage lower than V1 may be used. Furthermore, F
If the potential of G20 is higher than that of OG97, the signal charge can be driven without backflow.

Further, by modulating φBG, the discharge of the signal charge to RD99 can be accelerated. Similarly,
When a negative voltage is applied to φBG in (b), the reverse flow of signal charge is considered, so OG97 and φ
It is also necessary to set a negative voltage for H1. As a result, the leak current is reduced, and even if the leak current is present, its influence is almost eliminated, so that a charge detection device having a stable output signal can be obtained. Needless to say, driving may be performed by combining FIGS. 9A and 9B.

[0057]

As described above, according to the present invention, noise mixing into the FDA output signal is reduced with a simple structure, so that the noise reduction function sufficiently functions and S /
It is possible to improve N. Further, since the parasitic capacitance included in the FGA can be effectively reduced, a highly sensitive charge detection device can be realized.

Furthermore, since the FG potential of the FGA hardly changes due to the leak current, the operating point of the source follower is almost fixed, and a stable output signal can be obtained. As described above, the charge detection device having a high sensitivity and a stable output signal and the driving method thereof can be realized with a simple structure, which is extremely effective in practice.

[Brief description of drawings]

FIG. 1 is a cross-sectional view around an FDA and a connection diagram of a source follower power supply in a first embodiment of the present invention.

FIG. 2 is a plan view (a) around an FGA and a BB ′ sectional view (b) thereof in a second embodiment of the present invention.

FIG. 3 is a plan view (a) around the FGA and a sectional view taken along the line CC ′ of FIG. 3B and an enlarged view D− of the FGA according to the third embodiment of the present invention.
It is a D'sectional view (c).

FIG. 4 is a plan view (a) around an FGA and a cross-sectional view taken along the line EE ′ (b) of the fourth embodiment of the present invention.

FIG. 5 is a plan view (a) around an FGA and a cross-sectional view taken along the line FF ′ (b) of the fifth embodiment of the present invention.

FIG. 6 is a plan view (a) around an FGA and a GG ′ cross-sectional view (b) thereof in a sixth embodiment of the present invention.

FIG. 7 is a plan view (a) around the FGA and a cross-sectional view taken along the line HH ′ (b) of the seventh embodiment of the present invention.

FIG. 8 is sectional views (a), (b) and (c) around an FGA according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing drive waveforms of the FGA of the present invention.

FIG. 10 is an overall view of a conventional CCD device using FDA.

FIG. 11 is a diagram illustrating a parasitic capacitance of a conventional FGA.

FIG. 12 is a waveform diagram of a conventional FDA.

FIG. 13 is a cross-sectional view around a conventional FDA.

FIG. 14 is a plan view and a cross-sectional view of a conventional FGA and its periphery.

[Explanation of symbols]

1 ... Source follower, 3, 4, 101, 102 ... P-well,
5, 8, 27, 94 ... Bias gate (BG), 6 ... First stage Tr, 7, 21, 22, 26 ... Contact hole, 9 ... Field oxide film, 10, 20, 95 ... Floating gate (F
G), 11 ... Accumulation part, 23, 25 ... Gate, 96 ... Gate oxide film, 97 ... Output gate (OG), 98 ... Reset gate (RG), 99 ... Reset drain (RD), 10
0 ... Floating capacitance diffusion region (FD).

Claims (18)

[Claims] 1. A first well formed on a semiconductor substrate, a second well having a higher concentration than the first well, and charge-voltage conversion means for accumulating signal charges and converting them into signal voltages. A charge detecting device comprising a reset drain for discharging signal charges accumulated in the charge-voltage converting means, wherein the second well is not in contact with the charge-voltage converting means and the reset drain. 2. A charge-voltage converter that stores signal charges and converts them into a signal voltage, a reset drain that discharges the signal charges stored in the charge-voltage converter, and a source follower that lowers the impedance of the signal voltage. In addition, a low-pass filter is inserted in the power supply supplied to the source follower, or a separate power supply is used. 3. The charge detection device according to claim 1, wherein a floating diffusion amplifier is used as the charge-voltage conversion means. 4. The charge detecting device according to claim 1, wherein a floating gate amplifier is used as the charge-voltage converting means. 5. A charge transfer means composed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the rearmost part of the charge transfer means, and formed on the floating gate via an insulating film. A charge detection device comprising a bias gate, wherein the charge storage area of the floating gate is smaller than the charge storage area of the charge transfer means. 6. A first well formed on a semiconductor substrate, a second well having a concentration higher than that of the first well, and a third well formed and separated simultaneously with the second well. Charge well, a bias gate formed on the third well via an insulating film, and a source follower connected to the third well. 7. The charge detection device according to claim 6, wherein the bias gate is formed of metal aluminum, tungsten, or polysilicon. 8. A charge transfer means composed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the end of the charge transfer means, and a source follower in which the floating gate also serves as a first stage transistor. A field oxide film separating the source follower from the charge transfer means, and a bias gate formed on the floating gate via an insulating film. The bias gate and the floating gate are overlaid on the field oxide film. A charge detection device characterized by being wrapped. 9. A charge transfer means composed of a plurality of gates formed on a semiconductor substrate, a floating gate formed at the rearmost part of the charge transfer means, and formed on the floating gate via an insulating film. A charge detection device comprising: a bias gate; and a reset gate that gives a discharge signal of a signal charge accumulated under the floating gate, and the floating gate does not overlap with the charge transfer means and the reset gate. 10. A buried channel formed on a semiconductor substrate, a charge transfer means including a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. A floating gate, a source follower for lowering the impedance of the signal voltage of the floating gate, and a bias gate formed on the floating gate via an insulating film. The floating gate is formed only on the buried channel. A charge detection device characterized by the above. 11. A buried channel formed on a semiconductor substrate, a charge transfer means composed of a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. A floating gate, a source follower for lowering the impedance of the signal voltage of the floating gate, and a bias gate formed under the floating gate via an insulating film, the floating gate being formed only on the buried channel, The charge detector according to claim 1, wherein the source follower is formed only in a transistor active region. 12. The bias gate is disposed on the field oxide film.
Or the electric charge detection device described in 11. 13. The contact hole for connection is provided on the floating gate.
Or the electric charge detection device described in 11. 14. The charge detecting device according to claim 11, wherein the bias gate is formed of polysilicon. 15. The charge detection device according to claim 11, wherein a contact hole for connection is provided on the transistor gate of the source follower. 16. A buried channel formed on a semiconductor substrate, a charge transfer means comprising a plurality of gates formed on the buried channel via an insulating film, and a charge transfer means formed at the rearmost part of the charge transfer means. A charge detection device comprising a floating gate and a bias gate formed on the floating gate via an insulating film, and implanting an N-type impurity under the floating gate. 17. The method according to claim 1, further comprising a bias gate.
The charge detection device as described above, wherein the bias gate is driven with different voltages in the horizontal and vertical blanking periods and in the operation period. 18. The charge detection device according to claim 1, further comprising a bias gate and a reset gate, wherein the bias gate and the reset gate are driven in opposite phases.