JPH07130707A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To prevent damage to a diffusion layer, by stopping etching when a luminous intensity of carbon monoxide, which is generated by etching reaction, begins rising again after the luminous intensity increases to an equilibrium state and decreases abruptly. CONSTITUTION:An SiN region layer 28 is formed on a gate electrode 27. An impurity is implanted with a mask of the gate electrode 27 to form a first impurity diffusion layer 30A on both sides of the gate electrode 27, and a silicon oxide film 29 is all etched. During the etching, a luminous intensity of carbon monoxide generated in etching reaction is detected, and the etching is stopped when the intensity begins rising again after the intensity increases to an equilibrium state and decreases abruptly. A silicon oxide film 29 remaining at the side of the gate electrode 27 is formed as a side wall 31. In this way, the end- point of etching can be detected promptly and surely, and damage to the diffusion layer can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, an LDD (Lightly Doped Drain).
) Structure MOS transistor, it relates to the improvement of the formation process of the side wall formed on the side of the gate electrode.

[0002]

2. Description of the Related Art First, as shown in FIG. 7, a gate insulating film (2), a polysilicon layer (3), a tungsten silicide layer [hereinafter referred to as a WSix layer] on a semiconductor substrate (1) made of p-type silicon or the like. ] (4) is sequentially formed, and a resist film (5) is selectively formed. Next, a resist film (5)
The polysilicon layer (3) and the WSix layer (4) are removed by etching using the mask as a mask, and the polysilicon layer (6A) and WSix layer (6B) remaining under the resist film (5) are replaced with the gate electrode (6). ) (FIG. 8).

Next, P ⁺ ions are implanted by using the resist film (5) and the gate electrode (6) as a mask to form an n ⁻ type impurity diffusion layer (7A), and then the resist film (5).
Then, a SiO ₂ film (8) having a film thickness of about 4000 Å is formed on the entire surface by the CVD method (FIG. 9). Next, as shown in FIG. 10, the entire surface of the SiO ₂ film (8) is dry-etched using a narrow gap RIE etcher (not shown) using CF ₄ , CHF ₃ , Ar gas or the like to form the SiO ₂ film ( 8) and the gate insulating film (2) are removed, and the SiO ₂ film (8) remaining on the side of the gate electrode (6) is used as a side wall (9). In this etching step, the n ⁻ -type impurity diffusion layer (7A) and the WSix layer (4) constituting the gate electrode (6) are finally exposed, but they are not exposed at the same time, and the WSix layer (4) is exposed. Is confirmed to be exposed first.

In this etching process, even after the WSix layer (4) is exposed, the SiO ₂ on the n ^-- type impurity diffusion layer (7A) is removed.
Etching is continued until the film is removed, and it is difficult to detect the end point of the film. Therefore, the n ⁻ -type impurity diffusion layer (7A) is overetched, and the damage layer (10) is formed by plasma during etching. Will end up. The end point of the etching process is detected by detecting the CO (carbon monoxide) emission intensity. That is, by etching, C (carbon) contained in the etching gas such as CF ₄ or CHF ₃ and O (oxygen) contained in the SiO ₂ film (8) are combined to generate CO. The CO emission intensity is actually detected by detecting the intensity of the CO emission spectrum. As shown in FIG. 13, the emission spectrum intensity of CO starts to decrease when the SiO ₂ film is etched and the underlayer starts to be exposed after reaching an equilibrium state at a certain level, which gradually increases, and reaches a certain level. Eventually it will be zero.

Therefore, as shown in FIG. 13, when the emission spectrum reaches a certain level or lower, it is considered that the etching is completed, and the etching is completed. At this time
Since the SiO ₂ film (8) has been completely removed in all regions and over-etching has been performed, as shown in FIG. 10, the n ⁻ -type impurity diffusion layer (on the semiconductor substrate (1) made of silicon ( 7A) and the WSix layer (4) are exposed and damaged by etching plasma, and a damage layer (10) is formed on each of them.

Next, as shown in FIG. 11, after the damage layer (10) is removed by dry etching, the entire surface is re-oxidized to form a protective film (12) for the subsequent ion implantation process. In this oxidation step, the upper layer of the WSix layer (6B) exposed from the side wall (9) is oxidized and becomes a tungsten oxide layer [hereinafter referred to as Wox layer] (11). next,
As shown in FIG. 12, using the gate electrode (6) and the sidewalls (9) as a mask, As ⁺ ions are implanted to n ⁺
A type impurity diffusion layer (7B) is formed, and the n ⁻ type impurity diffusion layer (7A) and the n ⁺ type impurity diffusion layer (7B) are used as the source / drain region layer (7).

[0007]

However, according to the above-mentioned conventional method, since the etching is completed based on the CO emission spectrum intensity, the etching is completed after the SiO ₂ film is completely removed. . Therefore, etching is actually performed more than necessary, and n ⁻
The type impurity diffusion layer (7A) is exposed and a damage layer (10) is formed by plasma, and it is not easy to remove it. Furthermore, the damage layer (10) is also formed on the upper layer of the WSix layer (6B) by the plasma, so that the insulating Wox layer (1) is formed by oxidation during the subsequent formation of the protective film.
Since 1) will be formed, the gate electrode (6) is correspondingly formed.
However, there is a problem that the number of conductive layers decreases and the gate resistance [Rs] increases.

[0008]

The present invention has been made in view of the above conventional drawbacks. A film is formed on a semiconductor substrate, a SiN film is formed on the film, and the film and the SiN film are patterned. , A silicon oxide film is formed on the entire surface, the entire surface of the silicon oxide film is dry-etched, the emission intensity of carbon monoxide generated by the etching reaction is detected, and the emission intensity of carbon monoxide increases to reach an equilibrium state. After reaching the level, it drops sharply, and when it rises again, the etching is terminated and the upper surface of the patterned SiN film is exposed.
In the DD-type MOS transistor, a SiN region layer (28) is formed on the gate electrode (27), impurities are implanted using the gate electrode (27) as a mask, and the first electrode is formed on both sides of the gate electrode (27). After forming the impurity diffusion layer (30A), a silicon oxide film (29) is formed, the silicon oxide film (29) is entirely etched, and the emission intensity of carbon monoxide generated by the etching reaction is detected. When the emission intensity of carbon oxide rises and reaches an equilibrium state, it drops sharply, and when it begins to rise again, etching is terminated and the silicon oxide film (29) remaining on the side of the gate electrode (27) is removed from the side. Use of the wall (31) reduces damage to the semiconductor substrate during the etching process of the silicon oxide film (29) and prevents the gate resistance from increasing. The present invention provides a method for manufacturing a semiconductor device that enables the above.

[0009]

[Operation] According to the method for manufacturing a semiconductor device of the present invention, a film is formed on a semiconductor substrate, a SiN film is formed on the film, the film and the SiN film are patterned, and a silicon oxide film is formed on the entire surface. Formed and dry-etched the entire surface of the silicon oxide film to detect the emission intensity of carbon monoxide generated by the etching reaction. The emission intensity of carbon monoxide rises, reaches an equilibrium state, and then drops rapidly. Then, when it rises again, etching is completed, and the upper surface of the patterned SiN film is exposed. For example, in a MOS transistor of LDD structure, a SiN region layer (28) is formed on the gate electrode (27). Then, impurities are implanted using the gate electrode (27) as a mask to form a first impurity diffusion layer (30A) on both sides of the gate electrode (27), and then a silicon oxide film (29) is formed. The entire surface of the oxide film (29) is etched, the emission intensity of carbon monoxide generated by the etching reaction is detected, and the emission intensity of the carbon monoxide rises to reach an equilibrium state and then sharply falls, and again. Etching is completed at the point when the gate electrode (2
The silicon oxide film (29) remaining on the side of (7) is used as the side wall (31).

Therefore, since the SiN region layer (28) is formed on the gate electrode (27), when the SiN region layer (28) is exposed by etching, the emission intensity of carbon monoxide in the atmosphere becomes abrupt. Exhibit a decline. This allows
When the carbon monoxide issuance intensity drops sharply and then begins to rise again, sidewalls are virtually formed,
Since it is no longer necessary to continue etching, by ending etching at this point, compared to the conventional method in which etching was continued until all SiO ₂ films were removed,
The end point of etching can be detected faster and more reliably than ever before.

Therefore, the first impurity diffusion layer (30A) can be etched so as not to be exposed.
It is possible to significantly reduce the damage due to the plasma entering the first impurity diffusion layer (30A). At the same time, the upper layer of the gate electrode (27) is protected from damage by the SiN region layer (28), and the SiN region layer (28) acts as an antioxidant film for the gate electrode (27). It is possible to suppress the increase in the gate resistance caused by the oxidation of the WSix layer.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. The method of manufacturing a semiconductor device according to the present embodiment is an LDD (Lightly Do).
This is a method for manufacturing a MOS transistor having a ped drain structure. First, as shown in FIG. 1, for example, on a semiconductor substrate (21) made of p-type silicon, a gate insulating film (22) having a film thickness of 200 Å and a polysilicon layer (2
3), a WSix layer (24) having a film thickness of 1000 to 1500Å is sequentially formed, and a 200 to 300Å SiN film (2) is formed thereon by a low pressure CVD method.
5) is formed, a photoresist of about 1 μm is applied thereon, patterning is performed in a desired pattern, and then a resist film (26) is selectively formed in a region where a gate electrode is formed.

Next, as shown in FIG. 2, a resist film (2
Using 6) as a mask, SiN film (25), WSix layer (2
4), the polysilicon layer (23) is removed by etching, and the polysilicon layer (27A) and WSix layer (27B) remaining under the resist film (26) are used as the gate electrode (27) at the same time as the SiN region layer. (28) the gate electrode (2
7) Form on top.

Then, with the resist film (26) and the gate electrode (27) used as masks, P ⁺ [phosphorus ion] is dosed at 3
After ion implantation under conditions of × 10 ¹³ cm ^-2 and accelerating voltage of 40 keV to form an n ^- type impurity diffusion layer (30A),
The resist film (26) is removed, and a film thickness is formed on the entire surface by the CVD method.
A SiO ₂ film (29) of 3000 Å to 4000 Å is formed (FIG. 3).

Next, the entire surface is dry-etched by using a narrow gap RIE etcher (not shown) to remove the SiO ₂ film (8) and the gate insulating film (22) and remain on the sides of the gate electrode (27). The SiO ₂ film (29) is used as the side wall (31) (FIG. 4). At this time, some damage (30C) enters the n ⁻ type impurity diffusion layer (30A).

The etching conditions are, for example, CF ₄ , CHF ₃ , and Ar of 50 sccm and ₃₀ scc, respectively.
Introduce m and 800sccm into the etching chamber, set the pressure of the atmosphere to 1.3 Torr, and set the electrode interval to 0.8.
Etching is performed with a discharge power of 200 cm between the electrodes. In this etching process, the n ⁻ -type impurity diffusion layer (3
0A) on the gate electrode (27) rather than the SiO ₂ film (29)
SiO ₂ film (29) on the SiN region layer (28) formed on it
Has been confirmed to etch faster.

The end point of the etching process is detected by CO
(Carbon monoxide) The emission intensity is detected. That is, by etching, C (carbon) contained in the etching gas such as CF ₄ or CHF ₃ and O (oxygen) contained in the SiO ₂ film (8) are combined to generate CO. This C
The O emission intensity is actually detected by detecting the intensity of the CO emission spectrum. As shown in FIG. 6, the emission spectrum intensity of CO reaches an equilibrium state at a certain level, which gradually increases, maintains a certain intensity, then sharply falls, rises again, and decreases again.

That is, as the etching progresses, CO
The emission intensity changes as shown below. 1) Initially [range from start of etching to point A in FIG. 6] CHF ₃ or CF _{4 as} etching gas with etching
C (carbon) contained in the SiO ₂ film reacts with O (oxygen) contained in the SiO ₂ film to generate CO (carbon monoxide). The emission spectrum intensity of CO (hereinafter referred to as CO emission intensity) increases with the progress of etching, and then reaches an equilibrium state and becomes constant.

2) Range from point A to point B As described above, Si formed on the gate electrode (27) rather than the SiO ₂ film (29) on the n ⁻ type impurity diffusion layer (30A).
When the SiO ₂ film (29) on the N 2 region layer (28) is etched faster and the SiN region layer (28) is exposed, the total area of the SiO ₂ film that contributes to the CO production reaction decreases, and SiN
Due to the action of N (nitrogen) supplied from the region layer (28), the amount of CO produced is drastically reduced, and thus the CO emission intensity is drastically reduced. During this etching, SiN
Since the area layer (28) is also etched at the same time, C
After the amount of O produced decreased sharply, the SiN region layer (2
The supply amount of N supplied from 8) decreases, and the production amount of CO also starts to increase accordingly.

3) Area after point B When the SiN region layer (28) is etched and completely removed in this manner, N is no longer supplied from the SiN region layer (28), and the SiO ₂ film is reduced as in the conventional case. At the same time, the production of CO starts to decrease again, and eventually the SiO ₂ film is completely removed, so that the CO emission intensity approaches 0.

In such a process, the CO emission intensity changes with the progress of etching. In order to actually finish the etching, the SiN region layer (28) may be left in the range from point A to point B in FIG. 6, which is ideally the derivative of the graph in FIG. That is, it is desirable to detect the change rate of the emission intensity with time (hereinafter referred to as a differential coefficient) at any time and terminate the etching when the differential coefficient is inverted from negative to positive. The reason is that, at this time, the SiN region layer (28) is exposed and still remains. The reason why it is desirable that the SiN region layer (28) remains at this time will be described later.

Then, as shown in FIG. 5, damage (3
0C) is removed by dry etching, and then the entire surface is oxidized again to form a protective film (32) for ion implantation. In this dry etching process, since the damage in the diffusion layer is small, the etching for removing the damage can be light and easy. Further, in this embodiment, the SiN region layer (2) is formed on the surface of the WSix layer (27B).
If 8) remains, this is the WSix layer (27B).
Since the upper layer of the WSix layer (27B) exposed from the sidewall (31) is not oxidized unlike the conventional case, it is possible to prevent the upper layer of the gate electrode from being oxidized and increasing the gate resistance. Therefore, it is desirable to finish the etching so that the SiN region layer (28) remains.

Next, as shown in FIG. 12, the gate electrode (27) and the side wall (31) are used as a mask to form A.
S ⁺ [arsenic] ions are ion-implanted under the conditions of a dose amount of 5 × 10 ¹⁵ cm ^-2 and an acceleration voltage of 50 keV to form an n ⁺ -type impurity diffusion layer (30B), and an n ⁻ -type impurity diffusion layer (30A).
And the n ⁺ -type impurity diffusion layer (30B) are used as the source / drain region layer (30).

As described above, according to the method of manufacturing the semiconductor device of the embodiment of the present invention, the gate electrode (27)
A SiN region layer (28) is formed on the silicon oxide film (2)
When the entire surface of 9) is etched, the emission spectrum intensity of CO produced by the etching reaction is detected to
When the emission intensity rises, reaches an equilibrium state, then drops sharply, and begins to rise again, that is, from point A to point B in FIG.
Etching is completed within the range of points.

This is because the SiN region layer (28) is formed on the gate electrode (27), so that when the SiN region layer (28) is exposed by etching, the CO emission intensity in the atmosphere shows a sharp decrease. . As a result, the SiN region layer (28) is exposed and the sidewalls (31) are practically formed at the time when the CO emission intensity sharply decreases and then rises again, and it is not necessary to continue etching. By ending the etching at this point, it becomes possible to detect the end point of the etching faster and more reliably than in the conventional case where the etching is continued until all the SiO ₂ film is removed. .

Therefore, since it is possible to perform etching so that the n ^-- type impurity diffusion layer (30A) is not exposed,
It is possible to greatly reduce the damage due to the plasma entering the n ⁻ type impurity diffusion layer (30A). At the same time, since the SiN region layer (28) can be left on the upper layer of the gate electrode (27), the SiN region layer (28) acts as an anti-oxidation film for the gate electrode (27). It becomes possible to suppress the increase in the gate resistance caused by the oxidation of the upper WSix layer.

[0027]

As described above, according to the method for manufacturing a semiconductor device of the present invention, for example, a MOS having an LDD structure is used.
Type transistor, SiN on the gate electrode (27)
After forming the region layer (28), implanting impurities using the gate electrode (27) as a mask, and forming the first impurity diffusion layers (30A) on both sides of the gate electrode (27), the silicon oxide film ( 29) is formed, the silicon oxide film (29) is entirely etched, and the silicon oxide film (29) remaining on the side of the gate electrode (27) is used as a side wall (31). During etching, the emission intensity of carbon monoxide generated by the etching reaction is detected, and the emission intensity of the carbon monoxide rises, reaches an equilibrium state, then drops sharply, and begins to rise again. Since it has been completed, it is possible to significantly reduce the damage of the diffusion layer, and at the same time, the WSix layer above the conventional gate electrode is oxidized during the subsequent protective film formation. Therefore, it is possible to suppress the increase in the gate resistance that has occurred.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 6 is a graph illustrating a method for manufacturing a semiconductor device according to an example of the present invention.

FIG. 7 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 8 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 9 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 10 is a fourth cross-sectional view explaining the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 13 is a graph illustrating a method for manufacturing a semiconductor device according to a conventional example.

[Explanation of symbols]

(21) Semiconductor substrate (22) Gate insulating film (23) Polysilicon layer (24) WSix layer (25) SiN film (26) Resist film (27) Gate electrode (28) SiN region layer (29) Silicon oxide film ( 30) Source / drain region layer (30A) n ⁻ type impurity diffusion layer (30B) n ⁺ type impurity diffusion layer (30C) Damage (31) Side wall (32) Protective film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 21/336 7514-4M H01L 29/78 301 L

Claims (2)

[Claims] 1. A film is formed on a semiconductor substrate, and Si is formed on the film.
Forming an N film and patterning the film and SiN film, forming a silicon oxide film on the entire surface, dry etching the entire surface of the silicon oxide film, and emitting carbon monoxide generated by an etching reaction. Intensity is detected, the emission intensity of the carbon monoxide rises, reaches an equilibrium state, then drops sharply, and when it rises again, etching is terminated and the upper surface of the patterned SiN film is exposed. A method of manufacturing a semiconductor device, comprising: 2. A resist film (26) after a gate insulating film (22), a polysilicon layer (23), a tungsten silicide layer (24) and a SiN film (25) are sequentially formed on a semiconductor substrate (21). Selectively forming, and using the resist film (26) as a mask, the polysilicon layer (23) and the tungsten silicide layer (24)
And the polysilicon region layer (27) remaining under the resist film (26) by etching the SiN film (25).
A) and the tungsten silicide region layer (27B) are used as the gate electrode (27), and at the same time, a SiN region layer (28) is formed on the gate electrode (27), and impurities are formed by using the gate electrode (27) as a mask. To form a first impurity diffusion layer (30A) on both sides of the gate electrode (27).
9), and the silicon oxide film (29) is entirely etched, and the emission intensity of carbon monoxide generated by the etching reaction is detected to increase the emission intensity of carbon monoxide to reach an equilibrium state. When the silicon oxide film (29) which has reached the side of the gate electrode (27) is turned into a sidewall (31), the etching is completed at the time when the silicon oxide film (29) rapidly descends and then rises again. The gate electrode (27) and the side wall (3
1) is used as a mask to form a second impurity diffusion layer (30B), which is used as a source / drain region layer (30) together with the first impurity diffusion layer (30A). Manufacturing method of semiconductor device.