JPH07128686A - Liquid crystal display device and its production - Google Patents

Abstract

PURPOSE:To suppress the electric resistance of scanning lines and gate electrodes increased at the time of forming interlayer insulating films to a lower level and to obtain high display quality by subjecting the interlayer insulating film layers of thin-film transistors (TFTs) formed with address wiring to a heat treatment in a temp. range above the distortion point and below the m. p. after film formation by utilizing silicon oxidized films contg. phosphorus or boron or both. CONSTITUTION:A switching element is a TFT having three layers; an active layer 102 consisting of polycyrstalline silicon, a gate insulating layer 103 and a gate electrode 104 connected on a scanning line on a substrate 101 and the interlayer insulating film layer 108 formed to cover these three layers. The gate electrode 1 04 and the scanning line are the gate electrode 104 and scanning line formed of a high melting metal or high melting metal silicide or the laminated layers of the high melting silicide and polycrystalline silicon. The interlayer insulating film 108 is an interlayer insulating film of a single layer or the laminated structure contg. at least one layer of the layer formed by using the silicon oxidized film contg. phosphorus or boron or the phosphorus and the boron or the laminated structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display which has a thin film transistor as a switching element and which suppresses the electric resistance of its gate electrode and scanning line to a low level to realize high display quality. The present invention relates to a device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have the great advantages of thinness, light weight, and low power consumption. Therefore, display devices for OA equipment such as liquid crystal televisions, panel televisions, Japanese word processors and desktop personal computers. Is actively used as.
In addition, application to small LCDs such as projection and reflection type projection displays and viewfinders with a diagonal of 1 inch or less is being actively researched and developed.

A polycrystalline silicon thin film transistor using a polycrystalline silicon film as an active layer (hereinafter, abbreviated as p-Si TFT) for the purpose of improving display performance such as higher definition and larger screen of such a liquid crystal display device. ) Is actively developing a liquid crystal display device.

A conventional thin film transistor using a p-Si TFT as an active layer is a switching element for switching a voltage application to a pixel portion of a liquid crystal display device, or a scanning pulse or a video signal voltage for scanning the switching element. It is expected to be applied as a thin film transistor circuit element that forms a liquid crystal drive circuit that is applied via lines and signal lines.

By the way, in a switching element array substrate used in an active matrix type liquid crystal display device, a gate electrode of a thin film transistor formed on a transparent insulating substrate and an electrical short circuit between a scanning line and a signal line connected thereto. In order to prevent (short circuit), the scanning line and the signal line are provided in different layers, and an interlayer insulating film is provided to insulate the scanning line and the signal line from each other. As a material for the interlayer insulating film, a film having a high insulating property and a good light transmittance such as SiO _x (silicon oxide film) or SiN _x (silicon nitride film) is generally used.

On the other hand, in an active matrix type liquid crystal display device, when a video signal voltage is written in a liquid crystal cell formed of a pixel electrode, a liquid crystal layer and a counter electrode, the voltage is connected to the pixel electrode of the liquid crystal cell. If the response characteristic of the switching element that performs the switching of the applied voltage (high-speed response characteristic of the switching operation) is poor, the video signal voltage cannot be written accurately to the liquid crystal cell, and good display cannot be performed. Here, the response characteristic of the switching element is rate-controlled by the pulse rise time of the gate voltage and the video signal writing time.

The pulse rise time of the gate voltage is determined by the wiring resistance and the wiring capacitance of the scanning line (and the gate electrode). Therefore, since the scanning line is required to have low resistance, p-Si doped with impurities, refractory metal or polycide is generally used as the material.

[0008]

However, the CVD method is applied on the scanning line and the gate electrode formed of the refractory metal or refractory metal silicide or the lamination of refractory metal silicide and polycrystalline silicon as described above. When the silicon oxide film or the silicon nitride film is formed to form the interlayer insulating film, the resistance value of the scanning line and the gate electrode covered under the interlayer insulating film increases.

As an example, tungsten silicide and p
A case where the scanning line and the gate electrode are formed with a laminated structure of -Si (polysilicon) will be described.

The resistance value of the scanning line and the gate electrode at the stage of forming the laminated structure of tungsten silicide and p-Si is about 20 to 30 Ω / □. Then heat-treat 10
Reduce the resistance to less than Ω / □.

However, after that, a silicon oxide film is formed as an interlayer insulating film so as to cover the scanning lines and the gate electrodes.
Low temperature atmospheric pressure CVD method of about 450 ℃ and depressurized CV of about 800 ℃
When the film is formed by the D method, after the interlayer insulating film is formed, the electric resistance value of the scanning line and the gate electrode covered therewith is 15
Ω / □ or more. As a result, there is a problem in that the response characteristics of the switching element connected to the scanning line and the gate electrode are deteriorated, and good display as a liquid crystal display device is hindered.

The present invention has been made to solve such a problem, and suppresses the increased electric resistance of the scanning line and the gate electrode when the interlayer insulating film is formed, and realizes high display quality. Another object of the present invention is to provide the liquid crystal display device.

[0013]

In order to solve the above-mentioned problems, a liquid crystal display device of the present invention comprises a plurality of scanning lines, a plurality of signal lines arranged so as to intersect the scanning lines, and A pixel electrode arranged for each grid of a matrix formed by the scanning lines and the signal lines, and a liquid crystal drive voltage applied to the pixel electrodes connected to the pixel electrodes, the scanning lines and the signal lines. A switching element array substrate having a switching element for performing a switching operation on a transparent insulating substrate, and a counter substrate having a counter electrode on the insulating substrate, the pixel electrode and the counter electrode of the switching element array substrate. In the liquid crystal display device, the switching element is arranged so as to face each other with a gap between them, and the opposite substrate is sealed around the periphery and holds a liquid crystal layer in the gap. An active layer formed of polycrystalline silicon on the plate, a gate insulating layer, at least three layers of a gate electrode connected to the scanning line, and an interlayer insulating film formed so as to cover the three layers. A thin film transistor provided, wherein the gate electrode and the scanning line are formed of a refractory metal, a refractory metal silicide, or a stacked layer of a refractory metal silicide and polycrystalline silicon. The inter-layer insulating film is a single-layer or multi-layer inter-layer insulating film including at least one layer formed of phosphorus, boron, or a silicon oxide film containing phosphorus and boron. .

In the above liquid crystal display device, the interlayer insulating film may contain 0.1 to 15% by weight of phosphorus or 0.1 to 15% by weight.
A liquid crystal display device comprising an interlayer insulating film formed by using a silicon oxide film containing 25% by weight of boron or 0.1 to 20% by weight of phosphorus and boron.

Also, in the method for manufacturing a liquid crystal display device of the present invention, an active layer made of a polycrystalline silicon film is formed on a transparent insulating substrate, and gate insulation is performed so as to cover the transparent insulating substrate including the active layer. Forming a layer, forming a gate electrode on the layer, forming an interlayer insulating film of a single layer or a laminated structure so as to cover the layer, and forming a switching element array substrate, and facing the insulating substrate. Forming a counter substrate by forming electrodes, and arranging the switching element array substrate and the counter substrate so as to face each other with a gap between the pixel electrode and the counter electrode, and surrounding the both substrates. A method of manufacturing a liquid crystal display device, which comprises a step of sealing and injecting a liquid crystal layer into the gap, wherein the gate electrode and the scanning line are made of a refractory metal, a refractory metal silicide, or a refractory metal silicide. Forming a stacked between the polycrystalline silicon, at least one layer of the interlayer insulating film,
A step of forming using phosphorus, boron, or a silicon oxide film containing phosphorus and boron; and, after forming the interlayer insulating film, subjecting the interlayer insulating film to heat treatment or high-frequency energy applying treatment, The method is characterized by comprising a step of heating the interlayer insulating film to a strain point or higher and a melting point or lower of the interlayer insulating film.

[0016]

In the conventional liquid crystal display device, for example, when the stacked structure of tungsten silicide and polysilicon is used for the scanning line and the gate electrode as described above, interlayer insulation is performed so as to cover the scanning line and the gate electrode thereafter. A silicon oxide film is used as a film at a low temperature and atmospheric pressure CVD method at about 450 ° C.
When the film is formed by the low pressure CVD method at about 800 ° C., after the interlayer insulating film is formed, the electric resistance values of the scanning line and the gate electrode covered by the interlayer insulating film increase to 15Ω / □ or more. As a result, the response characteristics of the switching element connected to the scanning line and the gate electrode are deteriorated.

The inventors of the present invention have confirmed that the above phenomenon is a unique phenomenon on a quartz substrate, which is a transparent insulating substrate used as a panel substrate of a liquid crystal display device, and does not occur on a single crystal silicon substrate. I found it.

Therefore, in the thin film transistor array substrate relating to the liquid crystal display device of the present invention, a high melting point metal or a high melting point metal silicide is formed in the pixel portion formed on the insulating substrate.
Alternatively, a silicon oxide film containing phosphorus or boron or both is used as an interlayer insulating film of a thin film transistor in which an address line is formed by stacking a refractory metal silicide and polycrystalline silicon, and a strain point or higher and a melting point or lower after the film formation are used. A heat treatment within a temperature range is performed. As a result, the interlayer insulating film is fluidized, and the interlayer stress existing at the interface between the scanning line and the gate electrode and the interlayer insulating film is relaxed. Further, the heat treatment improves the crystallinity of the polycide, the refractory metal, the refractory metal silicide, or the refractory metal silicide used as the material of the gate electrode or the scanning line, and the resistance of the scanning line and the gate electrode is reduced.

As described above, a silicon oxide film containing phosphorus or boron, or both is formed as an interlayer insulating film, and a heat treatment is applied to this film to scan lines even on a quartz substrate which is a transparent insulating substrate. Also, the electric resistance value of the gate electrode can be reduced to about 10 Ω / □ or less.

It is considered that this is due to the following action principle. That is, (1) after the interlayer insulating film is formed, heat treatment is applied to the interlayer insulating film to fluidize the interlayer insulating film, and to form an interface between the interlayer insulating film and the gate electrode or the scanning line. The existing stress was relaxed and the gate electrode and scan line electrical resistance decreased.

(2) By heat-treating the interlayer insulating film and the underlying gate electrode and scanning line covered therewith, polycide, refractory metal, refractory metal silicide or high-grade metal which is a material for forming the gate electrode and scanning line This is because the crystallinity such as the lamination of the melting point metal silicide and the polycrystalline silicon is improved, and the electric resistance of the gate electrode and the scanning line is reduced.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a liquid crystal display device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing the main part of the structure of a thin film transistor (TFT) array substrate in a liquid crystal display device according to the present invention.

(Embodiment 1) The principal part of the structure of the liquid crystal display device of the first embodiment according to the present invention is manufactured by the following manufacturing method.

First, a depressurized CV is formed on the transparent insulating substrate 101.
By the thermal decomposition method of disilane gas using D device, film thickness 1
A 35 nm a-Si (amorphous silicon) film is formed. As the transparent insulating substrate, a non-alkali glass substrate or a quartz substrate can be used.

Then, annealing is carried out at 600 ° C. for 25 hours to solid-phase grow the a-Si film to crystallize it and p-
An Si (polycrystalline silicon) film is formed, and this is patterned into an island shape to form an active layer 102 made of polycrystalline silicon. The polycrystalline silicon of the active layer 102 may be formed by crystallizing the a-Si film using light energy such as laser irradiation, in addition to the above-described annealing treatment.

After that, the surface of the active layer 102 is oxidized to form a gate insulating film (gate oxide film) 103.

Subsequently, the gate electrode 104 is formed. Then, by self-alignment using the gate electrode 104 as a mask, implantation of impurity ions into the active layer 102 exposed from the gate electrode 104 is performed by p-type / n implantation.
The source region 105 and the drain region 106 are formed according to the mold. The gate electrode 104 is integrally formed in the same layer by using the same material film as the scanning line (not shown). Further, as will be described later, the signal line 107 is formed of a wiring metal film so as to be connected to the source region 105 exposed by being opened due to the contact hole.

Then, a SiO _x film (silicon oxide film) 108a is formed at a film thickness of 100 to 200 nm at 450 ° C. so as to cover the main surface of the substrate including the gate electrode 104 and the active layer 102.
The film is formed by the low temperature atmospheric pressure CVD method. And this Si
On the O _x film 108a, P (phosphorus) or B (boron) or a SiO _x film 108b containing both P and B so that fluidization may occur by a heat treatment performed later.
Is formed to a film thickness of 500 to 1000 nm by using the low temperature atmospheric pressure CVD method as in the case of the SiO _x film 108a. The interlayer insulating film 109 is formed by the SiO _x film 108a and the SiO _x film 108b.

At this time, the P (phosphorus) concentration is preferably 0.1 to 25% by weight, more preferably 3 to 15% by weight. The concentration of B (boron) is 0.1 to 15% by weight, more preferably
1-10% by weight is preferred. In the case of the SiO _x film 108b containing both P (phosphorus) and B (boron), P
And the total of B is 0.1-20% by weight, more preferably 1-
It is preferably within the range of 15% by weight.

As the concentration of P and B is higher, fluidization is more likely to occur, and the flatness of the upper surface of the interlayer insulating film 109 is improved. On the other hand, however, if the concentration is too high, particles containing P and B are generated during the heat treatment, and these particles diffuse, for example, into the active layer 102 and the like as pollutants, which causes deterioration of the material in that portion. Therefore, the concentrations of P and B are set within the above range. Of the two layers of SiO _x film forming the interlayer insulating film 109, the SiO _x film 108a
Is the gate electrode 104 below the SiO _x film 108b.
It is formed for the purpose of preventing P or B from diffusing into the active layer 102 or the like and having an adverse effect.

Next, the above-mentioned thin film transistor array substrate is heated in a POCl ₃ (phosphoryl chloride) atmosphere, an N ₂ (nitrogen) atmosphere, or an H ₂ O (steam) atmosphere, and its interlayer insulating film 109 and gate electrode are heated. Heat treatment is performed on 104.

FIG. 2 is a diagram showing changes in electric resistance values corresponding to different heat treatment temperatures in the gate electrode 104 formed of the stacked structure of tungsten silicide and p-Si when the above heat treatment is performed. .

The electrical resistance value of the gate electrode 104 at the stage after the gate electrode 104 is formed by stacking the tungsten silicide and the p-Si stacked structure is about 20 to 30 Ω / □. Therefore, heat treatment is performed to reduce the resistance value to about 10 Ω / □.

However, if the interlayer insulating film 109 is formed thereafter so as to cover the gate electrode 104, the electric resistance value of the gate electrode 104 increases to about 15 Ω / □. Therefore, after that, heat treatment is further performed on the interlayer insulating film 109 and the gate electrode 104, whereby the electric resistance value of the gate electrode 104 can be significantly reduced. At this time, as is clear from FIG. 2, heat treatment at 850 ° C. is about 7Ω / □, at 900 ° C. is about 6Ω / □, 950 ° C.
In the heat treatment at, the resistance value can be reduced to less than about 5Ω / □.

In the above heat treatment, the flatness of the interlayer insulating film 109 improves as the heating temperature increases, and the gate electrode 104
The electric resistance value of is reduced. However, if heated to an excessively high temperature, impurity ions such as B (boron), P (phosphorus), and As (arsenic) implanted in the source / drain of the thin film transistor will become active layers 1 of the thin film transistor.
02 becomes easy to diffuse, which causes a short channel effect. Therefore, an appropriate range of processing temperature and processing time must be selected so that the electrical resistance of the gate electrode 104 can be reduced without impairing the operating characteristics of the transistor. From the viewpoint of preventing the diffusion of impurity ions as such pollutants, the temperature of the above heat treatment is not less than the strain point and not more than the melting point at normal pressure in an N ₂ atmosphere, more preferably between 850 ° C and 1000 ° C.
It is desirable to set the processing time to about 30 to 90 minutes.

After the above heat treatment, a contact hole is formed at a predetermined position, and a signal line 107 is formed from the metal wiring material film so as to make ohmic contact with the source region 105 through the contact hole. Further, a transparent conductive film is formed so as to be in contact with the drain region 106, and this is patterned into a predetermined shape to form the pixel electrode 110.

The thin film transistor array substrate thus manufactured is combined with a counter substrate having a counter electrode formed with a gap, and a sealing material is arranged around both substrates to seal the periphery. Then, the liquid crystal composition is injected into the gap between the two substrates to seal the injection port, and the liquid crystal display device is completed.

The liquid crystal display device of the present invention having the structure thus formed has the following features. That is, (1) a thin film transistor having a low resistance gate line was obtained, and a liquid crystal display device capable of realizing high-quality image display was obtained.

(2) The flatness on the interlayer insulating film is improved,
The disconnection of the signal line was suppressed.

(3) By using the low temperature atmospheric pressure CVD method for forming the interlayer insulating film between the gate line and the signal line, the film forming time is shortened as compared with the conventional case and the productivity is improved.

(4) By forming an interlayer insulating film using a SiO _x film containing phosphorus or boron, or both, a gettering effect by the interlayer insulating film with respect to mobile ions in the active layer can be obtained. A thin film transistor with stable operating characteristics could be formed. (5) an interlayer insulating film is a multilayer structure including a SiO _x film containing an SiO _x film and a phosphorus or boron or both, advantages over electrical short circuit caused by film defects as compared with the single layer structure is observed It was

(Embodiment 2) In the first embodiment, the thin film transistor array substrate is made of H ₂ O (water vapor) or the like as a means for performing heat treatment on the interlayer insulating film 109, the gate electrode 104, the scanning lines and the like. Although it was performed by exposing it to the above heating atmosphere, the heat treatment can also be performed by applying high frequency energy or energy such as microwave.
In this case, for example, if a film forming furnace using the above plasma or the like is used, the flattening step can be performed by continuous processing without exposing the furnace to the atmosphere. A typical example of such a case will be shown below as a second embodiment.

A BPSG film having a thickness of 900 nm was formed on an array substrate on which TFT elements were formed as in the first embodiment. B
The concentrations of boron and phosphorus contained in the PSG film are the same as in the first embodiment. Here, as a practical manufacturing method,
Instead of silane gas, TEOS (Tetra Ethyl Ortho-Sili
cate) and DADBS (Diacetoxyditertiarybutoxysilan)
An organic silane such as e) may be used. Further, TMP (Tri-Methyl Phospate) and TMB (Tri-Methyl Borate) may be used as the doping gas. In this embodiment, TEOS, which is a siloxane-based raw material, is used instead of silane gas.
(Tetra-etoxi-Silane) was used. Further, the above doping gas was used as the doping gas.

Then, in the present embodiment, the heat treatment step was performed using high frequency energy.

That is, a conducting wire was spirally wound around a quartz tube as a reaction tube, and a high frequency induction furnace for generating a high frequency energy by passing a high frequency current of 1 to 20 MHz was prepared. Nitrogen and oxygen were introduced into the reaction tube to maintain the atmosphere at a pressure of about 10 ^-2 torr to carry out the reaction. In addition to the above, the reaction may be performed under a normal pressure atmosphere using a microwave of 50 to 1000 MHz.

As a result of performing the heat treatment with such high frequency energy, the treatment time could be shortened to about half the time of the first embodiment.

In the above embodiments, for simplification of the description, the charges formed in parallel with the liquid crystal cell formed of the pixel electrode, the liquid crystal layer and the counter electrode to control the display state of the liquid crystal cell. Although the description of the structure of the auxiliary capacitance for assisting the above and the manufacturing method thereof is omitted, it goes without saying that such an auxiliary capacitance can be used in the liquid crystal display device according to the present invention.

Needless to say, the materials for forming the respective parts of the liquid crystal display device according to the present invention are not limited to the above-mentioned embodiments without departing from the gist of the present invention.

[0050]

As is clear from the detailed description above, according to the present invention, the increased electrical resistance of the scanning line and the gate electrode when the interlayer insulating film is formed can be suppressed to a low level to realize high display quality. The liquid crystal display device can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a thin film transistor array substrate in a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing changes in electrical resistance values of gate electrodes and scanning lines due to differences in heat treatment temperatures.

[Explanation of symbols]

101 ... transparent insulating substrate 102 ... active layer 103 ... gate insulating film 104 ... gate electrode 105 ... source region 106 ... drain region 107 ... signal line 108a ... SiO _x film (non-doped) 108b ... SiO _x film (doped) 109 ... interlayer Insulating film 110 ... Pixel electrode

Claims (3)

[Claims] 1. A plurality of scanning lines, a plurality of signal lines arranged so as to intersect the scanning lines, and a grid formed by the scanning lines and the signal lines. A switching element array substrate including a pixel electrode, a switching element connected to the pixel electrode, the scanning line and the signal line, and performing a switching operation of a liquid crystal driving voltage applied to the pixel electrode, on a transparent insulating substrate. A counter substrate having a counter electrode on an insulating substrate, the pixel electrode of the switching element array substrate and the counter electrode are arranged so as to face each other with a gap, and the periphery is sealed. In a liquid crystal display device comprising a counter substrate sandwiching a liquid crystal layer in the gap, the switching element includes an active layer formed of polycrystalline silicon on the substrate, a gate insulating layer, and A thin film transistor comprising at least three layers with a gate electrode connected to a scanning line, and an interlayer insulating film formed so as to cover the three layers, wherein the gate electrode and the scanning line are refractory metal, Or a gate electrode and a scan line formed of a high-melting-point metal silicide, or a stack of a high-melting-point metal silicide and polycrystalline silicon, wherein the interlayer insulating film is phosphorus or boron, or silicon oxide containing phosphorus and boron. A liquid crystal display device, which is an interlayer insulating film having a single layer or a laminated structure including at least one layer formed by using a film. 2. The liquid crystal display device according to claim 1, wherein the interlayer insulating film contains 0.1 to 15% by weight of phosphorus or 0.1.
A liquid crystal display device comprising an interlayer insulating film formed by using a silicon oxide film containing 1 to 25% by weight of boron or 0.1 to 20% by weight of phosphorus and boron. 3. An active layer made of a polycrystalline silicon film is formed on a transparent insulating substrate, a gate insulating layer is formed so as to cover the transparent insulating substrate including the active layer, and a gate electrode is formed thereon. A step of forming a switching element array substrate by forming an interlayer insulating film of a single layer or a laminated structure so as to cover it, and a step of forming a counter electrode by forming a counter electrode on the insulating substrate. And the switching element array substrate and the counter substrate are arranged to face each other with a gap between the pixel electrode and the counter electrode, the periphery of both substrates is sealed, and a liquid crystal layer is injected into the gap. And a step of forming the gate electrode and the scanning line with a refractory metal, a refractory metal silicide, or a laminated layer of a refractory metal silicide and polycrystalline silicon. A step of forming at least one layer of the interlayer insulating film using phosphorus, boron, or a silicon oxide film containing phosphorus and boron; and after forming the interlayer insulating film, A method of manufacturing a liquid crystal display device, which comprises a step of heating the interlayer insulating film to a temperature not lower than a strain point and not higher than a melting point of the interlayer insulating film by performing a heating process or a high frequency energy applying process.