JPH07123287A - Video signal conversion method - Google Patents

Abstract

PURPOSE:To display data on an entire screen whose aspect ratio is 16:9 by reading and latching three lines of data recorded in a field memory and a line memory alternately and outputting the data of 3 dots each from a latch section so as to magnify the data by a multiple of three in both horizontal and vertical directions. CONSTITUTION:Data of one dot each are read simultaneously from three field memories 4a, 4b, 4c of a field memory section 4 and at first a 1st dot signal of a 1st line is latched by three latches 9a, 9b, 9c of a latch section 9. Then a multiplexer 10 is used to convert the latched data into serial data sequentially. Simultaneously data read by one dot each are received by three line memories 5a, 5b, 5c of a line memory section 5 in which data of one line are recorded. The processing above is repeated sequentially to obtain dot structure magnified thrice. Thus, a pattern whose aspect ratio is 4:3 is magnified thrice and the resulting picture is displayed on an entire screen whose aspect ratio is 16:9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion method, which converts a video signal of a computer device or the like into a video signal of the HDTV system or the like, which can be displayed on a display device of the HDTV system or the like.

[0002]

2. Description of the Related Art FIG. 4 and FIG. 5 show a block diagram of a conventional main part and a dot configuration diagram. Conventionally, a video input unit for inputting analog RGB video signals having substantially the same vertical sync frequency but different horizontal sync frequencies, such as a computer device, and an A / D conversion unit for converting the video signal from the video input unit into a digital signal. An S / P converter for converting a digital signal from the A / D converter into a parallel signal from a serial signal; a field memory unit for recording the parallel signal from the S / P converter; Writing in the field memory based on the vertical synchronizing signal, horizontal synchronizing signal and dot clock signal, and reading based on the vertical synchronizing signal, horizontal synchronizing signal and dot clock signal for HDTV generated by the synchronizing signal generator. A memory control unit for controlling, a latch unit for latching a digital signal read from the field memory unit, and a latch The P / S conversion unit, such as a multiplexer, which converts the parallel signal read by the control unit into a serial signal, and the D / A conversion unit, which converts the serial digital signal into an analog signal, are converted into analog signals. The video signal is output from the video output section. With the above configuration, the video signal for displaying on the screen of the computer device having the aspect ratio of 4: 3 is enlarged to 2 times or 4 times and displayed on the screen of the HDTV system having the aspect ratio of 16: 9.
-As shown in (a), invalid areas that are not displayed appear at the top, bottom, left, and right ends, and the screen usage rate is (screen usage rate) = (number of pixels in video display area) / (number of HDTV system screen effective pixels)
= ((1280 × 960) ÷ (1920 × 1035))
× 100% = 61.8%, and FIG.
As shown in (b), there are many non-displayable areas that cannot be displayed outside the upper, lower, left, and right screens, and the screen display rate is (screen display rate) = (HDTV system screen effective pixel count).
÷ (Number of effective pixels for video) = ((1920 × 1035) ÷
(2560 × 1920) × 100% = 40.4%, so that a video signal of a computer device having an aspect ratio of 4: 3 can be effectively displayed on a display device such as an HDTV having an aspect ratio of 16: 9. could not.

[0003]

In view of the above-mentioned problems, the present invention provides a method for magnifying a video signal of a computer or the like by a factor of 3 to effectively display it on the screen of a display device such as an HDTV. With the goal.

[0004]

In order to solve the above problems, the present invention provides a video input section for inputting analog RGB video signals having substantially the same vertical sync frequency but different horizontal sync frequencies in a computer device and the like. From the A / D converter that converts the video signal from the input unit into a digital signal, the S / P converter that converts the digital signal from the A / D converter into a parallel signal from the serial signal, and from the S / P converter Field memory section for recording the parallel signal, the line memory section for recording one line of the parallel signal read from the field memory section, the vertical synchronizing signal, the horizontal synchronizing signal and the dot clock signal which are input at the same time as the video signal. Based on the writing of the field memory unit and the line memory unit, and the vertical synchronizing signal for HDTV generated from the synchronizing signal generator, A memory control unit for controlling the reading of the field memory unit and the line memory unit based on the flat sync signal and the dot clock signal, and a digital signal read from the field memory unit or a digital signal read from the line memory unit. It is composed of a latch section, a P / S conversion section such as a multiplexer for converting a parallel signal from the latch section into a serial signal, and a D / A conversion section for converting the serial digital signal into an analog signal. The video signal is output from the video output section.

[0005]

With the above-described configuration, analog RGB video signals having substantially the same vertical synchronizing frequency but different horizontal synchronizing frequencies of computer devices are converted into digital signals, and the digital signals are converted from parallel signals into parallel signals. Then
One field of the parallel signal is sequentially recorded in the field memory, and reading from the field memory is performed by the HDT.
Based on the vertical synchronizing signal for V, the horizontal synchronizing signal, and the dot clock signal, it is performed for each horizontal line, and the signal for one line read from the field memory is recorded in the line memory and recorded in the field memory and the line memory. Alternately read the data for 3 lines on the screen, latch it, output 3 dots for every 3 dots from the latch part, convert it to a parallel signal which is expanded 3 times in the horizontal and vertical directions, and then convert it to a serial signal. Then, it is sent from the video output section to the display device as an HDTV RGB video signal.

[0006]

Embodiments of the video signal conversion method according to the present invention will be described in detail below with reference to the drawings. 1 is a block diagram of an essential part showing an embodiment of a video signal converting method according to the present invention. FIG. 1 is a detailed block diagram of part A of FIG. 1- (a).
It is shown in (b). An image input unit 1 receives analog RGB image signals having substantially the same vertical synchronizing frequency but different horizontal synchronizing frequencies of a computer device and the like, with matching impedances, and amplifies them to an optimum level. Reference numeral 2 denotes an A / D conversion unit that converts a video signal from the video input unit into a digital signal. Reference numeral 3 is an S / P (serial / parallel) converter, which converts a digital signal from the A / D converter from a serial signal to a parallel signal. Reference numeral 4 is a field memory unit, and three field memories are provided for each color signal, totaling 9 fields.
Individually prepared, the same parallel signals from the S / P converter are simultaneously recorded so that an element having a slow processing speed can be used. A line memory unit 5 records the parallel signals read from the field memory unit 4 for one line. Reference numeral 6 denotes a sync signal input section for receiving a sync signal input simultaneously with the video signal with matching impedance, separating it into a sync signal such as a vertical sync signal, a horizontal sync signal and a dot clock signal, and amplifying to an optimum level. And a memory controller 7 for writing to the field memory and line memory based on the vertical synchronizing signal, horizontal synchronizing signal and dot clock signal distributed from the synchronizing signal input section. Also, the reading from the field memory and the line memory is controlled based on the vertical synchronizing signal for HDTV, the horizontal synchronizing signal and the dot clock signal generated from the synchronizing signal generator 8. A latch unit 9 latches the digital signal read from the field memory unit or the digital signal read from the line memory unit to adjust the timing. The multiplexer unit 10 converts a parallel signal from the latch unit into a serial signal, the D / A converter 11 converts the digital signal into an analog signal, and the analog output video signal is output from the video output unit 12. Configured to output.

FIG. 2 shows a dot configuration on the display screen of the HDTV system according to the present invention. In the figure, a two-digit number indicates a dot number, ODD and EVEN indicate lines of an odd field and an even field, respectively, and the whole shows a part of a frame resulting from interlaced scanning. 1 dot data obtained by A / D converting a video signal from a computer or the like is displayed on 1 line, that is, 3 dots in the horizontal direction, and is displayed vertically for 3 lines including ODD and EVEN. It indicates that one pixel is formed by multiplying the pixels of the video signal of 3 in both the vertical and horizontal directions, that is, 9 dots. One dot at a time is read from the three field memories 4a, 4b, 4c of the field memory unit 4 at the same time. First, the first dot (1) of the first line (L1) is read.
1) The signal is the three latches 9a, 9b, 9 of the latch unit 9.
latched by c, the multiplexer 10 sequentially converts the latched data into serial data. Next, the second dot (12) signal of L1 is latched by the three latches 9a, 9b, 9c of the latch unit 9, and the multiplexer 10
Converts the latch data into serial data sequentially.
By repeating this, the data of the first line of the odd field of the HDTV system is converted into the dot configuration like the first ODD column in FIG. Also, the three field memories 4a, 4b,
The data of the first line (L1) read from the 4c at the same time for each dot is input to the latch unit 9 and at the same time, the three line memories 5a, 5 of the line memory unit 5 are connected.
Input to b and 5c and one line is recorded.

At the data timing of the second line of the odd field of the HDTV system, the line memories 5a, 5
One dot at a time is read from b and 5c at the same time. First, the first dot (11) signal of the first line (L1) is latched by the three latches 9a, 9b and 9c of the latch unit 9, and the multiplexer 10 , The latch data is sequentially converted into serial data. Next, the second dot (12) of L1 is the three latches 9a, 9b, 9c of the latch unit 9.
, And the multiplexer 10 sequentially converts the latched data into serial data. By repeating this, the data of the first line of the odd field of the HDTV system is converted into the dot configuration like the second ODD column in FIG.

At the data timing of the third line of the odd field of the HDTV system, the field memory unit 4 is used.
Simultaneously from the three field memories 4a, 4b, and 4c of the same, first, the first dot (2
1) The signal is the three latches 9a, 9b, 9 of the latch unit 9.
latched by c, the multiplexer 10 sequentially converts the latched data into serial data. Next, the second dot (22) signal of L2 is latched by the three latches 9a, 9b, 9c of the latch unit 9, and the multiplexer 10
Converts the latch data into serial data sequentially.
By repeating this, the data of the first line of the odd field of the HDTV system is converted into the dot configuration like the third ODD row in FIG. In the data timing of the fourth, fifth, and sixth lines of the odd field of the HDTV system, the first, second, and
In the order of the method described in the timing of three lines, L3, L
4 signals are converted, and this is repeated to convert signals for the screen of one odd field. Then in the even field,
In the order of the method described in the timing of the third, first, and second lines of the odd field of the HDTV system, L1, L2, L
The signals of 3 ... Are converted, and this is repeated to convert the signals for the screen of one even field. In this way, a dot structure enlarged three times as shown in FIG. 2 is obtained.

FIG. 3 is a diagram showing an HDTV system with an aspect ratio of 16: 9, which is obtained by enlarging a screen having an aspect ratio of 4: 3 in a computer device to 3 times by the image conversion method according to the present invention.
The number of effective pixels on the display screen is (1920 × 1035) and the number of effective pixels of the video display area is also (1920 × 1035), so that the screen utilization efficiency is 100%. The number of effective display pixels on the screen of the computer device displayed in the video display area is (640 × 34
In 5), since the total number of effective display pixels on the screen of the computer device is (640 × 480), the image display rate is 71.
8%. According to the present invention, the number of effective pixels on the display screen in the case of 2 times enlargement of the conventional one is 1280 × 960, the screen utilization efficiency is 61.8%, and the effective display pixels on the screen of the computer device in the case of 4 times enlargement. The number is 480 × 258 and the image display ratio is 40.3%, and thus a video signal conversion method with sufficiently high efficiency can be provided.

[0011]

As described above, according to the video signal conversion method of the present invention, 640 × 480 pixels out of 640 × 480 pixels of a screen having an aspect ratio of 4: 3 in a computer device or the like.
A method can be provided in which 345 pixels are enlarged three times and displayed on the entire screen of the HDTV system with an aspect ratio of 16: 9.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a video signal conversion method according to the present invention.

FIG. 2 shows a dot configuration on a display screen of an HDTV system according to the present invention.

FIG. 3 shows the number of effective pixels and the number of effective display pixels on a display screen according to the present invention.

FIG. 4 is a block diagram of essential parts showing an embodiment of a conventional video signal conversion method.

FIG. 5 shows a dot configuration on a display screen of an HDTV system according to a conventional method.

FIG. 6 shows the number of effective pixels and the number of effective display pixels on a display screen according to a conventional method.

[Explanation of symbols]

 1 Video Input Section 2 A / D Conversion Section 3 S / P Conversion Section 4 Field Memory Section 5 Line Memory Section 6 Sync Signal Input Section 7 Memory Control Section 8 Sync Signal Generator 9 Latch Section 10 Multiplexer Section 11 D / A Conversion Section 12 Video output section

Claims (5)

[Claims] 1. A video input section for inputting analog RGB video signals having substantially the same vertical sync frequency but different horizontal sync frequencies, such as a computer device, and an A / D for converting the video signal from the video input section to a digital signal. From the conversion unit, the S / P conversion unit that converts the digital signal from the A / D conversion unit into the parallel signal from the serial signal, the field memory unit that records the parallel signal from the S / P conversion unit, and the field memory unit A line memory unit for recording the read parallel signal for one line, and writing from the field memory on the basis of a vertical synchronizing signal, a horizontal synchronizing signal and a dot clock signal input at the same time as the video signal, and generated from a synchronizing signal generator A memory control unit for controlling reading based on the vertical synchronizing signal, the horizontal synchronizing signal, and the dot clock signal, P / S such as a latch unit for latching a digital signal read from the field memory unit or a digital signal from the line memory unit and a multiplexer for converting a parallel signal from the latch unit into a serial signal
A video signal conversion method comprising a conversion unit and a D / A conversion unit for converting the serial digital signal into an analog signal, and outputting the analog-converted video signal from the video output unit. 2. The field memory unit includes R, G, B
2. The video signal conversion method according to claim 1, wherein three field memories are provided for each. 3. The video signal conversion method according to claim 1, wherein the field memory has a FIFO structure. 4. The video signal conversion method according to claim 1, wherein the line memory unit is provided with three line memories for each of R, G and B. 5. The video signal conversion method according to claim 1, wherein the line memory has a FIFO structure.