JPH0712205B2 - Image transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a first image recording medium on which an image signal is recorded,
The present invention relates to an image transfer device that reads out the image signal, transfers the image signal for a plurality of screens to a recordable second image recording medium, and records the image signal.

Conventionally, in this type of camera, miniaturization has been aimed at in order to improve portability. Therefore, it is conceivable to divide the image recording medium requiring a relatively large space into the first image recording medium and the second image recording medium. For example, the camera device can be downsized by mounting the first image recording medium having a relatively small capacity on the camera body and performing shooting. However, if the capacity of the first image recording medium is reduced to reduce the size, for example, if the capacity of a still image is reduced to about 20 screens, the number of images that can be captured at one time is limited. It means that recording another image signal in the image area where the image signal was once recorded means that the previous image signal that you want to save will be deleted, or that the previous and current image signals are mixed. Because it is not convenient. Therefore, since only the first image recording medium can capture only 20 screens, another image recording medium is required.
That is, the recorded content of the first image recording medium that has been photographed is transferred to, for example, the second image recording medium provided outside. Once transferred, there is no problem in making the first image recording medium reusable. The second image recording medium can also be used for storage. Therefore, an image transfer device for transferring the image signal recorded by the first image recording medium to the second image recording medium is required.

An object of the present invention is to provide an image transfer device that simply and automatically transfers only a shooting screen when transferring from a first image recording medium to a second image recording medium.

1 and 2 show the appearance of one embodiment of the electronic camera used in the present invention. The camera comprises an image pickup unit 1 for photoelectrically converting a subject image into a still image signal, and a storage unit 2 provided with a memory for storing one frame of still image information for 20 frames. Both these parts are separable as shown in FIGS. 3 (a) and 3 (b).

A photographing lens 10 is mounted on the front surface of the image pickup unit 1, and the lens 10 forms a subject image on the image pickup surface of an image pickup element 11 arranged inside the image pickup unit 1 as shown in the sectional view of FIG. To do. A diaphragm 10a is arranged on the lens 10, and a mosaic filter 11a for color separation is arranged on the front surface of the image pickup element 11. Further, the image pickup unit 1 is provided with a finder 12 penetrating from the front surface to the rear surface thereof to define a photographing field of view, and in FIG. 1, the upper surface thereof is provided with a contact 13 for attaching an external light source such as a speedlight. An accessory shoe 14 and a release button 15 are provided. When the release button 15 is pressed shallowly, the power supply switch inserted in the power supply circuit is turned on, and power is supplied. Along with this, the photometric operation is performed. When the release button 15 is pressed deeply, the power supply switch remains ON and the shooting sequence is further started. Once the shooting sequence is started, it does not stop even if the release button 15 is released halfway. Further, the power supply switch is kept ON until the shooting sequence ends. In FIG. 2, on the rear surface of the image pickup unit 1, a mode selection lever 16 for selecting one of a mode for automatically accessing the address of the memory cell of the storage unit 2, a mode for manual access and a mode for multiple exposure, and a manual A push button 17 for access, a 7-segment display device 18 such as a liquid crystal display for displaying the address of the memory currently accessed, and a switch 19 for disabling the sound warning device are provided. Further, on the side surface of the image pickup unit 1, a mounting screw 100 for mounting an external accessory such as a data imprinting device or an electronic monitor device for monitoring a subject image, and a connector 130 for the accessory.
And are respectively provided.

As shown in FIG. 2, a display device 201 such as a liquid crystal or an electrochromic device for displaying the address of a used memory and a storage capacity (the total number of memory cells, that is, the number of storable frames) on the rear surface of the storage unit 2. ) And the like are provided on the label 202. Further, as shown in FIG. 3 (b), there is a detachable slider 203 on the side surface. When this is slid to the right, the detachable key 204 protruding on the upper surface of the storage unit 2 slides in the same direction, and the engagement with the fixed key (not shown) in the corresponding portion of the image pickup unit 1 is released and the storage unit 2 is released. Can be separated from the imaging unit 1. The storage unit 2 is provided with a T-groove 205, which is a guide member on the side of the imaging unit at the time of attachment / detachment.
Engage with 131 and guide it.

A connector 206 and a pin 207 are provided upright on the upper surface of the storage unit 2. The connector 206 is connected to a corresponding connector (not shown) of the image pickup unit 1 to mutually transmit electric signals.
The pin 207 mechanically transmits the storage capacity of the storage unit 2 to the imaging unit 1.

FIG. 5 illustrates an internal structure of the image pickup device 11 of the image pickup unit 1.
This is a so-called interline type charge engagement device (CC
A CCD image pickup device using D), in which light receiving elements a _{1 and 1} and a _{1, 2} , ..., a _{1 .n} , a ₂ .1, a _{2 .n} ,
_{...... a m · 1, a m} · 2, ......, a m · n are arranged in an m × n matrix constitutes a light receiving portion. The total number of light receiving elements, that is, the number of pixels is preferably about 10 ⁶ . A row of these light-receiving elements, for example a _{1, 1} , a
The both sides of each of _{2 · 1, a m} · 1 transfer gate TG _{1 · 1} and TG _{2 · 1} are disposed. Gate
TG _{1 · 1} transfers the charge corresponding to the amount of incident light to the transfer signal phi _TG1 via the terminal 11C is accumulated to be applied to each element in the longitudinal direction to the CCD analog shift register S _V1. While the gate TG _{2 · 1} transfer signal phi _TG2 via the terminal 11b to transfer the application and the charge to the area OD ₁ of the overflow drain. Incidentally, the electrical potential of the transfer gate TG _{2 · 1} is slightly lower than the potential between each bit of the transfer signal phi _TG2 potential and longitudinal shift register between the light receiving element each other even if is not applied S _V1. Therefore, the charges overflowing from the potential well of the light receiving element flow into the direction of the lower barrier, that is, the overflow drain OD ₁ , and the blooming phenomenon is prevented. The above is exactly the same for other rows of light receiving elements. Overflow drain OD ₁ from the output terminal 11a ......, charges transferred to ODn is output to the input terminal 11b the transfer gate TG _{2 · 1,}
...... transfer signal phi _TG2 to TG _{2 · n} is inputted, the transfer gate TG _{1 · 1} to the input terminal _11c, ..., TG
The transfer signal φ _TG1 to _{1 · n} is input.

The transfer gate _{TG 1 · 1, ......, TG} 1 · longitudinal shift register by the transfer signal phi _TG1 to _n S _V1, ......,
The charges transferred to Svn are sequentially transferred downward by the vertical transfer pulses φ _V1 and φ _V2 input via the input terminals 11d and 11e, and are sent to each bit of the horizontal shift register Sh. Then, it is transferred to the right by lateral transfer pulses φh ₁ and φh ₂ input through the input terminals 11f and 11g, amplified by the sense amplifier A, and taken out from the terminal 11h to the outside.

FIG. 6 shows the circuit configuration of the storage unit 2. FIG. 6 (a) shows the memory MC1 for one frame taken out and showing the inside thereof, which includes the memory matrix RM, addressing circuits Ax and Ay, address counters Cx and Cy, and input circuit IP.
It also includes a random access memory consisting of an output circuit OP. Memory matrix RM is 4 bits / 1
The memory cell group of words is provided by the number obtained by adding 1 to the total number of light receiving elements included in the image pickup element 11 (that is, the total number of pixels m × n). That is, (m × n + 1) words ×
It has a 4-bit configuration. 1 with this 1-word digital signal
Pixel gradation is expressed. The amount of information that can be represented by 4 bits is 16 steps from 0000 to 1111 in binary, of which 11 are
The steps are used for gradation expression, and the remaining five steps, for example, 1111, 111
0, 1101, 1011, and 0111 are used as information indicating the start position of the image signal for one frame. Hereinafter, this 4-bit information is called a start signal. If such five kinds of start signals are prepared, noise will be introduced into one of the four bits, and there will be no problem even if one of the four bits originally should have been 1111 becomes 0. Therefore 0000, 0001, 001
The same thing can be said even if five kinds of 0, 0100, and 1000 are adopted as the start signals. A memory cell group of 1 word is addressed to the input terminals MC1g to MC1j via the input circuit IP and the output circuit OP by designating its address by the X-direction addressing circuit Ax and the y-direction addressing circuit. The output terminals MC1a to MC1d are accessed. The addresses of the designation circuits Ax and Ay are given by the x-direction address counter Cx and the y-direction address counter Cy, respectively. That is, these counters are connected immediately before and count the clock pulse φ _CT input to the counter Cx from the terminal MC1f. This counter starts from x = 0, y = 0 and accesses the memory of the row of y = 0. At the end, x returns to 0, and y = 1 by the digit increase, and access to the memory of this row is started.
In this way, when all the memories in the memory matrix RM have been accessed, it is configured to return to x = 0 and y = 0 again.

The start signal and the image signal are sequentially sent to the input terminals MC1g to MC1j in synchronization with the clock pulse φ _CT . First, when the clock pulse φ _CT goes high, the input circuit IP opens. At the same time, a start signal is input via it, and the address (x
= 0, y = 0). Subsequently, when the H-level pulse falls, the counter Cx counts up and the memory at the next address (x = 1, y = 0) is accessed. When the pulse goes to L level, the output circuit OP
Opens. Next, when the pulse goes to H level, the input circuit IP opens and the first image signal is input and stored in the accessed address (x = 1, y = 0).

By repeating the above operation, the last address (x-m, y =
The last image signal is stored in the memory of n), and when the pulse falls, the memory of the first address (x = 0y = 0) makes access again. Then, when the clock pulse becomes L level, the output circuit OP opens and the start signal stored therein is output to MC1a to MC1d.
If the clock pulse φ _CT from MC1f is stopped, the image signal for one frame is stored in the memory matrix RM. A detection circuit DC is connected to the output terminals MC1a to MC1d, and one of five types of start signals is output.
If one appears, it is detected and an output signal indicating that the image signal has been transferred to the memory MC1, that is, the memory MC1 has been used, is output to the output terminal MC1k.

The reset terminal MC1e is for resetting the start signal by sending a reset signal to the terminal when the start signal is being accessed.

As will be described in detail later, this function is used when reusing a frame of an address that has failed to be photographed or performing multiple exposure.

FIG. 6 (b) shows an example of the configuration of the circuit system 2a of the storage unit 2 because a plurality of memories MC for one frame as described above are assembled. Twenty memories MC1 (MC1 to MC20) as shown in FIG. 6 (a) are provided, and these input terminals are all connected to the address setting circuit AS except the output terminals MC1k to MC20k of the detection circuit DC. ing. The address setting circuit AS is provided with an address input terminal MA, an output terminal MO, an input terminal MI, an input terminal MT for the transfer clock pulse φ _CT and a reset terminal MR. When the signal φ _A of the memory address at the address input terminal MA is input, for example, 1
When a signal that selects the memory at the address is input, the output terminals MC1a to MC1d of the memory MC1 at the address 1 are output to the output terminal MO,
Memory input terminals MC1g to MC1j are input terminals MI, memory clock terminal MC1f is terminal MT, memory reset terminal MC
1e is selectively connected to the terminal MR, and the memory MC1 at address 1 is accessed.

On the other hand, the output terminals MC1k to MC20k of the detection circuit DC are all connected to the display circuit DP, and the output of the circuit DP drives the display device 201 which displays the memory in which the start signal is output, that is, the used memory. This device 201 includes an electro-optical element such as liquid crystal or electrochromic and has an appearance as shown in FIG. In this example, the storage device has a storage capacity of "20 frames", and 20 liquid crystal or electrochromic segments are lined up.
Of these, the segment corresponding to the used memory receives the output signal of the detection circuit DC and is colored. In this example, 1-6,
This means that the memories MC1 to MC6 and MC8 to MC10 at the addresses 8 to 10 have been used.

FIG. 8 shows a circuit system 1a of the image pickup section 1. In the image pickup device 11 as shown in FIG. 5, the output terminal 11a of its overflow drain is connected to the input terminal of the photometric circuit 102 including a photocurrent amplifier. The output of the photometric circuit is a memory operation circuit
The circuit 103 is connected to the input terminal of 103, and the circuit 103 calculates an exposure time value and an aperture value that provide proper exposure based on the output of the photometric circuit 102. The control pulse generation circuit 101 generates various pulses that control the imaging sequence, and the circuit 103 has its terminal 101.
When receiving the signal φ _101C from c, the output signal of the photometric circuit 102 is stored. The storage operation circuit 103 has three output terminals, and the first output of the circuit 103 is supplied to the display circuit 106 via the first terminal.
The output of the circuit 106 drives a display device 107 including a display element such as an LED and a liquid crystal provided in the finder, and displays an exposure time, an aperture value and the like. Arithmetic circuit 103
The second output of is input to the aperture control circuit 105 via the second terminal, and the output of the circuit 105 controls the aperture 10a of the taking lens. Further, the third output of the circuit 103 is input to the clock circuit 104 via the third terminal, and the circuit 104 outputs the pulse generation circuit 101.
The signal φ ₁₀₁ a from the output terminal ₁₀₁ a of the above is received, and after that time, an exposure end signal is sent to the input terminal 101 b of the pulse generation circuit 101 after a time corresponding to the output of the circuit 103.

Each of the input terminals 11b to 11g of the image pickup device 11 is a pulse generation circuit 101.
Connected to the output terminals 101d to 101i of the
The various control pulses φ _TG2 , φ _TG1 , for driving 11
Receives φ _V1 , φ _V2 , φh ₁ and φh ₂ . The output terminal 11h of the image pickup device 11 is connected to the AD conversion circuit 108, where an analog signal corresponding to the light intensity of each pixel (each light receiving element) is converted into a 4-bit digital signal and sent to the selection gate 109. Adder circuit 110 used for multiple exposure
Is the output of the AD conversion circuit 108 and the image signal input from the storage unit 2 via the input terminal CI, and is divided by 2. That is, the arithmetic mean of the two is taken and the signal is selected by the selection gate 109.
Add to. The switch 16d is the mode selection lever 16 shown in FIG.
When the lever 16 is in the position of MUL (multiple exposure), it is turned on and the addition circuit 110 is activated,
In other cases, it is turned off and the adder circuit 110 is made inoperative. Switch 16c also opens and closes in conjunction with lever 16,
Turns on when lever 16 is in the MUL position and selects gate 1
The output of AD circuit 108 is blocked while the output of adder circuit 110 is passed through 09. Switch 16c is lever 16
When it is in another position, it is turned off, and the output of the AD conversion circuit 108 is passed through the gate 109 contrary to the above, and the output of the adder circuit 110 is blocked. The output signal of the selection gate 109 is sent to another selection gate 111. The select gate 111 has a start signal generating circuit for generating the start signal described above.
The output terminal of 112 is also connected. The gate 111 selects either the output of the selection gate 109 or the output of the start signal generation circuit 112 according to the signal φ ₁₀₁ k from the output terminal ₁₀₁ k of the control pulse generation circuit 101, and the storage unit 2 via the output terminal CO.
Output to. The detection circuit 113 determines whether the signal input from the output terminal MO of the storage unit 2 via the input terminal CI is a start signal, and sends the resulting signal to the input terminal 101j of the control pulse generation circuit 101. .

The content of the address counter 114 is sent to the address setting circuit AS of the storage unit 2 via the 5-bit output terminal CA to access the memory cell at the specified address. On the other hand the counter
The output of 114 drives the aforementioned display device 18 via the display circuit 117 to display the address of the memory cell being accessed. The switch 16a is interlocked with the mode selection lever 16 shown in FIG. 2, and when the lever 16 is in the A (automatic access) position, the terminal A in FIG. 8 and the MAN (manual access) or MUL position is the 8th position. It is connected to the terminal M in the figure. The manual address setting circuit 115 outputs one pulse each time the push button switch 17a is turned on when the switch 16a is at the position of the terminal M, and changes the contents of the address counter 114 one by one. When the switch 16a is switched to the position of the terminal A, the address counter 114 is connected to the output terminal 101i of the control pulse generating circuit 101 via the input terminal 114a, and the circuit 1
Count clock pulses from 01. The switch 16b is interlocked with the mode selection lever 16 and is OF when the lever is in A.
F, it is turned on when it is in another place, and informs the control pulse generation circuit 101 via the input terminal 101n whether or not the selected mode is the automatic access. The one-shot multivibrator 116 is switched to the switch 15a by pressing the release button 15.
Is turned on, a single pulse φ _S is generated and the input terminal 101p
A signal for starting the photographing sequence is sent to the circuit 101 via. Output terminal 101q is transfer pulse φ for memory
_{The CT} is sent to the storage unit 2 via the output terminal CT. Output terminal 101r
Sends a reset pulse sent to the storage unit 2 to the input terminal MR of the storage unit 2 via the output terminal CR. The output terminal 101s outputs a signal φbusy indicating whether or not the shooting sequence is in progress. The signal φbusy causes the sounding body 119 to emit a warning sound via the drive circuit 118, and the warning display device 121 such as an LED 121 via the display circuit 120.
Is turned on, and the electromagnet 123 is operated via the drive circuit 122 to make it impossible to remove the storage unit 2 from the image pickup unit 1 during the shooting sequence by a safety device (not shown).
A switch 19 (see FIG. 2) is inserted between the output terminal 101s and the drive circuit 118 to turn off the warning sound by turning it off. The output terminal 101m is connected to the circuits 117 and 118, and when the memory of the storage unit 2 is completely used and there is no free space, a continuation signal is issued, the display device 18 blinks, and the sounding body 19 sounds intermittently. , It is displayed that there is no unused memory cell in the storage unit 2. The output of the output terminal 101a is sent as a tuning signal to the speedlight or the like via the contact 13 (see FIG. 2). Changeover switch 12 connected to input terminal 101t
Reference numeral 4 denotes a pin 207 that is erected on the upper surface of the storage unit 2 (Fig. 3 (b)).
The storage capacity of the storage unit 2 is transmitted to the circuit 101. When the memory unit 2 is removed from the image pickup unit 1, the switch 124 causes the counter 114 to be a reset terminal.
It is connected to 114r and resets the contents of the counter 114.

FIG. 9 is a perspective view showing the appearance of a converter having a reproducing function and a monitor according to an embodiment of the present invention. In FIG. 9, a converter 3 for transferring the image signal stored in the storage unit 2 to the magnetic tape cassette and a monitor 4 for imaging the image signal are shown. The converter 3 is provided with a connector 301 connected to the connector 205, a cassette holder 302 into which a magnetic tape cassette is loaded, and an operation key board 303. Next, the operation of this embodiment will be described. First, in FIG. 2, the storage unit 2 is attached to the image pickup unit 1. As a result, the connector 206 of the storage unit 2 is connected to the connector (not shown) of the image pickup unit 1, and the terminals MA, MO, MI, MT and MR shown in FIG. 6B are the terminals CA and CI of FIG. , CO,
Connected to CT and CR respectively. Now, set the mode selection lever 16 of the image pickup unit 1 to the position of automatic access A, and turn on the switch 19.
Let's say Then, the switch 16a in FIG. 8 is connected to the terminal A, and the switches 16b, 16c and 16d are turned off.
It becomes the state of. In this state, the taking lens 10 is aimed at the subject, the composition is determined, and the focus is adjusted. And release button 15
When is pressed deeply, the switch 15a in FIG. 8 is turned on, and the single pulse φ _S shown in the time chart of FIG. 10 (a) from the one-shot multivibrator 116 is input to the input terminal 101p of the control pulse generation circuit 101. Is emitted. The circuit 101 which has received it emits a pulse φ _A from the output terminal 101i at the timing shown in FIG. This pulse φ _A is for switch 16
It becomes an input of the address counter 114 via a. The counter 114 is reset when the storage unit 2 is removed from the image pickup unit 1.

Therefore, the content of the counter advances from 1 to 1 every time one pulse φ _A enters. As a result, the counter 114 has terminals CA and MA.
The memory in the storage unit 2 is sequentially accessed via the. That is, when the counter 114 counts the first pulse from the terminal 101i, the first memory MC1 is accessed first, then the second pulse is counted, the second memory MC2 is accessed, and so on. The last memory MC20 is accessed each time. The detection circuit 113 receives the output signal of the memory accessed by the counter 114 via terminals MO and CI,
If this is a start signal, an L level signal φ ₁₁₃ is sent to the input terminal 101j otherwise. Usually, most of the memories of the newly installed storage unit 2 are unused, so the signal φ ₁₁₃ is the first memory M.
Access C1 and immediately go to H level. Therefore, the first memory MC1 is accessed for photographing, and the address of the first memory, that is, "1" appears on the display device. However, if some memories, for example, the first to third memories MC1 to MC3 have been used, the circuit 101 counts the pulse φ _A while the output φ ₁₁₃ of the detection circuit ₁₁₃ is at the L level. Continue sending to 114. In this way, when the address is advanced one by one and an unused memory, in this case, the fourth memory MC4 is reached, the output φ ₁₁₃ is output, as shown in FIG. 10 (b).
At the timing shown in (4), the H level is set and the output of the pulse φ _A stops. Then, the memory at that time is accessed for photographing, and the address of the memory is displayed on the display device 18.
The process described above is called an address search. If the output of the circuit 113 does not become the H level even if the address pulse φ _A is issued by the number of frames transmitted by the pin 270 and the changeover switch 124, the circuit 101 indicates that all the memories in the storage unit 2 have been used. To detect. Then the circuit 101
Emits an intermittent signal from the terminal 101m to cause the display device 18 to blink, the sounding body 119 emits an intermittent sound, and stops the photographing sequence. This allows the photographer to know that there is no unused memory. This series of warning operations is also performed when the release button is pressed without attaching the storage unit 2 to the image pickup unit 1. This is because the circuit 101 detects that the storage unit 2 is not mounted by opening the switch 124. The warning that the storage unit 2 is not mounted is such that the storage unit is mounted inside the imaging unit and the presence of the storage unit cannot be visually recognized from the outside. Is especially effective in the case of.

Output of circuit 113 when unused memory is accessed φ ₁₁₃
Goes to the H level, and the pulse φ _A stops. As shown in FIG. 10 (e), the output φ _{TG2 of the} terminal 101d goes to the H level with the start of power supply by pressing the release button 15 shallowly, and FIG. keep the transfer gate TG _{2 · 1} ~TG _{2 · n} of the image pickup device 11 in the open state shown in. Thus the light receiving element a _{1 · 1,} ..., an overflow drain OD ₁ ~ODn without charges generated according to the intensity of light irradiated to a m · _n is stored in each element, the output terminal 11
It is always taken out as a photocurrent via a, and is subjected to processing such as amplification, logarithmic conversion, and AD conversion by the photometric circuit 102, and then added to the storage operation circuit 103. When the access to the unused memory of the storage unit 2 is completed, the terminal is output according to the output φ _{113 of the} circuit 113.
The output φ _101C of 101c is L at the timing shown in FIG. 10 (d).
Change from level to H level. While this output φ _101C is at the H level, the output of the photometry circuit 102 is stored in the circuit 103.
The circuit 103 calculates the aperture value and the charge accumulation time, that is, the exposure time, from which the appropriate exposure (charge accumulation amount) can be obtained from the stored light intensity value. Information on the appropriate aperture value is sent to the aperture control circuit 105, and the aperture 10a is controlled by a known method. Further, both the information of the proper aperture value and the proper charge accumulation time are sent to the display circuit 106, and the display element 107 displays the information in the viewfinder. Further, information on the proper charge storage time is also sent to the time counting circuit 104. Immediately after, the output phi _TG2 terminal 101d is changed from H level to L level at the timing shown in FIG. 10 (e), the transfer gate TG _{2 · 1} ~
TG _{2 · n} is closed. Receiving element a _{1 · 1} of the imaging device at the same _{time, ...,} a m · similar signal to the terminal 101a and the signal phi _TG2 with the accumulation of charge corresponding to the amount of exposure is started _n phi ₁₀₁ a (FIG. 10 ( e)) appears. Timing circuit 10
4 receives the signal φ ₁₀₁ a, changes its output φ ₁₀₄ from L level to H level as shown in FIG. 10 (f), and starts timing. Then, when the appropriate charge storage time has elapsed, the output φ ₁₀₄ changes from the H level to the L level.
The circuit 101 which receives this via the terminal 101b is the output terminal 101e.
The pulse φ _TG1 shown in FIG. 10 (g) is output,
Trump Fur gate TG _{1 · 1} ~TG _{1 · n} of the image pickup device 11
Open for a moment. As a result, the light receiving element a _{1, 1} ,
..., the charge accumulated in a _{m · n} is the vertical shift register
Move to Sv ₁ ~ Svn. The exposure is now complete. The charge accumulation time, that is, the exposure time is the transfer gate TG when the output φ _TG2 changes from H level to L level.
Is the time until the opening of the transfer gate TG _{1 · 1 ~TG 1 · n} from closure of _{2 ·} 1 _{~TG 2 · n} due to the pulse phi _TG1 is issued.

After the exposure is completed as described above, the signal φ is transferred from the terminal 101k to the selection gate 111 at the timing shown in FIG. 10 (h).
₁₀₁ k is emitted. Since the output from the terminal 101k is H level, the gate 111 selects the output (start signal) from the start signal generating circuit 112 and outputs it to the output terminal CO. In synchronism with this, a transfer pulse φ _CT as shown in FIG. 10 (m) is sent from the terminal 101q to the storage unit 2 via the terminals CT and MT, and the start signal is accessed via the input terminal MI. Sent to memory. Then, from the output terminals 101f and 101g, longitudinal transfer pulses φ _V1 and φ _V2 are output to the input terminals 11d and 11e of the image pickup device 11 of FIG. 5 at the timings shown in FIGS. 10 (i) and 10 (j), respectively. Lateral transfer pulses φh ₁ and φh ₂ are sent to the input terminals 11f and 11g from 101h and 101i at the timings shown in FIGS. As a result, the image signal of each light receiving element is output from the output terminal 11h in time series. This signal is converted into a digital signal by the AD conversion circuit 108 and applied to the selection gate 109. The gate 109 allows the image signal from the circuit 108 to pass because the switch 16c is off. Since the output from the terminal 101k becomes L level, the selection gate 111 also allows the image signal from the gate 109 to pass therethrough and is applied from the output terminal CO to the input terminal MI of the storage unit 2. Furthermore, the transfer pulses φ _V1 , φ
_The image signal is sequentially transferred into the memory matrix of the memory which is continuously accessed after the start signal by the transfer pulse φ _CT generated in synchronization with V ₂ , φh ₁ and φh ₂ . When the transfer of the image signal for one frame is completed, a start signal appears at the output terminal MO of the storage unit 2, and this is added to the detection circuit 113 via the input terminal CI of the image pickup unit 1. The circuit 113 detects this and stops the transfer pulses φ _V1 , φ _V2 , φh ₁ , φh ₂ , and φ _CT described above. This completes the shooting sequence for one frame. Then release button
Each time you press 15 deeply, the above-described shooting sequence can be repeated until there is no unused memory.

During the above shooting sequence, that is, the release button 15
From the pressing of the button to the exposure of the address search and the completion of the transfer, the signal φbu shown in FIG. 10 (n) is output from the output terminal 101s.
sy is emitted. The signal φbusy is generated by the sound generator 119 and the display device 1.
21 is driven to warn that the photographing sequence is in progress, and a safety device (not shown) is activated by exciting the electromagnet 123 to store the image signal from the image pickup unit 1 before the transfer to the storage unit 2 is completed. Makes it impossible to separate part 2. Next, use the mode selection lever 16 to manually access (MA
The case where N) is selected will be described.

In this case, the memory at the desired address can be manually accessed. When the lever 16 shown in FIG. 2 is moved to the MAN position, the switch 16a shown in FIG.
6b turns on, but switches 16c and 16d remain off. When the push button 17 is pressed in this state, the normally open switch 17a turns on.
Then, each time the button is pressed, a pulse is issued from the manual address setting circuit 115 one by one, whereby the content of the address counter 114 advances one by one from the address of the memory cell to which the image signal was transferred immediately before and the image signal was transferred. Therefore, it suffices to determine the memory of the desired address by looking at the display device 201 and operate the push button 17 until the desired address appears on the display device 18. Of course, when the memory used immediately before is desired, it is not necessary to push the push button 17. When the release button 15 is pressed after completing this manual access, there is no process of the address search described above, and instead a reset pulse is issued from the terminal 101r to the memory via the terminals CR and MR, and the accessed memory is already used. In this case, 4 bits of the start signal output to the memory are reset. Therefore, the accessed memory can be used because the output of the detection circuit 113 becomes H level regardless of whether it is used or not. In the subsequent sequence, the start signal and the image signal are transferred to the accessed memory as in the case where the lever 16 is at A. Therefore, according to the manual access mode,
Even if shooting fails, simply adjust the lever 16 to MAN and press the release button 15 deeply again, the failed image signal transferred to the memory will be replaced with the newly shot image signal, thus wasting memory. Can be used without. Further, by operating the push button 17, a desired memory can be used, for example, MC1, MC3, MC5, ... Manual access is performed cyclically. That is, when the push button 17 is pressed after the last address memory (MC20) is accessed, the first memory (MC1) is accessed. For example, if counter 114 is a programmable counter,
Switch 124 and pin 2 on the program input terminal (not shown)
This is because the storage capacity of the storage unit 2 due to 07 is digitalized and input, and when the total number of memories is counted, the contents of the counter are reset.

Next, the case where the multiple exposure mode is selected with the lever 16 will be described. First, the lever 16 is set to the MUL position after the shooting sequence is completed in either of the above two modes.
Then, the switch 16a is connected to the terminal M, and the switch 16a
b, 16c, 16d are all turned ON. Then, even if the release button 15 is pressed, there is no process of address search as in the case of the above-mentioned manual access mode, and the memory cell to which the image signal was immediately photographed and the image signal was transferred remains accessed.
Therefore, as in the case of the manual access mode, a reset pulse is output from the terminal 101r to reset the start signal of the memory that has been accessed. Next, the charge accumulation (exposure) process described above proceeds to the transfer process. Since the switch 16c is turned on here, the selection gate 109 outputs the output of the adder circuit 110 which is activated by turning on the switch 16d. Is selected to allow passage. First, when the start signal is transferred to the accessed memory as before, the adder circuit 110 inputs the image signal from the accessed memory cell input from the terminal CI and the image captured from the AD conversion circuit 108. The signal of the arithmetic mean with the signal is output. Of course, this is done under perfect synchronization of each transfer pulse. Then, this arithmetic mean signal is transferred to the accessed memory through the gates 109 and 111 and the terminals CO and MI. When the transfer of one frame is completed as described above, the accessed memory stores the image signal in which the first photographed subject and the second photographed subject are combined. This can be repeated multiple times as many times as desired, and there is no risk of overexposure because the arithmetic mean is taken instead of the sum each time. It is also possible to combine not only the memory used immediately before but also the image signal of the memory used previously by accessing the memory of the desired address with the push button 17.

The storage unit 2 that has been photographed in any of the above modes and has no unused memory is removed from the imaging unit 1 by operating the detachable slider 203 to pull it down. Then, the converter 3 transfers the image signal stored in the storage unit 2 to the magnetic tape cassette. For that purpose, the connector 206 of the storage unit 2 is connected to the connector 301, the tape cassette is loaded into the cassette holder 302, and the operation key board 303 is operated. Then, the image signals of the memory of the storage unit 2 are sequentially transferred to the magnetic tape, and the transferred memory is reset and can be reused. At this time, the converter 3 charges the secondary battery built in the storage unit 2 for backing up the memory and driving the display device 201.

The power supply system of the electronic camera system including the image pickup unit 1, the storage unit 2 and the converter 3 will be described in detail below.

FIG. 11 (a) shows a power supply battery E1 such as a manganese dry battery built in the image pickup unit 1, and FIG. 11 (b) shows a rechargeable power supply battery E2 such as a silver oxide secondary battery built in the storage unit 2. Each is shown in a cutaway view. In the state where the image pickup unit 1 and the storage unit 2 are separated as shown in FIG. 11, the image pickup unit 1 moves from the battery E1 to
The storage unit 2 is supplied with power from the battery E2, but when the storage unit 2 is attached to the imaging unit 1, the storage unit 2 is
Receives power from battery E1. This can minimize consumption of the battery E2 having a small electric capacity.

Figure 12 shows the power supply circuit system for that purpose. As is apparent from FIG. 12, when the storage unit 2 is attached to the image pickup unit 1, backup terminals CB and MB for the image pickup unit 1 and the storage unit 2 are attached.
Are connected. Therefore, the battery E1 supplies power to the circuit system 1a (see FIG. 8) of the image pickup unit 1 and also includes the memory MC and its peripheral circuits via the backup terminals CB and MB (see FIG. 6). Power supply). At this time, the P-channel enhancement MOSFET Q1 is turned off because a high level voltage is applied to the gate, and the battery E2 to the circuit system 2
The power supply path to a is cut off.

If the battery E1 is exhausted at this time and the voltage across its terminals is not sufficient to retain the contents stored in the memory MC, FETQ
FETQ1 is turned on because the gate voltage of 1 does not rise,
Power is supplied from the battery E2 to the memory circuit system 2a. Here, the diode D1 is for preventing the current from the battery E2 from flowing into the imaging unit 1 when the voltage of the battery E1 is low, and the capacitor C1 absorbs the voltage fluctuation of the battery E1 due to the load fluctuation, and It has a function of holding the power supply voltage so that the contents of the memory MC are not volatilized even if the power supply to the memory circuit system 2a is cut off for an extremely short time due to an accident.

When the storage unit 2 is removed from the image pickup unit 1, the terminals CB and MB are connected or disconnected. Therefore, the FET Q1 is turned on by the decrease of the gate voltage, and the battery E2 supplies power to the circuit system 2a instead of the battery E1.

The voltage detection circuit VD constantly detects the voltage of the battery E2,
When the voltage drops to the first level, an intermittent signal is sent to the detection circuit DP shown in FIG. 6 to blink the display device 201. This warns that the voltage of the battery ED has begun to drop. When the voltage of the battery E2 further drops and reaches the second level, the circuit VD sends an operation signal to the sounding device SD to generate a warning sound. As a result, the voltage of the battery E2 is
Warns you that you are approaching the minimum voltage required to hold the contents of. Further, the voltage detection circuit VD outputs the charge completion signal to the voltage detection end MV only when the voltage of the battery E2 is sufficient. A charging terminal MC for charging the battery E2 is connected to both ends of the battery E2.

FIG. 13 shows a circuit system of the converter 3.
The storage unit 2 is removed from the imaging unit 1 for image signal transfer, and the connector 206 of the storage unit 2 is connected to the connector 3 of the converter 3.
When connected to 01, each terminal MA, MO, MT, MR in FIG. 6 (b) of the storage unit 2 and each terminal MB, MC, MV in FIG.
Of the converter 3 terminals CvA, CvI, CvT, Cv
R, CvB, CvC, CvC are respectively connected. When this connection is completed, the power supply unit 304 of the converter 3 automatically connects to the terminal Cv.
Charging current is supplied to the battery E2 via C and MC to start charging. At the same time, the power supply unit 304 backs up the circuit system 2a via the terminals CvB and MB. Therefore, at this time, the FET Q1 is turned off, and the charging current from the terminal MC is prevented from flowing into the circuit system 2a.

FIG. 14 shows the internal structure of the power supply unit 304. AC input AC
Is reduced by transformer TR and rectified by full-wave rectifiers BR1, BR2, BR3. The output of the rectifier BR1 is smoothed by the capacitor C2 and supplied to each circuit of the converter 3. rectifier
The output of BR2 is smoothed by the capacitor C3 and sent to the backup terminal CvB, and the output of the rectifier BR3 is sent to the charging terminal CvC via the current limiting resistor R.

A large-capacity secondary battery may be built in the storage unit 2 to supply power to the circuit system 1a. In this case, the power supply circuit system when the image pickup unit 1 and the storage unit 2 are attached removes the battery E1 in FIG.
Connected to the terminal MC of. In that case, FETQ
1, two resistors connected to its gate, diode D1
Is removed because it is unnecessary and the lines connected to the source and drain of FET Q1 and the anode and cathode of diode D1 are short-circuited.

Now, returning to FIG. 13, the operation of the converter 3 for transferring an image signal from the storage unit 2 to the magnetic tape 305 according to the embodiment of the present invention will be described in detail. For the transfer, the converter 3 is appropriately selected from three operation modes: a search mode, an automatic transfer mode, and a manual transfer mode.
The search mode is a mode for selecting image signals stored in the memory of the storage unit 2 prior to image transfer, and the automatic transfer mode is for automatically transferring the image signals selected in the search mode to the tape in sequence. The manual transfer mode is a mode in which the image signals selected in the search mode are transferred to the tape in an arbitrary order.

First, the operation of the search mode will be described.

The magnetic tape 305 is loaded into the cassette holder 302 of the converter 3, and the search mode key on the key board 303 is pressed. Then, a signal is issued from the key board 303 to the control pulse generation circuit 306 to inform the circuit 306 that the search mode has been selected. Circuit 306 responds by sending a pulse to address counter 307. Then, the contents of the counter are incremented by one each time one pulse is input. As a result, the counter 307 sequentially accesses the memory in the storage unit 2 via the terminals CvA and MA. That is, the counter 307 is the circuit 306
Counting the first pulse from the first memory MC
When 1 is accessed and then the second pulse is counted, the second memory MC2 is accessed, and so on. Similarly, every time the pulse is counted, the last memory MC20 is accessed. The start signal detection circuit 308 receives the output signal of the memory accessed by the counter 307 via the terminals MO and CvI, and sends an H level signal to the circuit 306 if this is a start signal and an L level signal if not. In most cases, the memory 2 that has been newly mounted is normally used up in all the memories, so that the signal of the detection circuit 308 becomes the H level immediately after accessing the first memory MC1. Therefore, the first memory MC1 is accessed.

Then, the control pulse generation circuit 306 transmits the transfer pulse to the terminal Cv.
It is sent to the accessed memory MC1 of the storage unit 2 via T and MT. Therefore, the image number stored in the memory MC1 is read. At this time, the transfer pulse is repeatedly sent at a cycle of 1 frame every 1/30 second, and therefore the image signal is continuously sent to the signal synthesizing circuit 309 via the terminals MO and CvI. An index signal indicating the address of the memory being accessed from the address counter 307 is input to the circuit 309 together with this image signal. The circuit 309 synthesizes the image signal and the index signal and sends them to the selection gate 310. At this time, the gate 310 uses the control signal from the pulse generation circuit 306 to input the signal from the signal synthesis circuit 309 to the DA conversion circuit 3
It is set to send to 11. Therefore, the composite signal of the image signal and the index signal sent from the circuit 309 is sent to the NTSC conversion circuit 312 via the DA conversion circuit 311. The circuit 312 converts the composite signal into the NTSC system and sends it to the monitor 4 shown in FIG. 9 through the output terminal. On the monitor 4, the image signal stored in the memory MC1 is imaged, and the address of the memory MC1, that is, "1" is inserted and displayed on the image.

And if you're going to transfer this image, key board 303
Press the transfer key, and if you do not intend to transfer, press the reset key. When the transfer key is pressed, the key board 303 sends a signal to that effect to the control pulse generation circuit 306. In response to this, the circuit 306 sends a pulse to the address counter 307 to access the next used memory, and image the image signal stored in the memory and the address of the memory on the monitor 4 in the same manner as the above-mentioned operation. Turn into. If you press the reset key, the key board
A signal to that effect is sent from 303 to the control pulse generation circuit 306. In response to this, the circuit 306 sends a reset pulse to the memory MC1 via the terminals CvR and MR, and resets the start signal stored in the memory MC1. A pulse is then sent to the address counter 307 to access the next used memory for imaging on the monitor 4.

When the above operation is performed on all used memory,
A signal indicating the completion of the search operation is sent from the circuit 306 to the display device 313 to display that effect. Although information about the storage capacity of the storage unit 2 necessary for the determination, that is, information on the total number of memories is not shown, the amount of protrusion of the pin 207 implanted in the storage unit 2 is shown in FIG. It is obtained by detecting by the same means as above and transmitting to the circuit 306.

Next, the operation of the converter 3 when the automatic transfer mode is selected will be described.

When the automatic transfer mode key on the key board 303 is pressed, a signal is sent from the board 303 to the control pulse generation circuit 306 to notify that the mode has been selected. Circuit 306
In response to this, it sends a pulse to the address counter 307 to access the first memory where the start signal has not been reset, for example MC1, and at the same time transfer pulse to Cv.
The image signal stored in the memory MC1 is sent to the signal synthesizing circuit 309 via the T and MT. The circuit 309 synthesizes the index signal from the address counter 307 and the image signal and sends them to the selection gate 310. At this time, the gate 310 is set so that its output is sent to the buffer memory 314 by the control signal from the control pulse generating circuit 306. Therefore, the combined signal from the processing circuit 309 is
Sent to memory 314. The write control signal from the control pulse generation circuit 306 is sent to the memory 314, and the combined signal is written therein. The write control signal is issued in synchronization with the transfer pulse to the storage unit 2. When this writing is completed,
The control pulse generation circuit 306 repeatedly sends a control signal for reading to the buffer memory 314 at a cycle of 1 frame every 1/30 seconds. As a result, the composite signal stored in the buffer memory 314 is sent to the monitor 4 via the DA conversion circuit 311 and the NTSC conversion circuit 312. An image in which the image signal "1" of the memory MC1 is inserted appears on the monitor 4.

Upon completion of writing the composite signal to the buffer memory, the circuit 306 sends a control signal to the gate 310 and the composite circuit 30
The output of 9 is switched to be sent to the recording circuit 315, and the sending of the transfer pulse to the memory MC1 is stopped. The recording circuit 315 subjects the digital input signal to frequency modulation, amplification, etc., and sends it to the recording multi-head 315a. At the same time, the pulse generation circuit 306 sends a start signal to the motor drive circuit 316 to start the motor 317. When the rotation of the motor 317 reaches a steady state, the rotation of the motor is transmitted to the tape and the tape starts to rotate. At the same time, a transfer pulse having a relatively long cycle is sent from the pulse generation circuit 306 to the motor drive circuit 316 and the terminal CvT. Therefore, the image signal of the memory MC1 is read out at a relatively slow speed, and the signal synthesizing circuit 309, the selection gate 310, the recording circuit 315, and the recording multihead.
The data is recorded on the tape 305 through 315a (the head has four channels, but only one channel is shown for simplicity). At this time, the tape is speed-controlled by the transfer pulse.

At this time, since the index signal is not issued from the address counter 307 to the synthesizing circuit 309, the signal is not recorded on the tape.

When the transfer of the image signal to the tape 305 is completed, the terminals CvR, MR
A reset pulse is sent to the memory MC1 via the reset pulse and resets the start signal. Along with that, the motor drive circuit 316
The stop signal is sent to the motor and the motor stops.

Subsequently, the pulse generation circuit 306 sends a control signal to the selection gate 310 and outputs the output of the signal synthesis circuit 309 to the buffer memory 314.
Switch to send to. And address counter 307
To the next used memory, the image signal stored therein is imaged on the monitor 4 via the buffer memory by the same operation as described above, and the motor 317 is rotated to drive the tape. To record.

The above operation is repeated, the image signals of all the used memories are transferred to the tape 305, and their start signals are reset so that the pulse generating circuit 30 can be reused.
6 operates the display device 313 to display that the transfer is completed. At this time, if charging of the power supply battery E2 of the storage unit 2 is completed, the storage unit 2 is automatically detached from the converter 3. This is to receive a charge completion signal from the voltage detection circuit VD of the storage unit 2 at one input via the terminals MV and CvV, and to receive the transfer completion signal at the other input.
By providing the circuit 318, sending the output to the solenoid drive circuit 319 to operate the solenoid 320, and pressing the recording portion 2 in the detaching direction by the plunger of the solenoid.

The completion of writing one frame of the image signal to the buffer memory 314 and the tape 305 is detected by inputting the start signal of the memory accessed by the detection circuit 308 again.

Next, the operation when the manual transfer mode is selected will be described. When the manual transfer mode key on the key board 303 is pressed, a signal is sent from the board 303 to the pulse generation circuit 306 to notify that the manual transfer mode has been selected. Here, the desired used memory address is pressed with the ten-key pad of the key board 303. Then, a signal corresponding to that address is sent to the counter 307, and the counter 307 accesses the memory at that address. Then, similarly to the case of the automatic transfer mode, the image signal of the accessed memory is displayed on the monitor 4 together with its address number via the buffer memory 314, and the image signal is recorded on the tape 305. When the transfer to the tape is completed, a reset pulse is sent to the memory via the terminals CvR and MR, and the start signal is reset. Then, the display on the monitor 4 and the rotation of the tape are stopped.

And another used memory address on the keyboard
The numeric keypad 303 is pressed to access and the same operation as described above is performed.

The above operation is performed over all used memory,
The image signals stored in them are transferred to tape,
When the start signal is reset and becomes reusable, the display device 313 displays the transfer completion as described above. At this time, if the charging of the battery E2 of the storage unit 2 is also completed, the solenoid 320 operates and the storage unit 2 is detached from the converter 3.

When the image signal recorded on the tape 305 is to be reproduced on the motor 4, the reproduction key on the key board 303 is pressed. Then, the board 303 sends a signal to that effect to the pulse generation circuit 306. In response to this, the circuit 306 sends a motor start signal and a synchronization pulse to the motor drive circuit 316 to rotate the tape 305. An image signal for one frame recorded on the tape 305 is read out, a reproducing multi-head 321a, a reproducing circuit 321 for amplifying a signal from the head and demodulating into a digital signal, and a buffer memory via a selection gate 310.
Written in 314. When this writing is completed, the rotation of the tape 305 is stopped, the image signal stored in the buffer memory 314 is repeatedly read, and the DA conversion circuits 311 and N
It is imaged on the monitor 4 via the TSC conversion circuit.

At this time, the start signal detection circuit 308 detects that the transfer of one frame of the image signal from the tape 305 to the buffer memory 314 is completed by recording the start of the next image signal at the output of the reproduction circuit 321. By detecting the appearance of the start signal. (The wiring between the output terminal of the reproduction circuit 321 and the input terminal of the detection circuit 308 is not shown.) Before the image signal is transferred from the storage unit 2 to the tape 305, the date is operated by operating the key board 303. It is possible to send a data signal such as the above to the signal processing circuit 309, form a signal obtained by combining the image signal and data with a monitor, and record it on the tape 305.

Further, the DA conversion circuit is provided with an output terminal, and the terminal is connected to a device for converting an image signal converted into an analog signal into a hard copy. As is apparent from the above description, according to the present invention, when a manual operation for image transfer is applied, an image signal to be transferred is recorded by detecting the specific signal recorded on the first image recording medium. It is possible to shorten the time for searching the image recording area. In particular, in the present invention, when recording one screen of image signal corresponding to a subject image formed by the taking lens, a specific signal indicating whether or not the image signal to be stored in the image recording area is recorded Since the image is recorded in the specific signal recording area provided corresponding to each recording area, the image is recorded without manually selecting the transfer image after the image signal is recorded in the first image recording medium. The image signal can be read out only from the area and transferred to the second image recording medium. As described above, it is possible to eliminate the complexity of modifying the first image recording medium for image transfer, and to avoid unnecessary time for searching an unnecessary area.

[Brief description of drawings]

1 and 2 are perspective views of an electronic camera used in the present invention,
FIG. 3 is a perspective view showing a state in which the camera is separated into an image pickup section and a storage section, FIG. 4 is a schematic vertical sectional view of the camera, and FIG. 5 shows an internal structure of a solid-state image pickup element used in the present invention. Schematic diagram, FIG. 6 is a circuit diagram showing a part and the whole of the storage unit, FIG.
FIG. 8 is a front view showing a display section of a display device, FIG. 8 is a circuit diagram of an image pickup section, FIG. 9 is a perspective view of a converter and a monitor showing an embodiment of the present invention, and FIG. A time chart of main pulses for controlling the sequence, FIG. 11 is a cutaway view showing a power supply battery incorporated in each of the image pickup unit and the storage unit, FIG. 12 is a circuit diagram of the image pickup unit and the storage unit, and FIG. Shows a circuit diagram of the converter, and FIG. 14 shows a circuit diagram of the power supply unit of the converter. <Explanation of symbols of main parts> Image pickup device ... 11, internal storage device ... MC1 to MC20, power supply battery ... E2, electronic camera ... 1,2, external storage device ... 309, 315, 305, 317, 316, charging device ... 304, converter ... 3.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yutaka Ichihara 2-4-11-209 Susukino, Midori-ku, Yokohama-shi, Kanagawa (72) Inventor Akira Miyaji 4-16-11 Kaminoge, Setagaya-ku, Tokyo (56) References JP-A-50-87743 (JP, A) JP-A-54-156701 (JP, A) JP-A-47-32722 (JP, A) JP-A-48-43521 (JP, A) JP-A-57-29045 (JP, A) Actually developed 52-118615 (JP, U)

Claims (2)

[Claims] 1. A plurality of image recording areas in which image signals for one screen corresponding to a subject image formed by a photographing lens are respectively recorded, and the image recording areas are provided corresponding to each of the image recording areas. A first image recording medium having a plurality of specific signal recording areas in which a specific signal indicating whether or not the image signal to be stored in the image recording area is recorded when the image signal is recorded in the area And a second image recording medium capable of recording image signals for a plurality of screens, and when a manual operation for image transfer is applied, the specific signal recorded in the first image recording medium is detected, and the detection is performed. When it is determined that the image signal is recorded, the image recording area corresponding to the specific signal area is automatically searched, and when it is determined that the image signal is not recorded, the specific signal area is determined. Image corresponding to The recording area has an automatic searching unit that does not search, and a transfer unit that reads the image signal from the image recording area searched by the automatic searching unit and transfers the read image signal to the second image recording medium for recording. An image transfer device characterized by the above. 2. The specific signal, upon recording at the time of shooting, detects the presence or absence of an image based on the specific signal prior to recording, and can record the detected image signal in an unrecorded area. The image transfer apparatus according to claim 1, wherein the image transfer apparatus is also used as a control signal for setting the above.