JPH07122050A - Video tape recorder - Google Patents

Abstract

PURPOSE:To eliminate an operator's labor to make operation by automatically changing over a mode to a VTR even if the mode is set at a television and scramble broadcasting is received by the television and the VTR. CONSTITUTION:Switches 26, 28 and 30 are connected to terminals 26c, 28c and 30c by a high-level signal F outputted from a logic circuit 24 in accordance with a signal B and a signal A at the time of changeover and a signal E rises to a high level when the receiving channel of the VTR 10 is changed over from ordinary broadcasting to the scramble broadcasting during televiewing of the scramble broadcasting by the television 20. The scramble broadcasting signals outputted from a tuner 32 are descrambled by a decoder 22. The signal A outputted from the decoder 22 is then inputted to the logic circuit 24 and the descrambled TV signal into a video signal processing circuit 34. The signal D of a high level is outputted from the logic circuit 24 and the descramble TV signal from the video signal processing circuit 34 is inputted to the television 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder, and more particularly to a video tape recorder including a first output terminal for a first control signal, a first input terminal for a television signal (TV signal) and a second output terminal. A first terminal portion connected to a television receiving a TV signal when receiving a first level first control signal; a second input terminal for a second control signal; a third input terminal for a video signal; and a third output terminal The present invention relates to a video tape recorder including a second terminal unit and a tuner connected to a decoder that receives a scrambled broadcast signal and outputs a descramble TV signal and a second control signal of a first level.

[0002]

2. Description of the Related Art A descrambler (descrambler) is required to receive a scrambled broadcast. Here, when the device that receives the scrambled broadcast is only one television, the television and the decoder may be directly connected, but the video tape recorder (hereinafter, "VTR") also receives the scrambled broadcast and transmits it on the television. If you want to watch, you have to change the connection between the decoder and the TV and video tape recorder as needed.

Therefore, the conventional VTR 10 shown in FIG.
Was configured as follows. That is, VTR1
0 includes 21 pin terminals 12 and 14 and cable 16
It is connected to the television 20 and the decoder 22 via 18 and 18. The logic circuit 24 is connected to the 8th pin 12a of the 21st pin terminal 12, the terminal 26a of the switch 26 is connected to the 19th pin 12b, and the terminal 28b of the switch 28 is connected to the 20th pin 12c. The 8th pin 14a of the 21-pin terminal 14 is connected to the logic circuit 24,
The 19th pin 14b is connected to the terminal 28a of the switch 28, and the 20th pin 14c is connected to the terminal 26c of the switch 26 and the terminal 30c of the switch 30. Switch 2
The terminal 28c of 8 and the terminal 30b of the switch 30 are connected to the tuner 32, and the terminal 26c of the switch 26 and the terminal 30a of the switch 30 are connected to the video signal processing circuit 34. Then, the system controller 36 controls the logic circuit 24, the switches 26, 28 and 30, and the tuner 32.

The switches 28 and 30 are connected to the terminal 28b when the tuner 32 does not receive a scrambled broadcast.
And 30b, and when receiving a scrambled broadcast, they are connected to terminals 28c and 30c. The switch 26 is connected to the terminal 26b when the mode is the television 20, and is connected to the terminal 26c when the mode is the VTR 10. Further, the 21-pin terminals 12 and 14 are terminals used for connecting video equipment in Europe, and control signals are input / output via the 8th pins 12a and 14a, and via the 19th pins 12b and 14b. The video signal is output, and the video signal is input via the 20th pins 12c and 14c. TV 20 is pin 1
When the control signal output from 2a is high level, the input is switched to the VTR 10 side, and when the descramble signal is input from the decoder 22 via the 20th pin 14c, the control signal input from the 8th pin 14a is changed. High level.

As shown in FIG. 13, the logic circuit 24 is an AN.
The D circuit 24a, the OR circuit 24b, and the buffer 24c are included, and the control signal A input from the eighth pin 14a and the signal B output from the syscon 36 are input to the AND circuit 24a. In addition, the output of the AND circuit 24a and the signal C output from the syscon 36 are the OR circuit 2
4b and the output of the OR circuit 24b is input to the buffer 24
It is output as a signal D via c. The signal B is V
A signal that becomes low level when TR10 uses the decoder 22 and becomes high level when not using the decoder 22,
The signal C is a signal which becomes high level when the mode is switched to the VTR 10 and when reproducing a video tape (not shown), and becomes low level at other times.
The system controller 36 switches processing under the control of the remote controller 38.

[0006]

[Table 1]

Referring to Table 1, when the mode is set to the television 20 and the normal broadcast is received by the tuner 32 of the VTR 10 and the television 20 ((1)), the high level signal B from the syscon 36 to the logic circuit 24 is received. And a low-level signal C are output, and the switches 26, 28 and 3 are
0 is connected to terminals 26b, 28b and 30b, respectively. Therefore, the 20th pin 12 of the 21st pin terminal 12
A normal video signal from c is input to the decoder 22 via the switch 28 and the 19th pin 14b of the 21st pin terminal 14. Therefore, the video signal that has not been processed from the decoder 22 is the 20th pin 1 of the 21st pin terminal 14.
The low level control signal A is input to the VTR 10 via the 4c and is transferred to the VTR 10 via the 8th pin 14a.
Input to TR10. Of these, control signal A
Is input to the logic circuit 24, and the video signal is output from the 19th pin 12b of the 21st pin terminal 12 via the switch 26. The signal D output from the logic circuit 24 becomes a low level, and the television 20 does not switch the input to the VTR 10 side. Therefore, the video signal is not input to the television 20,
The TV 20 outputs an internally processed normal broadcast. The video signal received by the tuner 32 is input to the video signal processing circuit 34 via the switch 30,
Although output from this circuit 34, the switch 26 has a terminal 2
Since it is connected to 6b, it is not output from the 19th pin 12b of the 21st pin terminal 12.

In this state, when the mode is switched to the VTR 10 side by the remote controller 38 ((2)), the switch 26 is connected to the terminal 26c and the signal C becomes high level. Therefore, the video signal output from the video signal processing circuit 34 is output from the 19th pin 12b of the 21st pin terminal 12, the high level signal D is output from the logic circuit 24, and the 8th pin 12a is output. TV 20
Entered in. Therefore, the video signal output from the 19th pin 12b is input to the television 20, and the video based on this video signal is output from the television 20.

The mode is set to the TV 20, and the TV 2
Receives scrambled broadcast with 0 and VTR10
When the normal broadcast is received by the tuner 32 ((3)), the high level signal B and the low level signal C are output from the syscon 36 to the logic circuit 24, and the switches 26, 28 and 30 are respectively connected to terminals. 26b, 28b and 30b are connected. Therefore, the scramble signal is input from the television 20 to the decoder 22, the high-level control signal A is input from the decoder 22 to the logic circuit 24, and the descramble signal is output from the 19th pin 12b of the 21-pin terminal 12. . on the other hand,
Since the signal D output from the logic circuit 24 has a high level, the television 20 switches the input to the VTR 10 side, whereby the descramble signal is input to the television 20. As a result, the scrambled broadcast is output from the television 20.

In this state, when the mode is switched to the VTR 10 side ((4)), the switch 26 is connected to the terminal 26c and the signal C becomes high level. Then, the video signal input from the tuner 32 to the video signal processing circuit 34 is transferred to the 19-pin of the 21-pin terminal 12 via the switch 26.
It is output from the pin 12b. Since the signal D output from the logic circuit 24 has a high level, the television 20 outputs a normal broadcast.

The mode is set to the TV 20 and the TV 2
When the normal broadcast is received at 0 and the scrambled broadcast is received at the VTR 10 ((5)), the signals B and C output from the syscon 36 are both at the low level, the switch 26 is connected to the terminal 26b, and the switch 28 is connected. And 30 are connected to terminals 28c and 30c, respectively. Therefore, the scramble signal input from the tuner 32 is input to the decoder 22, and the descramble signal released by the decoder 22 and the high-level control signal A are input to the video signal processing circuit 34 and the logic circuit 24, respectively. . The descramble signal is also output from the 19th pin 12b of the 21st pin terminal 12 via the switch 26. However, since the signal D is at the low level, the descramble signal is not input to the TV 20, and the normal broadcast is output from the TV 20.

When the mode is switched to the VTR 10 side in this state ((6)), the signal C becomes high level and the switch 2
6 is connected to the terminal 26c. Therefore, the signal D becomes high level, the descramble signal output from the video signal processing circuit 34 is input to the television 20, and the television 2
A scrambled broadcast is output from 0. When the mode is set to the television 20 and the scrambled broadcast is received by the television 20 and the VTR 10 ((7)), the signals B and C both become low level, the switches 28 and 30 are connected to the terminals 28c and 30c, and the switch 26 Is terminal 2
6b is connected. Therefore, the scrambled signal input from the tuner 32 is descrambled by the decoder 22, the descrambled signal is input to the video signal processing circuit 34, and the descrambled signal is input to the video signal processing circuit 34 through the switch 26.
It is output from the 19th pin 12b of the 1-pin terminal 12. Further, the high-level control signal A is input to the logic circuit 24. Since the signal D output from the logic circuit 24 becomes low level, the descramble signal is not input to the television 20, and the scrambled broadcast received by the television 20 itself is not descrambled and output from the television 20. To be done.

In this state, when the mode is switched to the VTR 10 side ((8)), the signal C becomes high level and
The switch 26 is connected to the terminal 26c. Therefore, the signal D becomes high level, the descramble signal output from the video signal processing release 34 is input to the television 20, and the descrambled scrambled broadcast is output from the television 20.

[0014]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In R10, the mode is set to TV 20 and TV 2
While watching the scrambled broadcast at 0, if the reception channel of the VTR 10 is switched from the normal broadcast to the scrambled broadcast in order to record the scrambled broadcast, the TV 20 outputs the scrambled video. Therefore, in order for the user to watch the scrambled broadcast, the mode is set to VT by the remote controller 38.
There is a problem that it is necessary to switch to the R10 side, and it takes time to operate the VTR 10.

Therefore, a main object of the present invention is to provide a VTR which is easy to operate.

[0016]

The present invention receives a first control signal of a first level including a first output terminal for a first control signal and a first input terminal and a second output terminal for a television signal. When descrambled by receiving a scrambled broadcast signal, including a first terminal portion connected to a television receiving a television signal, a second input terminal for the second control signal, a third input terminal and a third output terminal for the television signal In a video tape recorder having a tuner and a second terminal section connected to a decoder for outputting a signal and a second control signal of the first level, when the television and the tuner receive the scrambled broadcast, the scrambled broadcast signal received by the tuner is transmitted. It outputs to the decoder through the third output terminal, and outputs the first level second control signal from the decoder through the second input terminal. Then, the first control signal of the first level is output to the television through the first output terminal, and the descramble television signal input from the decoder through the third input terminal is output to the television through the second output terminal. It is a video tape recorder characterized by being output.

[0017]

When the mode is set to the television and the scrambled broadcast is being viewed on the television, if the VTR reception channel is switched from the normal broadcast to the scrambled broadcast channel, the scrambled broadcast signal received by the tuner by, for example, Syscon, is output to the decoder. To be done. For this reason,
A descramble TV signal and, for example, a high-level second control signal are input from the decoder to the VTR. This second control signal is input to the syscon and descrambled TV
The signal is output to the television from the second output terminal for the TV signal. The syscon first outputs, for example, a high-level first control signal based on the second control signal from the decoder.
The descramble TV signal is input to the television by outputting it from the output terminal to the television. That is, the mode is switched from the television to the VTR.

[0018]

According to the present invention, when the scrambled broadcast is received by the television and the scrambled broadcast is received by the video tape recorder while the scrambled broadcast is being output, the mode is automatically switched to the VTR side. It is possible to save the user the trouble of operating the VTR.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the following embodiments with reference to the drawings.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a VTR 10 of this embodiment.
Has substantially the same configuration as the conventional VTR 10 shown in FIG. 12, so only different points will be described, and description of the same points will be omitted. The logic circuit 24 has signals A and B
In addition to the input, a signal E that is high level when the mode is VTR 10 and is low level when the mode is television 20 and a signal G that is high level when playing a video tape (not shown) are input. Logic circuit 2
The control signal F is input from 4 to the syscon 36. As shown in FIG. 2, the logic circuit 24 includes an AND circuit 40, to which the signals A and B are input. Signal A is also D-
The signal B is input to the D terminal of the flip-flop circuit 42.
Is directly input to the R terminal of the circuit 42, and is also input to the CL terminal via the inverter 44. Then, the signal F is output from the Q terminal of the circuit 42. In addition, Q
A low level signal is output from the terminal when the R terminal input is at high level, and when the R terminal input is at low level,
The D terminal input is output when the CL terminal input rises from the low level to the high level. The inverter 4
Since 4 is provided, a slight time difference occurs between the R terminal input and the CL terminal input, so when the signal B falls, the CL terminal input goes high after the R terminal input goes low. It becomes a level. Therefore, the D-flip-flop circuit 42 operates as desired. The signals E and G are input to the OR circuit 46, and the output of the OR circuit 46 and the output of the AND circuit 40 are input to the OR circuit 48. Then, the output of the OR circuit 48 is output as the signal D through the buffer 50.

The syscon 36 basically performs the same processing as that of the VTR 10 shown in FIG. 12, but performs the processing shown in FIGS. 3 and 4 according to the output level of the signal B. That is, in step S1, it is determined whether or not the signal B is at the high level. If the signal B is at the high level, the flag 36a included in the system controller 36 is reset in step S3 and the process returns. If the signal B is at low level in step S1, it is determined in step S5 whether the flag 36a is set. Then, if it is set, the process returns. If not, the signal F is read in step S7, and the switches 28 and 30 are connected to the terminals 28c and 30c in step S15.
Connect to. Subsequently, in step S11, it is determined whether or not the signal F is at a high level. If the signal F is at a low level, the process returns, but if it is at a high level, the mode is switched to the VTR 10 in step S13, and then the process returns.

FIG. 4 shows a subroutine for mode switching in step S13. Here, first, step S
In step 1, the flag 36a is set, and then step S3
At the front panel (not shown) VTR display,
Then, in step S5, the switch 26 is connected to the terminal 26c.
Switch to. After that, in step S7, the signal E is set to the high level and the process returns.

[0023]

[Table 2]

In operation, referring to Table 2, when the mode is set to VTR 10 and the VTR 10 and the television 20 are receiving the normal broadcast ((1)), the high-level signal B is sent to the logic circuit 24. Since it is input, the signal F becomes low level. Further, low-level signals E and G are both input to the logic circuit 24. On the other hand, switch 2
8, 30 and 26 are connected to terminals 28b, 30b and 26b, respectively. Therefore, the video signal input from the television 20 through the 20th pin 12c of the 21st pin terminal 12 is output to the decoder 22 through the 19th pin 14b of the 21st pin terminal 14. Here, since the video signal is not scrambled, the low-level control signal A and the unprocessed video signal from the decoder 22 are 21-pin terminals 14 respectively.
8th pin 14a and 20th pin 14c to VTR1
Input to 0. Then, the signal A is input to the logic circuit 24, and the video signal is the 19th pin 12b of the 21st pin terminal 12.
Is output from.

A low level signal D is output from the logic circuit 24 and input to the television 20 through the eighth pin 12a of the 21-pin terminal 12, so that the television 20 inputs VT.
The video signal output from the 19th pin 12b is not input to the television 20 without switching to the R10 side. Therefore,
The television 20 outputs a normal broadcast processed internally. The video signal received by the tuner 32 at this time is input to the video signal processing circuit 34 via the switch 30.

When the mode is switched to the VTR 10 in this state ((2)), the signal E becomes high level and the switch 26 is switched to the terminal 26c. Therefore, the high-level signal D is output from the logic circuit 24, and the television 2
The video signal output from the video signal processing circuit 34 is input to 0. As a result, the television 20 outputs an image based on this image signal.

The mode is set to the TV 20 and the TV 2
When the scrambled broadcast is received at 0 and the normal broadcast is received at the VTR 10 ((3)), the signal B output from the syscon 36 becomes high level, and thus the signal F becomes low level. Further, the signals E and G both become low level. Switches 28, 30 and 26 are connected to terminals 28b, 30b and 26b, respectively. Therefore, the scramble signal input from the television 20 to the VTR 10 is input to the decoder 22, and the decoder 22 descrambles the signal. Therefore, the decoder 22 outputs the high-level control signal A and the descramble signal, of which the control signal A is input to the logic circuit 24. Further, a descramble signal is output from the 19th pin 12b of the 21st pin terminal 12. As a result, the signal D becomes high level, and the television 20 receives the descramble signal output from the VTR 10 and outputs it.

In this state, when the mode is switched to the VTR 10 ((4)), the signal E becomes high level and the switch 2
6 is connected to the terminal 26c. Therefore, the signal D becomes high level, and the video signal of the normal broadcast received by the tuner 32 is transmitted via the video signal processing circuit 34 to the television 20.
Entered in. As a result, the normal broadcast is output from the television 20.

The mode is set to the TV 20 and the TV 20
If the reception channel of the VTR 10 is switched from the normal broadcast to the scramble broadcast while receiving the normal broadcast at ((5)), the low level signal B is input from the syscon 36 to the logic circuit 24, and the signal B The signal F becomes low level by the signal A (low level) when the signal B becomes low level. The syscon 36 reads this signal F and switches the switches 28 and 30 to the terminals 28c and 30c. The above-described processing from when the signal B becomes low level to when the switches 28 and 30 are switched is performed in steps S1, S5, S7 and S9 shown in FIG.
Is based on. Since the signal F is at low level, it is returned. Logic circuit 2 from syscon 36
Also, low-level signals E and G are both input to 4. On the other hand, when the switches 28 and 30 are switched, the scramble signal received by the tuner 32 is input to the decoder 22, the descramble signal output from the decoder 22 is input to the video signal processing circuit 34, and a 21-pin terminal is provided. 12 pin number 12
It is output from b. Further, the high-level control signal A is input to the logic circuit 24. This gives the signal D
Becomes a low level, the descramble signal is not input to the television 20, and the television 20 outputs a normal broadcast.

When the mode is switched to the VTR 10 in this state ((6)), the switch 26 is connected to the terminal 26c,
The signal E becomes high level. This signal E causes signal D
Becomes a high level, the descramble signal output from the video signal processing circuit 34 is output to the switches 26 and 2.
The television 20 through the 19th pin 12b of the 1-pin terminal 12
, And the scrambled video is output from the television 20.

It should be noted that the mode is set to the television and the receiving channel of the VTR 10 is switched from the regular broadcast to the scramble broadcast while the television 10 is receiving the scramble broadcast ((7)). . At this time, the signal B becomes low level, and the signal F becomes high level based on this signal B and the high level signal A input to the logic circuit 24 at this time. The syscon 36 reads this signal F and then switches 28 and 30 to terminal 2
Switch to 8c and 30c. Then, the flag 36a
Is set, VTR is displayed on the front panel, and the switch 26 is switched to the terminal 26c. Then, the signal E is set to the high level. After outputting the above signal B, signal E
Is performed in accordance with steps S1, S5, S7, S9, S11 and S13 shown in FIG. 3 and steps S1 to S7 shown in FIG. Therefore, the scrambled signal received by the tuner 32 is descrambled by the decoder 22, the high-level signal A is input to the logic circuit 24, and the descrambled signal is input via the video signal processing circuit 34 to the 21-pin terminal 12 It is output from the No. 19 pin 12b. Syscon 36
Also, a low-level signal G is input to the logic circuit 24, and a signal D is generated by these signals A, B, E, and G.
Becomes high level. Therefore, the descramble signal is input to the television 20, and the descrambled video is output from the television 20. The flag 36a is
Once set, the VTR 10 will continue to be set unless the scrambled broadcast is stopped, so the mode is V
After the switching to TR10, the processes after step S7 are not performed.

The mode is set to VTR10 and the television 1
Even if the receiving channel of the VTR is switched to the scrambled broadcast ((8)) while the scrambled broadcast is received at 0 and the normal broadcast is received at the VTR 10, it is processed according to FIG. 3 and FIG. 4 as described above. It However,
Since the mode is set to the VTR 10 side, the switch 26 and the signal E do not change at all.

Since the VTR 10 of the other embodiment shown in FIG. 5 has substantially the same configuration as the VTR 10 shown in FIG. 1, only different points will be described and similar points will be omitted. The signal C is input from the system controller 36 to the logic circuit instead of the signals E and G. The signal C is a signal which becomes high level when the mode is switched to the VTR 10 and when the video tape is reproduced as in the prior art, and the signals E and G are combined into one in the OR mode. . That is, the signal C is the OR gate 4 of FIG.
It is equivalent to the output of 6. However, as can be seen from FIG. 6, since this signal C is directly input to the OR circuit 48,
The input of the OR circuit 48 is the same as in the prior art. As can be seen from FIGS. 7 and 8, the processing in the syscon 36 is the same as that of the VTR 10 shown in FIG. 1 except that the signal C is set to the high level in step S7 of FIG. In addition, the connection states of the switches 26, 28 and 30 and the signals A, B, according to the specification mode of the VTR 10,
The output states of C, D and F are shown in Table 3. Since the signal E and G are grouped together to form the signal C, the operation is the same as in Table 2, and detailed description thereof is omitted.

[0034]

[Table 3]

Referring to FIG. 9, a VTR of another embodiment.
Since 10 is also almost the same as the VTR 10 shown in FIG. 1, only different points will be described and the same points will be omitted. The signal A output from the decoder 22 is input to the syscon 36. The system controller 36 switches the switches 26, 28 and 30 in accordance with the specifications of the television 20 and the VTR 10, and further outputs the signal D based on the signal A.

The syscon 36 is basically processed so as to operate similarly to the VTR 10 shown in FIG.
When R10 selects the scrambled broadcast channel,
The ciscon 36 is processed according to FIGS. That is, it is determined in step S1 whether or not the scrambled broadcast channel is selected, and if "NO", the flag 36a is reset in step S3 and the process returns. On the other hand, if "YES" in the step S1, it is determined whether or not the flag 36a is set in the step S5. Then, if it is set, the process returns. If not, the signal A is read in step S7, and then the switches 28 and 30 are connected to the terminals 28c and 30c in step S9. Then, in step S11, it is determined whether or not the signal A is at the high level. If the signal is at the low level, the signal D is set to the low level in step S13 and the process returns. To do. Step S1
5, the process is performed as shown in FIG. That is, first, the flag 36a is set in step S1, and then the VTR is displayed on the front panel in step S3.
Display. Then, in step S5, the switch 26
Is switched to the terminal 26c, and then the signal D is set to high level in step S7.

[0037]

[Table 4]

In operation, referring to Table 4, when the mode is set to the television 20 and the ordinary broadcast is received by the television 20 and the VTR 10 ((1)), the switches 26 and 28 are used.
And 30 are connected to terminals 26b, 28b and 30b. Therefore, the video signal is input from the television 20 to the decoder 22, but the low-level signal A and the normal video signal are output from the decoder 22. Of these signals, the signal A is input to the syscon 36, whereby the low level signal D is output from the syscon 36. Also, the video signal is output from the 19th pin 12b of the 21-pin terminal 12 via the switch 26, but since the signal D is at a low level, the video signal is not input to the television 20 and the television 20
Outputs a normal image processed internally.

When the mode is switched to the VTR 10 in this state ((2)), the switch 26 is connected to the terminal 26c.
Therefore, the video signal received by the tuner 32 and input to the video signal processing circuit 34 is output from the 19th pin 12b of the 21st pin terminal 12 via the switch 26.
On the other hand, since the high-level signal D is output from the system controller 36, the video signal is input to the television 20,
An image based on this image signal is output from 0.

The mode is set to the TV 20 and the TV 2
When the scrambled broadcast is received at 0 and the normal broadcast is received at the VTR 10 ((3)), the switches 26, 28 and 30 are connected to 26b, 28b and 30b, respectively. Therefore, the scramble signal output from the television 20 is input to the decoder 22, and the decoder 22 outputs the high-level signal A and the descramble signal. Then, the syscon 36 outputs the high-level signal D based on the signal A, and the descramble signal output from the decoder 22 is input to the television 20. Therefore, the descrambled video is output from the television 20.

When the mode is switched to the VTR 10 ((4)), the switch 26 is connected to the terminal 26c. Therefore, the video signal processing circuit 3 received by the tuner 32 is received.
The video signal input to 4 is transmitted via switch 26 to 21
It is output from the 19th pin 12b of the pin terminal. On the other hand, since the signal D output from the syscon 36 is at a high level, the television 20 outputs a normal image.

The mode is switched to the TV 20 and the TV 2
When the reception channel of the VTR 10 is switched from the normal broadcast to the scrambled broadcast while receiving the normal broadcast at 0, the syscon 36 reads the signal A (low level) input to the syscon at the time of switching and also switches 28 and 30. To terminals 28c and 30c.
The switch 26 remains connected to the terminal 26b. Then, the low-level signal D is output. The above-described processing from channel switching to signal D output is performed in steps S1, S5, S7, S9, S11 and S13 of FIG.
Is done according to. The scrambled signal received by the tuner 32 is descrambled by the decoder 22, the high-level signal A is input to the syscon 36, and the descrambled signal is converted into the video signal processing circuit 34.
Entered in. Also, the descramble signal is sent to switch 2.
It is output from the 19th pin 12b of the 21-pin terminal 12 via 6. However, the signal D output from the syscon 36
Is low level, the descramble signal is not input to the television 20, and the television 20 outputs the normal broadcast received by itself.

When the mode is switched to the VTR 10 ((6)), the switch 26 is connected to the terminal 26c, and the syscon 36 outputs the high-level signal D. Therefore, the descramble signal output from the video signal processing circuit 34 is input to the television 20, and the television 20 outputs the descrambled video. It should be noted that the mode is set to the television 20 and the reception channel of the VTR 10 is switched from the regular broadcast to the scrambled broadcast while the television 20 is receiving the scrambled broadcast ((7)). In this case, the signal A output from the decoder 22 at the time of switching the channel is read into the syscon 36, and then the switches 28 and 30 are connected to the terminals 28c and 30c. Then, the flag 36a is set and the VTR display is made on the front panel. Further, the switch 26 is connected to the terminal 26c, and the signal D becomes high level. The processing from the above channel switching to the output of the signal D is performed according to the flow charts shown in FIGS. Therefore, the scrambled signal received by the tuner 32 is the decoder 2
It is canceled at 2, and the descramble signal is output from the 19th pin 12b of the 21st pin terminal 12 via the video signal processing circuit 34. Since the signal D is at the high level, the television 20 outputs the video that has been descrambled. As described in the operation of the embodiment of FIG. 1, the flag 36a, once set, remains set unless the VTR 10 stops the scramble broadcast. Note that when the reception channel of the VTR 10 is switched from the normal broadcast to the scramble broadcast ((8)) with the mode set to the VTR 10 from the beginning ((8)), the same operation as in the above is performed.
0 and FIG. 11, the switch 26 is connected to the terminal 26c and the signal D is at a high level, so that the connection and the output are not changed.

According to these embodiments, when the receiving channel of the VTR 10 is switched to the scrambled broadcast while watching the scrambled broadcast on the television 20, the mode is automatically set to the VTR 10 side, so Can save the trouble of switching the mode. Therefore, it is particularly significant when the recording of the scrambled broadcast is started while watching the scrambled broadcast on the television 20.

Although only video signals have been described in these embodiments, the present invention can be applied to audio signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of the embodiment shown in FIG.

FIG. 3 is a flowchart showing a part of the operation of FIG. 1 embodiment.

FIG. 4 is a flowchart showing a part of the operation of FIG. 1 embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a part of the embodiment shown in FIG. 5;

FIG. 7 is a flowchart showing a part of the operation of FIG. 5 embodiment.

FIG. 8 is a flowchart showing a part of the operation of FIG. 5 embodiment.

FIG. 9 is a block diagram showing another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a part of the embodiment shown in FIG. 9;

FIG. 11 is a flowchart showing a part of the operation of the embodiment in FIG. 9;

FIG. 12 is a block diagram showing a conventional technique.

13 is a circuit diagram showing a part of the conventional technique shown in FIG.

[Explanation of symbols]

 10 ... Video tape recorder 12, 14 ... 21 pin terminal 20 ... Television 22 ... Decoder 24 ... Logic circuit 26, 28, 30 ... Switch 32 ... Tuner 34 ... Video signal processing circuit 36 ... Syscon

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[Procedure amendment]

[Submission date] December 20, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The syscon 36 basically performs the same processing as that of the VTR 10 shown in FIG. 12, but performs the processing shown in FIGS. 3 and 4 according to the output level of the signal B. That is, in step S1, it is determined whether or not the signal B is at the high level. If the signal B is at the high level, the flag 36a included in the system controller 36 is reset in step S3 and the process returns. If the signal B is at low level in step S1, it is determined in step S5 whether the flag 36a is set. Then, although the return if set, read the signal F at step S7 if it is not set, connects the switch 28 and 30 to the terminals 28c and 30c in step S 9. Subsequently, in step S11, it is determined whether or not the signal F is at a high level. If the signal F is at a low level, the process returns, but if it is at a high level, the mode is switched to the VTR 10 in step S13, and then the process returns.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

In operation, referring to Table 2, set the mode
Since the high level signal B is input to the logic circuit 24 when the VTR 10 and the television 20 are receiving the normal broadcast ((1)), the signal F is at the low level. Further, low-level signals E and G are both input to the logic circuit 24. On the other hand, switch 2
8, 30 and 26 are connected to terminals 28b, 30b and 26b, respectively. Therefore, the video signal input from the television 20 through the 20th pin 12c of the 21st pin terminal 12 is output to the decoder 22 through the 19th pin 14b of the 21st pin terminal 14. Here, since the video signal is not scrambled, the low-level control signal A and the unprocessed video signal from the decoder 22 are 21-pin terminals 14 respectively.
8th pin 14a and 20th pin 14c to VTR1
Input to 0. Then, the signal A is input to the logic circuit 24, and the video signal is the 19th pin 12b of the 21st pin terminal 12.
Is output from.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The syscon 36 basically has the configuration shown in FIGS.
Is processed to operate in the same manner as VTR10 shown in any of FIG. 12, when the VTR10 selects a scrambled broadcast channel, the system controller 36 thus processes in FIGS. 10 and 1 1. That is, it is determined in step S1 whether or not the scrambled broadcast channel is selected. If “NO”, the flag 36 is set in step S3.
Reset a and return. On the other hand, if "YES" in the step S1, it is determined whether or not the flag 36a is set in the step S5. And
If it is set, the process returns. If it is not set, the signal A is read in step S7, and then the switches 28 and 30 are connected to the terminal 28 in step S9.
Connect to c and 30c. Then, in step S11, it is determined whether or not the signal A is at the high level. If the signal is at the low level, the signal D is set to the low level in step S13 and the process returns. To do. In step S15, processing is performed as shown in FIG. That is, first, the flag 36a is set in step S1, and then the VTR display is performed on the front panel in step S3. Subsequently, the switch 26 is switched to the terminal 26c in step S5, and then the signal D is set to the high level in step S7.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 10

[Correction method] Change

[Correction content]

FIG. 10 is a flowchart showing a part of the embodiment in FIG. 9;

Claims (1)

[Claims] 1. A first control signal including a first output terminal for a first control signal, a first input terminal for a television signal, and a second output terminal for a television signal.
A first terminal portion connected to a television for receiving a television signal when receiving the first control signal of a level, a second input terminal for a second control signal, a third input terminal for a television signal, and a third output terminal A video tape recorder comprising a tuner and a second terminal connected to a decoder for receiving a scrambled broadcast signal and outputting a descramble television signal and the second control signal of the first level, the television and the tuner Receives a scrambled broadcast, outputs the scrambled broadcast signal received by the tuner to the decoder via the third output terminal, and outputs the scrambled broadcast signal of the first level from the decoder via the second input terminal. The first control signal of the first level is forwarded via the first output terminal based on the second control signal. The video is characterized in that the descrambled television signal output from the decoder through the third input terminal is output to the television through the second output terminal. Tape recorder.