JPH07120747B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit with greatly improved integration density.

(B) Conventional Technology As semiconductor integrated circuits have advanced in performance and functionality, high integration has become a very important point.

For example, the structure and manufacturing method of the bipolar transistor are described in detail in "Latest LSI Process Technology" Industrial Research Group (issued April 25, 1984).

This bipolar transistor (1) has a P
An N type epitaxial layer (3) is laminated on the semiconductor substrate (2) of the type, and an N ⁺ type buried layer (4) is formed between the semiconductor substrate (2) and the epitaxial layer (3). ing.

Around the buried layer (4), there is a P ⁺ -type isolation region ( 5 ) which reaches the semiconductor substrate (2) from the surface of the epitaxial layer (3). This separation area ( 5 )
May be diffused all at once from the surface of the epitaxial layer, or may be diffused by a vertical separation method as shown in FIG.

Further, the isolation region ( 5 ) forms an island (6) made of the epitaxial layer (3), and the island (6) serves as an N-type collector region. Further, the P type base region (7) formed in the island (6), the N ⁺ type emitter region (8) formed in the base region (7), and the epitaxial layer serving as the collector are formed. There is a collector contact region (9) formed in the exposed region, and there are respective electrodes formed through the contact holes of the SiO ₂ film formed on the epitaxial layer (3).

Next, a method of manufacturing this bipolar transistor (1) will be described. First, a SiO ₂ film is formed on a P-type semiconductor substrate (2), a diffusion hole of an embedding layer (4) is formed in this SiO ₂ film, and antimony is added to the semiconductor substrate (2) through the diffusion hole. There is a first step to diffuse into.

Here, in the case of FIG. 2, since the separation region ( 5 ) is achieved by upper and lower separation, boron is diffused into the semiconductor substrate (2) through a diffusion hole, and the P ⁺ -type lower diffusion layer is formed. (1
0) is also formed.

Next, an epitaxial layer (3) is laminated on the surface of the semiconductor substrate (2), and a SiO ₂ film is formed on this epitaxial layer (3). In this SiO ₂ film, a diffusion hole in the upper diffusion region (11) of the separation region ( 5 ) is formed by applying a photoresist film, mask alignment, exposure, etching, etc., and boron is diffused through this diffusion hole. There is a second step in which the isolation region ( 5 ) is formed.

Then, a diffusion hole of the base region (7) is formed in the SiO ₂ film again by applying a photoresist film, mask alignment, exposure, etching, etc., and boron is diffused through the diffusion hole to form a base region (7). There is a third step of forming 7).

Further, diffusion holes of the emitter region (8) and the collector contact region (9) are formed in the SiO ₂ film by applying a photoresist film again, mask alignment, exposure, etching, etc., and arsenic is diffused through the diffusion holes. Then, there is a fourth step of forming the emitter region (8) and the collector contact region (9).

Finally, contact holes for the emitter region (8), the base region (7) and the collector contact region (9) are formed in the SiO ₂ film again by applying a photoresist film, aligning the mask, exposing and etching. For example Al
There is a fifth step of forming each electrode by vapor deposition.

(C) Problems to be Solved by the Invention By the above-described third step, the thermal oxide film formed on the base region (7) is formed to be thinner than the thermal oxide film on the collector region (6). It Due to this difference in film thickness, the following problem arises when the fourth step of simultaneously forming the diffusion hole, the base contact and the collector contact (9) in the emitter region (8) is performed.

The first problem is that when the fourth step is carried out by a wet method, the collector contact (9) is completely removed, and the diffusion hole and the base contact hole in the emitter region (8) are larger than expected sizes. is there.

The second problem is that when the fourth step is performed by dry etching, the collector contact (9) is completely removed.
That is, the epitaxial layer (3) in the emitter region (8) and the base contact region is vertically etched.

Therefore, the former makes it difficult to reduce the cell size, and the latter reduces the cell yield.

On the other hand, in order to solve this problem, there is a method of removing all the thermal oxide film on the epitaxial layer (3) and forming a CVD film from the outside. However, since the SiO ₂ film and the epitaxial layer are difficult to chemically bond with each other and are unstable, there is a problem that a leak current is likely to occur on the surface of the epitaxial layer.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a thermal oxide film sequentially formed on a semiconductor layer and a silicon oxide film externally deposited on the semiconductor layer of a transistor element. The problem is solved by making the insulating film of (1) substantially the same thickness.

(E) Action When a thermal oxide film is provided between the semiconductor layer and the silicon oxide film deposited from the outside, contamination from the outside is prevented, the surface of the semiconductor layer is stabilized, and the occurrence of leak current can be prevented. This is because the thermal oxide film and the semiconductor layer are chemically bonded.

(F) Example A method for manufacturing a semiconductor integrated circuit according to an example of the present invention will be described in detail below.

First, for convenience of description, the overall configuration will be described using FIG. 1J. As shown in FIG. 1J, there is a P-type silicon semiconductor substrate (21), and an N-type epitaxial layer (22) is provided on this semiconductor substrate (21). This epitaxial layer (2
A plurality of N ⁺ type buried layers (23) are provided between the semiconductor substrate (21) and the semiconductor substrate (21), and the buried layers (23) are surrounded and the epitaxial layer is formed from above and below to the upper diffusion region (24). There is an upper and lower separation region (26) for diffusing and separating the lower diffusion region (25). Therefore, a plurality of islands are formed by the upper and lower isolation regions (26).

Within the first island, the epitaxial layer (22)
There is a transistor (29) consisting of a collector region, a base region (27) and an emitter region (28). Second
In the island, there is a MOS capacitor element (30), there is a lower layer electrode region (31) on the surface of the epitaxial layer (22), and a dielectric layer (32) and an upper layer electrode (33) are formed thereon. A diffusion resistance (34) is present in the third island, and a diffusion resistance region (35) and contact regions (36) at both ends thereof are formed on the surface of the epitaxial layer (22).

Furthermore, on the epitaxial layer (22), a thermal oxide film (37) of about 400 to 1000 Å formed by light oxidation is formed.
And a film sequentially formed on the thermal oxide film (37) from the outside, for example, a non-doped SiO ₂ film (38) by CVD and a phosphorus-doped SiO ₂ film (39) by CVD.

This structure is a feature of the present invention. Since the epitaxial layer (22) is chemically engaged with the thermal oxide film (37), the surface of the epitaxial layer (22) is structurally stable. ing. Therefore, the leak current can be suppressed.

First, as shown in FIG. 1A, a thermal oxide film is formed on the surface of a P-type silicon semiconductor substrate (21) having an impurity concentration of about 10 ¹⁵ atom / cm ³ , and then an N ⁺ -type buried layer (23) is planned to be formed. After etching the region, N-type impurities such as antimony and arsenic are doped through this opening.

Subsequently, as shown in FIG. 1B, a thermal oxide film is formed on the region where the lower diffusion region (25) of the P ⁺ type upper and lower isolation regions (26) is to be formed, and P type impurities are opened through this opening. Is doped with boron.

Next, as shown in FIG. 1C, after removing all the thermal oxide film on the semiconductor substrate (21), a specific resistance of about 0.5 to 5 Ω · cm is formed on the semiconductor substrate (21) by a known vapor phase growth method. The N type epitaxial layer (22) is formed with a thickness of about 2 to 8 μm. At this time, the previously doped impurities are slightly diffused up and down.

Next, a thermal oxide film (40) is formed on the surface of the epitaxial layer (22) by thermal oxidation at a temperature of about 1000 ° C. for several hours, and then the entire semiconductor substrate is heat treated again to remove impurities previously doped. Redistribute.

Therefore, the lower diffusion region (25) is upwardly diffused up to about half or more of the epitaxial layer (22).

In addition, the thermal oxide film on the surface of the epitaxial layer (22) grows to a thickness of several thousand Å by this process, and this thermal oxide film (40)
Indicates a function similar to that of the mask described later. However, instead of the thermal oxide film, for example, a silicon nitride film or the like may be used as the diffusion mask, or the silicon oxide film may be formed by the CVD method.

Further, if the epitaxial layer thickness is about half or less as compared with the conventional one, the amount of heat treatment to diffuse can be reduced, so that the lateral spread can be reduced.

Subsequently, as shown in FIG. 1D, the silicon oxide film (40) on the lower electrode region (31) of the intended MOS capacitor element (30) is removed, and a ring lath, for example, is formed on the entire surface. After that, heat treatment is performed at a predetermined temperature for a predetermined time to diffuse phosphorus into the epitaxial layer (22). Then, the ring lath is removed with a predetermined etching solution, and heat treatment is performed again so as to reach a predetermined depth.

Subsequently, as shown in FIG. 1E, the upper diffusion region (24) of the planned upper and lower isolation regions (26), the planned base region (27), and the planned diffusion resistance (34) correspond to the silicon oxide film (4).
There is a step of forming the introduction holes (41), (42) and (43) of the impurity in (0).

Here, the positive resist film is used as a mask and is formed by dry etching. After this, the epitaxial layer (2
The exposed area of 2) is dummy-oxidized to form a dummy oxide film. This dummy oxide film reduces damage to the epitaxial layer (22) due to the subsequent ion implantation step,
It is also used to randomly disperse the implanted ions to make them uniform.

Subsequently, as shown in FIG. 1F, a mask (44) is provided in the predetermined base region and the introduction holes (42) and (43) on the diffusion resistors (27) and (34) to diffuse impurities and An upper diffusion region (24) is formed.

Here, after covering the entire surface with a resist film capable of blocking implantation ions, that is, a so-called mask (44), the mask (44) corresponding to the upper diffusion region (24) is removed, and a P-type impurity of poron is removed. Implantation is performed under predetermined conditions to form the upper diffusion region (24).

In this step, even if the opening of the mask (44) is formed larger than the introduction hole (41) of the silicon oxide film (40) as shown in the figure, since the silicon oxide film (40) acts as a mask, the introduction hole ( 41) and the upper diffusion region (24) are formed at the same position.

After that, the mask (44) is removed and a predetermined heat treatment is performed so that the upper diffusion region (24) reaches the lower diffusion region (25) as shown in FIG. 1G.

Then, as shown in FIG. 1G, all of the introduction holes (41), (4
Impurities are diffused from (2) and (43) to form the base region (2
7) and the step of forming the diffusion resistance region (35).

Here, the mask (44) is all removed in the previous step, and the introduction holes (41), (42), (43) of the upper diffusion region (24), the base region (27) and the diffusion resistance region (35) are removed. Exposed. In this state, boron (B) is ion-implanted.

Therefore, the base region (27) is formed, and at the same time, the diffusion resistance region (35) is formed. At the same time, the upper diffusion area (2
Impurities are diffused again in 4).

As shown in FIG. 1F, the formation position of the separation region (26) is determined by simply providing a mask in the introduction hole (42) and the diffusion resistance region (35) of the base region (27). It can be determined by the hole (41). Further, as shown in FIG. 1G, the base region (27) is determined by the introduction hole (42) of the base region (27) formed in advance without using the step of providing the mask.
Therefore, there is no need to worry about misalignment of mask formation or misalignment of the introduction hole in the base region. As shown in FIG. 1E, once the introduction holes (41), (42) and (43) are formed with high precision, the formation positions of the diffusion regions (24), (27) and (35) with this precision are formed. Can be realized.

Moreover, since the ion diffusion is performed by ion implantation, the lateral spread of each diffusion region can be minimized as compared with thermal diffusion. Further, by making the diffusion depth of the base region (27) shallower than that of the conventional one, it is possible to prevent further spread in the lateral direction.

In the step of FIG. 1G, the diffusion was performed without forming the mask, but the mask is provided in the introduction hole (41) on the isolation region (26) of the present application, and then impurities are diffused to form the base region (27). May be diffused.

As described with reference to FIG. 1F, the opening of the mask corresponding to the base region (27) and the diffusion resistance (34) is made slightly larger than the introduction holes (42) and (43), and the base is accurately measured. The area (27) and the diffusion resistance (34) can be determined. Here, the mask can prevent excessive impurities from being implanted into the isolation region (24).

Subsequently, as shown in FIG. 1H, the region corresponding to the base contact region (45) to be formed in the base region (27), the isolation region (26), and the contact region (36) of the diffusion resistance region (35) are formed. There is a step of forming a photoresist film (46) serving as a mask so as to be opened.

Then, there is a step of implanting boron (B) ions.

Subsequently, as shown in FIG. 1I, there is a step of removing the photoresist film (46) and the silicon oxide film (40) and then making the insulating film on the surface of the epitaxial layer (22) substantially the same over the entire surface. .

This step is a step which is a feature of the present invention, and a collector hole (48), a base hole (49) and an emitter hole (50) which will be described later.
If the insulating film is formed to have substantially the same film thickness before the step of opening the holes, the collector hole (48), the base hole (49), and the emitter hole (50) may end the etching at the same time. it can.

This is because, for example, in the case of dry etching, if the silicon oxide film shown in FIG.
Since the silicon oxide film on 8) is thinner than the silicon oxide film on the planned collector contact region (51), it is necessary to completely open the introduction hole of the collector contact region (51).
The epitaxial layer that will become the emitter region (28) is etched. Therefore, as described above, the silicon oxide film is re-formed to substantially eliminate the film thickness difference and prevent the epitaxial layer in the emitter region (28) from being etched.

As a method, after removing the photoresist film (46),
Substantially all of the silicon oxide film (40) is removed by a wet process, and the silicon oxide film (here, the thermal oxide film (37),
It is composed of a non-doped and phosphorus-doped two-layer structure SiO ₂ film by the CVD method for gettering. However, the CVD film may be only phosphorus-doped. ) There is a method of reattaching.

Therefore, even if etching is performed with a wet etching solution that does not etch silicon, the etching will end at the same time.
Does not increase. Further, since the dry etching that also etches silicon is finished at the same time, the etching of the silicon that becomes the emitter region (28) is eliminated, and the yield of characteristics can be improved. Moreover, the thermal oxide film (37) and the epitaxial layer (22) are deposited by the CVD method.
Formed between the iO ₂ films (38) and (39), the epitaxial layer can prevent contamination from the outside, so that the thermal oxide film (37) and the epitaxial layer (22) are chemically bonded. . Therefore, when forming the transistor, the formation of the thermal oxide film (37) can prevent the generation of leak current on the surface of the epitaxial layer (22). Further, as shown in FIG. 1I, a negative photoresist film is used to form a silicon oxide film (3) on which a dielectric thin film (32) intended for a MOS capacitor element (30) is formed.
There is a step of removing 7), (38) and (39) to form a dielectric thin film (32). Here, this silicon oxide film is opened by wet etching, and several hundred liters of silicon nitride film (32) is formed on the entire surface. Then, chemical dry etching is performed as shown in the figure.

Finally, a photoresist film is formed on the entire surface, and by anisotropic etching, a planned emitter region (28), a planned collector contact region (51), a planned lower layer electrode (31) contact region (52), and a diffusion resistance. Silicon oxide films (37), (38), (39) on the contact region (36) of the region (35)
Removed, collector hole (48), base hole (49), emitter hole (50), MOS capacitor element (30) and diffusion resistance (34)
Contact holes (52) and (36) are formed. Then, after removing the photoresist film, the epitaxial layer corresponding to the intended emitter region (28), the intended collector contact region (51) and the contact region (52) of the lower electrode region (31) is exposed again. Forming a photoresist film.

Then, using this photoresist film as a mask, arsenic (As)
Are ion-implanted to form a contact region (52) of the emitter region (28), the collector contact region (51) and the lower electrode region (31).

Then, the resist film is removed, heat treatment is performed to diffuse the emitter region (28) downward, and then light etching is performed to form an aluminum electrode as shown in FIG. 1J.

(G) Effect of the Invention As is apparent from the above description, the surface of the epitaxial layer is re-attached by reattaching the film of the three-layer structure of the thermal oxide film, the non-doped silicon oxide film, and the phosphorus-doped silicon oxide film. Si with substantially the same film thickness as a whole
An O ₂ film is formed. Therefore, even if the silicon oxide film corresponding to the emitter region or the collector contact region is etched by wet or dry etching, the etching is completed substantially at the same time, so that the etching of the epitaxial layer and the enlargement of the opening can be prevented.

Moreover, since the thermal oxide film is formed, contamination from the outside can be eliminated, and when a transistor is formed, the generation of leak current can be prevented.

As described above, by adopting the method of forming the introduction hole at a time,
The occupied area between the isolation region and the base region can be reduced, the transistor size can be reduced, and etching of the emitter region and generation of leakage current can be prevented, so that a more stable transistor can be provided.

[Brief description of drawings]

1A to 1J are sectional views showing a method for manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor integrated circuit.

Claims (4)

[Claims] 1. A step of forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of the same conductivity type in which an impurity of one conductivity type is doped in a portion corresponding to the isolation region below the isolation region to be formed, Heat-treating the epitaxial layer to diffuse impurities in the lower isolation region so as to occupy more than half of the thickness of the epitaxial layer, and use this step to grow an oxide film provided in the epitaxial layer, or A step of forming a first insulating film by a step of reattaching a silicon oxide film or a silicon nitride film separately, and a step of forming a first insulating film on the epitaxial layer, A step of simultaneously forming an impurity introduction port in the insulating film corresponding to the isolation region, and selecting from the planned upper isolation region and the planned base region introduction port. Then, a step of ion-implanting impurities into the planned upper isolation region and the planned base region, and removing the first insulating film over the entire surface, so that the substantially entire film thickness is made uniform over the entire surface. Forming a second insulating film made of a silicon oxide film on the epitaxial layer; removing a part of the second insulating film to expose the collector hole exposing the epitaxial layer and the base region. Forming the base hole and the emitter hole, introducing impurities into the base region through the emitter hole and diffusing the emitter region, and making ohmic contact with the collector region, the base region and the emitter region. And a step of forming a collector electrode, a base electrode and an emitter electrode through the collector hole, the base hole and the emitter hole. The method of manufacturing a semiconductor integrated circuit, comprising. 2. In the step of removing the first insulating film and forming the second insulating film so that the film thickness is substantially uniform over the entire surface, the second insulating film is formed. Thermal oxide film, non-doped silicon oxide film by CVD method and CVD
2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the method comprises a phosphorus-doped silicon oxide film formed by the method. 3. In the step of removing the first insulating film and forming the second insulating film so that the film thickness of the substantially entire surface becomes uniform over the entire surface, the second insulating film comprises: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising a thermal oxide film and a phosphorus-doped silicon oxide film formed by a CVD method. 4. The semiconductor integrated circuit device according to claim 1, wherein in the step of introducing the impurity into the predetermined base region, a mask is provided in the introduction hole on the isolation region to diffuse the impurity. Production method.