JPH07120707B2 - Microwave integrated circuit - Google Patents

Microwave integrated circuit

Info

Publication number
JPH07120707B2
JPH07120707B2 JP62003274A JP327487A JPH07120707B2 JP H07120707 B2 JPH07120707 B2 JP H07120707B2 JP 62003274 A JP62003274 A JP 62003274A JP 327487 A JP327487 A JP 327487A JP H07120707 B2 JPH07120707 B2 JP H07120707B2
Authority
JP
Japan
Prior art keywords
line
input
signal line
output
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62003274A
Other languages
Japanese (ja)
Other versions
JPS63172447A (en
Inventor
克彦 荒木
治彦 加藤
栄一 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62003274A priority Critical patent/JPH07120707B2/en
Publication of JPS63172447A publication Critical patent/JPS63172447A/en
Publication of JPH07120707B2 publication Critical patent/JPH07120707B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路の配線用線路に関し、特にそ
の外部漏洩電磁界の低減に関するものである。
Description: TECHNICAL FIELD The present invention relates to a wiring line for a semiconductor integrated circuit, and more particularly to reducing an external leakage electromagnetic field.

〔従来の技術〕[Conventional technology]

従来のこの種の線路としては、半導体基板裏面に形成し
た導体と半導体基板上に形成した導体とで構成されるマ
イクロストリップ線路が用いられている。この線路の周
辺には電磁界が漏洩するため、回路を集積化して線路同
士の間隔が狭くなった場合あるいは線路同士が交差する
場合に線路同士の結合が生じ、信号が漏洩するという欠
点があった。特にマイクロ波帯の高い周波数を用いるマ
イクロ波集積回路では大きな問題であった。
As a conventional line of this type, a microstrip line composed of a conductor formed on the back surface of a semiconductor substrate and a conductor formed on a semiconductor substrate is used. Since the electromagnetic field leaks around this line, there is a drawback that the lines are coupled and the signal leaks when the distance between the lines is narrowed by integrating the circuits or when the lines cross each other. It was In particular, this is a big problem in microwave integrated circuits that use high frequencies in the microwave band.

以上の点について、m×nマトリクススイッチ回路を例
にあげて説明する。従来のこの種のm×n(1≦m,1≦
n)マトリクススイッチ回路を第5図に示す。
The above points will be described by taking an m × n matrix switch circuit as an example. This type of conventional m × n (1 ≤ m, 1 ≤
n) The matrix switch circuit is shown in FIG.

第5図において、入力端子IT1〜ITmにそれぞれ入力信号
線IL1〜ILmの一端が接続され、出力端子OT1〜OTnに出力
信号線OL1〜OLnの一端がそれぞれ接続されている。ま
た、入力信号線IL1〜ILmと出力信号線OL1〜OLnとは互い
に交差部Cij(i=1,2,・・・,m、j=1,2,・・・,n)
で交差され、これら各交差部にそれぞれ1入力1出力ス
イッチSijが設けられ、信号合成器Mijがその点における
各出力信号線OLjに挿入される。さらに、入力信号線IL1
〜ILmおよび出力信号線OL1〜OLnの各他端は、終端抵抗I
R1〜IRmおよびOR1〜ORnに接続されている。第5図にお
いて、入力信号線IL1〜ILm,出力信号線OL1〜OLnの構造
はマイクロストリップ線路構造である。
In FIG. 5, input terminals IT1 to ITm are respectively connected to one ends of input signal lines IL1 to ILm, and output terminals OT1 to OTn are respectively connected to one ends of output signal lines OL1 to OLn. Further, the input signal lines IL1 to ILm and the output signal lines OL1 to OLn intersect with each other at intersections Cij (i = 1,2, ..., m, j = 1,2, ..., n).
, And one-input one-output switch Sij is provided at each of these intersections, and a signal synthesizer Mij is inserted in each output signal line OLj at that point. In addition, input signal line IL1
~ ILm and the other end of each of the output signal lines OL1 to OLn are connected to a terminating resistor I
Connected to R1-IRm and OR1-ORn. In FIG. 5, the structure of the input signal lines IL1 to ILm and the output signal lines OL1 to OLn is a microstrip line structure.

交差部Cijの例を第6図に示す。同図においては、マイ
クロストリップ線路としての入力信号線ILと出力信号線
OLとをエアブリッジ1で交差させている。このマイクロ
ストリップ線路同士の交差部分において、入力信号線IL
と出力信号線OLとの間で信号の結合が生じる。このこと
に関し、例えば「電子通信学会昭和59年度総合全国大会
S9−1」において、1CHzの周波数において40dB程度によ
り結合を少なくすることは困難であると報告されてい
る。
An example of the intersection Cij is shown in FIG. In the figure, the input signal line IL and the output signal line as the microstrip line
The OL is crossed by Air Bridge 1. At the intersection of these microstrip lines, input signal line IL
Signal coupling occurs between the output signal line OL and the output signal line OL. In this regard, for example, "The Institute of Electronics and Communication Engineers 1984 General National Convention
S9-1 ”, it is reported that it is difficult to reduce the coupling by about 40 dB at the frequency of 1 CHz.

第5図において、1入力1出力スイッチSkl(1≦k≦
m,1≦l≦n)をオン状態にすると、入力端子ITkに入力
された信号は、入力信号線ILk,1入力1出力スイッチSK
l,信号合成器Mkl,出力信号線OLlおよび信号合成器Mpl
(p=k+1,k+2,・・・,m)を通って出力端子のOTlに
出力される。同様にして任意の入力端子と出力端子との
間を結合することがでかる。1入力1出力スイッチSij
のオンオフ比としては、例えば1GHzの周波数において50
dB以上のものが作製できる。
In FIG. 5, one-input one-output switch Skl (1≤k≤
When m, 1 ≦ l ≦ n) is turned on, the signal input to the input terminal ITk is input signal line ILk, 1 input 1 output switch SK
l, signal synthesizer Mkl, output signal line OLl and signal synthesizer Mpl
It is output to OTl of the output terminal through (p = k + 1, k + 2, ..., M). Similarly, an arbitrary input terminal and output terminal can be connected. 1 input 1 output switch Sij
The on / off ratio of is, for example, 50 at a frequency of 1 GHz.
It is possible to manufacture products with dB or higher.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかし、1入力1出力スイッチSijのオンオフ比をいく
ら高くとるようにしても、交差部Cijから不要な信号が
漏れ込み、出力端子OTjにおけるオンオフ比を高くする
のは困難であった。例えば1入力1出力スイッチS11,S2
1,・・・,Sm1がオフ状態のとき、出力端子OT1には、上
記1入力1出力スイッチS11,S21,・・・,Sm1からの漏洩
信号に加えて、交差部C11,C21,・・・,Cm1からの漏洩信
号が加算されて出力される。
However, no matter how high the ON / OFF ratio of the 1-input 1-output switch Sij is set, it is difficult to increase the ON / OFF ratio at the output terminal OTj because an unnecessary signal leaks from the intersection Cij. For example, 1-input 1-output switch S11, S2
1, ..., When Sm1 is in the off state, the output terminal OT1 has, in addition to the leakage signal from the 1-input 1-output switch S11, S21, ..., Sm1, the intersection C11, C21 ,.・, Leakage signal from Cm1 is added and output.

このため、高いオンオフ比を有するマトリクススイッチ
回路をモノリシックICで実現することができなかった。
また、その他のマイクロ波集積回路においても、線路間
の漏洩があるため高い利得を有する増幅回路の作製が困
難であったり、線路同士の接近や交差ができないためレ
イアウトに制限が生じ、高集積化ができない場合やICが
構成できない場合があるなどの欠点があった。
Therefore, a matrix switch circuit having a high on / off ratio cannot be realized by a monolithic IC.
Also in other microwave integrated circuits, it is difficult to fabricate an amplifier circuit having high gain due to leakage between lines, and layout is restricted because lines cannot approach or intersect each other, resulting in high integration. However, there are some drawbacks such as not being able to do it and sometimes not being able to configure the IC.

本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、線路同士を接近あるいは交差し
ても信号漏洩が少ない線路を提供することにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a line with little signal leakage even when the lines approach or intersect each other.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、マトリクススイッチ回路を構成し、入力線が
1入力1出力スイッチを介して出力線に接続されている
マイクロ波集積回路において、中心導体が誘電体を介し
て電導性壁で囲まれた金属被覆線路を半導体基板上に形
成し、入力線および出力線からなる信号線路又は直流バ
イアス用線路の全部または一部をその金属被覆線路で構
成し、信号線路又は直流バイアス用線路がクロスする部
分では、いずれか一方のみが電導性壁で囲まれているよ
うにしたものである。
The present invention relates to a microwave integrated circuit which constitutes a matrix switch circuit and in which an input line is connected to an output line via a 1-input 1-output switch, and a central conductor is surrounded by a conductive wall via a dielectric. A metal-covered line is formed on a semiconductor substrate, and a signal line or a DC bias line consisting of an input line and an output line is wholly or partially composed of the metal-covered line, and the signal line or the DC bias line crosses. Then, only one of them is surrounded by a conductive wall.

〔作用〕[Action]

本発明に係わる線路においては、線路の接近・交差によ
る信号漏洩が少ない。
In the line according to the present invention, there is little signal leakage due to the approach and intersection of the lines.

〔実施例〕〔Example〕

第1図は、本発明に係わる集積回路の一実施例を示す回
路図である。第1図において、A1〜Amは金属被覆線路を
構成する導電性壁であり、同図において第5図と同一部
分又は相当部分には同一符号が付してある。
FIG. 1 is a circuit diagram showing an embodiment of an integrated circuit according to the present invention. In FIG. 1, A1 to Am are conductive walls forming a metallized line, and in FIG. 1, the same or corresponding portions as those in FIG. 5 are designated by the same reference numerals.

第1図に示すように、入力信号線IL1〜ILmの周囲をそれ
ぞれ導電性壁A1〜Amで囲み、導電性壁A1〜Amの両端をそ
れぞれ接地する。
As shown in FIG. 1, the input signal lines IL1 to ILm are surrounded by conductive walls A1 to Am, and both ends of the conductive walls A1 to Am are grounded.

入力信号線ILi(i=1,2,・・・,m)と導電性壁Aiの構
成例を第2図に示す。第2図は断面図であり、入力信号
線ILiは紙面に垂直に延びている。
FIG. 2 shows a configuration example of the input signal line ILi (i = 1, 2, ..., M) and the conductive wall Ai. FIG. 2 is a sectional view, and the input signal line ILi extends perpendicularly to the paper surface.

次に、第2図に示す金属被覆線路の作製手順について説
明する。まず、シリコン基板2に第1の導体配線層であ
る底面用導電性壁Ai1を作製し、次に第1の誘電体層で
あるポリイミド等の誘電体層3aを作製し、その上に第2
の導体配線層である入力信号線ILiを作製する。次に、
第2の誘電体層3bを作製し、第3の導体配線層である側
面および上面用導電性壁Ai2で誘電体層3a,3bを囲む。こ
のとき、導電性壁Ai1とAi2を電気的に結合させる。
Next, a procedure for manufacturing the metal-covered line shown in FIG. 2 will be described. First, the bottom conductive wall Ai1 that is the first conductor wiring layer is formed on the silicon substrate 2, then the dielectric layer 3a such as polyimide that is the first dielectric layer is formed, and the second dielectric layer 3a is formed on the dielectric layer 3a.
The input signal line ILi which is the conductor wiring layer of is manufactured. next,
The second dielectric layer 3b is produced, and the dielectric layers 3a and 3b are surrounded by the conductive walls Ai2 for the side surface and the upper surface which are the third conductor wiring layer. At this time, the conductive walls Ai1 and Ai2 are electrically coupled.

第1図で示した交差部Cij(i=1,2,・・・,m、j=1,
2,・・・,n)の例を第3図に示す。第3図は断面図であ
る。同図において、入力信号線ILiは紙面に垂直に、出
力信号線OLjは紙面に平行に延びている。作製手順は、
シリコン基板2上に絶縁用の誘電体層3cおよび出力信号
線OLjを作製し、出力信号線OLjの上に絶縁用の誘電体層
3dを挟んで導電性壁Ai,誘電体層3e,入力信号線ILiを作
製する。このような構造になっているため、入力信号線
ILiに流れる信号のエネルギーのほとんど大部分は導電
性壁Aiで囲まれた領域に閉じ込められて伝送される。こ
のため、入力信号線ILiと出力信号線OLjとの電磁界結合
を、従来のマイクロストリップ線路同士の交差の場合と
比べて大幅に減少させることができ、高オンオフ比を有
する1入力1出力スイッチを使用することにより、モノ
リシックマトリクススイッチ回路のオンオフ比を高くす
ることができる。
The intersection Cij shown in FIG. 1 (i = 1,2, ..., m, j = 1,
An example of 2, ..., N) is shown in FIG. FIG. 3 is a sectional view. In the figure, the input signal line ILi extends perpendicularly to the paper surface, and the output signal line OLj extends parallel to the paper surface. The manufacturing procedure is
An insulating dielectric layer 3c and an output signal line OLj are formed on the silicon substrate 2, and an insulating dielectric layer is formed on the output signal line OLj.
The conductive wall Ai, the dielectric layer 3e, and the input signal line ILi are manufactured with the 3d in between. Due to this structure, the input signal line
Most of the energy of the signal flowing through ILi is confined and transmitted in the region surrounded by the conductive wall Ai. Therefore, the electromagnetic field coupling between the input signal line ILi and the output signal line OLj can be significantly reduced as compared with the case where the conventional microstrip lines cross each other, and the 1-input 1-output switch having a high on / off ratio is provided. Is used, the on / off ratio of the monolithic matrix switch circuit can be increased.

上記実施例においては、入力信号線のかわりに出力信号
線を金属被覆線路としてもよい。また、入力信号線と出
力信号線の両者を金属被覆線路としてもよい。
In the above embodiment, the output signal line may be a metal covered line instead of the input signal line. Further, both the input signal line and the output signal line may be metal-coated lines.

入力信号線と出力信号線の両者を金属被覆線路とした場
合の交差部の構成例を第4図に示す。第4図はその交差
部の断面図であり、入力信号線ILiは紙面に垂直に、出
力信号線OLjは紙面に平行に延びている。シリコン基板
2上において、絶縁用の誘電体層3を間に挟み、出力信
号線OLjおよび出力信号線用導電性壁4j,入力信号線ILi
および入力信号線用導電性壁Aiを作製する。
FIG. 4 shows an example of the structure of the intersection where both the input signal line and the output signal line are metal-coated lines. FIG. 4 is a cross-sectional view of the intersection, in which the input signal line ILi extends perpendicular to the paper surface and the output signal line OLj extends parallel to the paper surface. On the silicon substrate 2, the insulating dielectric layer 3 is sandwiched between the output signal line OLj, the output signal line conductive wall 4j, and the input signal line ILi.
And the conductive wall Ai for the input signal line is produced.

上記実施例では、基板としてシリコン基板を例に説明し
たが、GaAs等の半導体基板でも同様の構成が可能であ
る。また、マトリクススイッチ回路を例に説明したが、
増幅回路等の回路において線路間アイソレーションをと
る必要がある場合にも大きな効果が期待できる。
In the above-mentioned embodiment, the silicon substrate is used as an example of the substrate, but a semiconductor substrate such as GaAs may have the same structure. Also, the matrix switch circuit has been described as an example,
A great effect can be expected even when it is necessary to take isolation between lines in a circuit such as an amplifier circuit.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、中心導体が誘電体を介し
て電導性壁で囲まれた金属被覆線路を半導体基板上に形
成し、入力線および出力線からなる信号線路又は直流バ
イアス用線路の全部または一部をその金属被覆線路で構
成し、信号線路又は直流バイアス用線路がクロスする部
分では、いずれか一方のみが電導性壁で囲まれているよ
うにしたことにより、交差する線路部分に段差を作るこ
となく、接近し又は交差する線路の信号漏洩を少なくす
ることができるので、高オンオフ比を有するマトリクス
スイッチ回路や高利得を有する増幅回路などの高集積回
路化を実現できる効果があり、特にマイクロ波回路にお
いてはその効果が大きい。
INDUSTRIAL APPLICABILITY As described above, the present invention forms a metal-coated line whose central conductor is surrounded by an electrically conductive wall via a dielectric on a semiconductor substrate, and uses a signal line or a DC bias line composed of an input line and an output line. All or part of the line is covered with metal, and at the part where the signal line or the DC bias line crosses, only one of them is surrounded by the conductive wall, so that Since it is possible to reduce the signal leakage of lines that approach or intersect without forming a step, it is possible to realize a highly integrated circuit such as a matrix switch circuit having a high on / off ratio or an amplifier circuit having a high gain. Especially, the effect is great in the microwave circuit.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係わる集積回路の一実施例を示す回路
図、第2図は第1図の集積回路を構成する金属被覆線路
を示す断面図、第3図は第1図の集積回路の交差部の一
実施例を示す断面図、第4図はその第2の実施例を示す
断面図、第5図は従来の集積回路を示す回路図、第6図
はその交差部を示す斜視図である。 IT1〜ITm……入力端子、IL1〜ILM……入力信号線、OT1
〜OTn……出力端子、OL1〜OLn……出力信号線、Cij……
交差部、Sij……1入力1出力スイッチ、Mij……信号合
成器、IR1〜IRm,OR1〜ORn……終端抵抗、A1〜Am……導
電性壁。
1 is a circuit diagram showing an embodiment of an integrated circuit according to the present invention, FIG. 2 is a sectional view showing a metal-coated line which constitutes the integrated circuit of FIG. 1, and FIG. 3 is an integrated circuit of FIG. FIG. 4 is a cross-sectional view showing an embodiment of the intersection of FIG. 4, FIG. 4 is a cross-sectional view showing the second embodiment thereof, FIG. 5 is a circuit diagram showing a conventional integrated circuit, and FIG. 6 is a perspective view showing the intersection. It is a figure. IT1 to ITm …… input terminal, IL1 to ILM …… input signal line, OT1
~ OTn …… Output terminal, OL1 ~ OLn …… Output signal line, Cij ……
Intersection, Sij ... 1 input 1 output switch, Mij ... Signal combiner, IR1 to IRm, OR1 to ORn ... Termination resistance, A1 to Am ... Conductive wall.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】マトリクススイッチ回路を構成し、入力線
が1入力1出力スイッチを介して出力線に接続されてい
るマイクロ波集積回路において、 中心導体が誘電体を介して電導性壁で囲まれた金属被覆
線路を半導体基板上に形成し、前記入力線および出力線
からなる信号線路又は直流バイアス用線路の全部または
一部を前記金属被覆線路で構成し、前記信号線路又は直
流バイアス用線路がクロスする部分では、いずれか一方
のみが前記電導性壁で囲まれていることを特徴とするマ
イクロ波集積回路。
1. A microwave integrated circuit, which constitutes a matrix switch circuit and has an input line connected to an output line through a 1-input 1-output switch, wherein a central conductor is surrounded by a conductive wall through a dielectric. A metal-coated line on a semiconductor substrate, and the signal line or the DC bias line consisting of the input line and the output line is wholly or partly composed of the metal-coated line, and the signal line or the DC bias line is The microwave integrated circuit, wherein only one of the intersecting portions is surrounded by the conductive wall.
JP62003274A 1987-01-12 1987-01-12 Microwave integrated circuit Expired - Lifetime JPH07120707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62003274A JPH07120707B2 (en) 1987-01-12 1987-01-12 Microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62003274A JPH07120707B2 (en) 1987-01-12 1987-01-12 Microwave integrated circuit

Publications (2)

Publication Number Publication Date
JPS63172447A JPS63172447A (en) 1988-07-16
JPH07120707B2 true JPH07120707B2 (en) 1995-12-20

Family

ID=11552862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62003274A Expired - Lifetime JPH07120707B2 (en) 1987-01-12 1987-01-12 Microwave integrated circuit

Country Status (1)

Country Link
JP (1) JPH07120707B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2673046B2 (en) * 1991-01-31 1997-11-05 株式会社日立製作所 Semiconductor integrated circuit wiring method
JPH1047971A (en) * 1996-08-05 1998-02-20 Nippon Soken Inc Angular velocity sensor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216448A (en) * 1985-03-22 1986-09-26 Matsushita Electric Ind Co Ltd Integrated circuit device

Also Published As

Publication number Publication date
JPS63172447A (en) 1988-07-16

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