JPH07120282B2 - Branch instruction processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a branch instruction processing device, and more particularly to a branch instruction processing device in an information processing device for performing advance control of instructions.

2. Description of the Related Art Conventionally, in an information processing apparatus that employs instruction prior processing, in branch instructions, particularly conditional branch instruction processing, the branch condition cannot be determined until the instruction is executed, so the branch destination address cannot be predicted. Also, even if you can predict,
If the prediction is unsuccessful, an extra overhead is generated in branch instruction processing.

However, in an actual program, coding is often used to judge a certain condition and skip one instruction as shown in FIG. Conventionally, as a technique for speeding up a branch instruction in such a case, if a skipped instruction (ADD instruction in FIG. 2) is processed in advance and supplied to an arithmetic processing unit, and if this instruction is skipped, There is a method for suppressing the writing of the result when the calculation is executed (for example, see Japanese Patent Publication No. 5-5540).

In such a conventional technique, the instruction to be skipped is as if NO.
Since the instruction is executed like a P (No Operation) instruction, an instruction that should not be needed is executed, which has the drawback of degrading the performance.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to prevent the execution of unnecessary instructions by arithmetic operations so as to prevent performance degradation. It is another object of the present invention to provide a branch instruction processing device that enables high-speed processing of branch instructions.

According to the present invention, a branch instruction processing method in an information processing apparatus having an operand stack composed of a plurality of entries for holding an instruction and an opland in a pair and performing advance control of the instruction And means for supplying a read address of the operand stack, means for obtaining a difference between an instruction word address and a branch destination address, and means for correcting the read address of the operand stack according to the difference. A branch instruction processing device characterized by the above is obtained.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1 is a prefetch stack, which is an instruction word, an operand,
It has an entry capacity capable of storing a plurality of pairs of operand addresses and the like. The write address of the prefetch stack 1 is generated by the address register 2 and the incrementer 11. The read address of the stack 1 is generated by the address register 3, the incrementer 12, and the adder 4.

The operand address register 5 holds the operand address of the instruction currently being executed, and the instruction counter 6 holds the instruction word address of the instruction currently being executed. Subtractor 7 is operand address register 5
Is subtracted from the output of the instruction counter 6, and the result of this subtraction is supplied to the control unit 8. Also,
This subtraction result 302 is one addition input of the adder 4 (data to be added to the output of the read address register 3)
It is an input of the 2-input / 1-output selector 9 for selecting. “0” is applied to the other input of the selector 9. Incidentally, 13 is an incrementer for incrementing the content of the instruction counter 6.

When the instruction prefetching is completed, the entry pairs of the instruction word, operand, operand address, etc. are lined up on the prefetch stack 1.
At the same time as being set via 101, the contents of the write address register 2 are also updated by the incrementer 11. Next, when an arithmetic unit (not shown) is activated, the contents of the prefetch stack 1 are transferred to this arithmetic unit. At this time, the read address of the prefetch stack 1 is the register 3
Is the content of. That is, the selector 9 selects "0" data, and the adder 4 adds the contents of the register 3 and "0" data to generate the read address of the prefetch stack 1.

Here, the operand address register 5 holds the operand address currently being executed, the instruction counter 6 holds the instruction word address of the instruction currently being executed, and the instruction counter 6 finishes executing the instruction. Each time it is done, the incrementer 13 updates it by +1.

FIG. 3 is a diagram showing the manner of storing instructions in the prefetch stack 1 when processing the instruction sequence as shown in FIG. Now, suppose that the JNE instruction is executed. The preprocessed information is read from the entry corresponding to the address "2", and the operand address, that is, the branch destination address is set in the operand address register 5. At this time, if the content of the instruction counter 6 is "100", "102" is set in the operand address register 5. At this point, the read address register 3 becomes +
It is updated by 1 to become "3".

If branch GO is determined by executing this JNE instruction, line 2
This is reported to the control unit 8 through 01. On the other hand, the subtracter 7 performs an operation such that a value obtained by adding 1 to the content of the instruction counter 6 is subtracted from the content of the operand address register 5. Now, the operand address is "10
2 ”and the content of the instruction counter 6 is“ 100 ”, the subtraction result is“ 1 ”. This result is input to the control unit 8 to determine whether skipping is possible. If it is determined that skipping is possible, the selector 9 is controlled by the line 301 and the output 302 of the subtracter 7 is selected. Therefore, the correction value "1" of the read address is sent to the adder 4.

Since the content of the read address register 3 of the prefetch stack 1 is "3", the read address is "3".
It is corrected to "+1" and becomes "4", the ADD instruction is skipped, the ST instruction which is the branch destination is read, and the instruction is executed as the subsequent instruction.

When the subtraction result of the subtractor 7 becomes larger than the predetermined value determined by the capacity of the prefetch stack 1, even if the read address of the prefetch stack 1 is corrected by the subtraction result, the maximum address value of the prefetch stack 1 remains unchanged. Will be exceeded. Therefore, the control unit 8 compares the subtraction result with a predetermined value, and if the subtraction result is less than or equal to the predetermined value, determines that the entry in the prefetch stack 1 can be skipped. Make a correction.

By doing so, high-speed processing of branch instructions becomes possible without executing unnecessary instructions.

As described above, according to the present invention, the read address of the prefetch stack is corrected in response to the branch GO judgment by the execution of the branch instruction, so that the skip destination address is automatically generated by the branch GO. As a result, the execution of unnecessary instructions is suppressed and the performance is prevented from being degraded.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of an instruction sequence, and FIG. 3 is a diagram showing a storage mode of a prefetch stack. Description of symbols of main part 1 ... Prefetch stack 3 ... Read address register 4 ... Adder 5 ... Operand address register 6 ... Instruction counter 7 ... Subtractor 8 ... Control unit 9 ... Selector

Claims (1)

[Claims] 1. A branch instruction processing method in an information processing apparatus, comprising: an operand stack composed of a plurality of entries for holding instructions and operands in pairs, and performing advance control of instructions. A read address of the operand stack, a means for obtaining a difference between an instruction word address and a branch destination address, and a means for correcting the read address of the operand stack according to the difference. Branch instruction processing device.