JPH07120261B2 - Digital comparison circuit - Google Patents

Description

The present invention relates to a logical operation circuit used in, for example, an EEPROM (electrically erasable / rewritable read-only memory), and more particularly, The present invention relates to a digital comparison circuit for comparing the magnitude relationship of two binary numbers.

(Prior Art) Generally, a digital comparison circuit for comparing the magnitude relationship of two binary numbers is well known, and details thereof are, for example, "Electronic Computer Circuit", edited by Masao Yoneyama, 1974, published by Tokai University Press. P.69-73 of the above. Such a comparison circuit has been used not only in electronic computers and other digital signal processing circuits but also in semiconductor memories in recent years. That is, for example, when using the EEPROM, if it is desired to prohibit the rewriting of data in a part of the memory area, it is prohibited so as to prevent accidental rewriting of the prohibited area, or the above-mentioned prohibition is caused by a malfunction due to noise or the like. In order to prohibit rewriting of the area, it is necessary to detect whether the input address data does not specify the address area corresponding to the prohibited area. In order to perform this detection, the input address data is compared with the upper limit value (maximum address) of the prohibited area address, and similarly the input address data is compared with the lower limit value (maximum address) of the prohibited area address. A digital comparison circuit for doing so is formed on the same semiconductor chip as the memory cell.

By the way, as described above, it is desirable that the digital comparison circuit formed on a semiconductor chip such as a memory chip has a structure as simple as possible and a pattern occupation area on the chip is as small as possible. However, in the conventional digital comparison circuit, the number of elements used is large, and when formed on a semiconductor chip, the circuit pattern occupies a large area on the chip, which limits the degree of freedom in pattern design on the chip. There's a problem.

(Problems to be Solved by the Invention) The present invention has been made to solve the problem that the pattern occupying area becomes large when forming on a semiconductor chip due to the large number of used elements as described above. It is an object of the present invention to provide a digital comparison circuit which uses a small number of elements, has a simple configuration, and requires a small pattern occupying area when formed on a semiconductor chip.

[Structure of Invention]

(Means for Solving Problems) In the digital comparison circuit of the present invention, m first MOS transistors are connected in series between an output terminal and a reference potential terminal, and m second MOS transistors are connected to the transistor group. Connected in a ladder form, a load element is connected between the output end and a predetermined potential end, and bit data having respective corresponding weights in two m-bit binary data A and B.
Predetermined logical processing is performed on m _i first logic circuits for A _i and B _i to determine the logic level of the 1-bit comparison output Z _1i , and the respective correspondences in the first MOS transistor group are determined. The transistors at the bit positions to be switched are switch-controlled, and similarly, the bit data A _i and B _i are subjected to predetermined logical processing different from that of the first logical circuit by the m second logical circuits to generate 1 bit each. Of the comparison output Z _2i is determined, and the transistors at the corresponding bit positions in the second MOS transistor group are switch-controlled.

(Operation) By the first logic circuit and the second logic circuit, comparison outputs Z _1i and Z _2i whose logic levels are determined according to the magnitude relation of the bit data A _i and B _i are obtained, and the comparison outputs Z _1i and Z 1 _2i switch-controls a pair of transistors in each corresponding bit position in the first MOS transistor group and the second MOS transistor group. In this case, each transistor pair from the output end side to the reference end side is correspondingly switch-controlled by each bit pair from the maximum bit weight to the minimum bit weight in the comparison outputs Z _1i and Z _2i , A logic level corresponding to the magnitude relation between the two data A and B is obtained at the output terminal.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a digital comparison circuit for comparing the magnitude relations of two m-bit (m is an integer) binary data A and B, each of which has m number of N-channel enhancement type (E type). The first MOS transistors T _{11 to} T _1m are connected in series between the reference potential terminal 1 and the output terminal 2,
The series connection points N _{1 to} N _m-1 of the transistors in the S transistors T _{11 to} T _1m and the output terminal 2 respectively correspond to the ground via the N channel E type second MOS transistors T _{21 to} T _2m. A load element (for example, an N-channel depletion type (D-type) MOS transistor 3 whose gate and source are connected to each other) is connected between the output terminal 2 and the V _cc power source terminal. That is, m first MOSs
Transistors T _{11 to} T _1m and m second MOS transistors T
_{21 to} T _2m are connected so as to form a so-called ladder shape as a whole. Then, the first MOS transistors T _{11 to} T
Each gate of _{1 m} has one data A (= A _m , A _m-1 , ...
A ₁ ) and the other data B (= B _m , B _m-1 , ..., B ₁ ) having corresponding bit weights A _i , B _i (i = 1, 2, ..., M−)
1, m) Logical processing (here, × symbols logical product, the + sign represents the logical sum) each output Z of the first logic circuit 4 ₁₁ to 4 _{1 m} to perform
_1i is added. In this case, the maximum weight bits of the data A and B are A _m and B _m , and the minimum weight bits are A ₁ and B ₁ . Similarly, the gates of the second MOS transistors T _{21 to} T _2m are connected to the bits A _i and B _i , respectively. Second logic circuit 4 ₂₁ to 42 _m for performing logical processing of each output Z
_2i is added.

NOR circuit 4 _2i shown in FIG. 2 (a) shows a specific example of each of the second logic circuit 4 ₂₁ to 4 _2m, applied to the inverted data ▲ ▼ gate of the bit data A _i N Channel E-type MOS transistor TA ₂ and N-channel E-type MOS transistor TB _{2 to} which bit data B _i is added to the gate
Are connected in parallel between the output node 5 and the ground terminal, and an N-channel D-type MOS transistor 6 for load is connected between the output node 5 and the V _cc power supply node. The NAND circuit 4 _1i shown in FIG. 2B shows a specific example of each of the first logic circuits 4 _1i to 4 _1m. Inverted data A _i of bit data A _i is added to the gate. N-channel E-type MOS transistor TA ₁ and N-channel E-type MOS transistor TB _{1 to} which bit data B _i is added to the gate
Are connected in series between the output node 7 and the ground terminal, and the load N-channel D-type MOS transistor 8 is connected between the output node 7 and the V _cc power supply node.

The NOR circuit 4 _2i and NAND circuit 4 shown in FIGS. 2 (a) and 2 (b).
The operation of _1i is as shown in the truth table of Table 1 below.

That is, only when A _i is larger than B _i , the NOR circuit output Z _2i
Becomes "1" level (high level), and _Z1r becomes "0" level only when A _i is smaller than B _i .

Next, the operation of the digital comparison circuit will be described. The MO
Paired MOS transistors T _1i , T _2i (i = m, m−1, ..., S) in the S transistors T _{11 to} T _1m and T _{21 to} T _2m , respectively.
In 1), T _1i is turned off only when A _i <B _i , and T _2i is A
_Turns on when _i > B _i . And the least weight bit
The level of the connection point N ₁ is determined by the operation state of the transistor pair T ₂₁ and T ₁₁ gated by the comparison results Z ₂₁ and Z ₁₁ of A ₁ and B ₁ , and thereafter the higher level A _i and B of 1 bit are set. _i comparison result Z _2i of the transistor pair is gated by Z _1i T
_2i , T _1i depending on the operating state, the connection point N _i (i = 2, ..., m−
1) The transistor pair T whose level is determined and which is gated by the comparison result Z _2m , Z _1m of the maximum weight bits A _m , B _m
The output level of the output terminal 2 is determined by the operating states of _{2 m} and T _{1 m} . Therefore, the priority on the determination of the output level of the output terminal 2 becomes lower in order from the comparison results Z _2m and Z _1m of the maximum weight bits to the comparison results Z ₂₁ and Z _{11 of the} minimum weight bits. That is, if A _m > B _m , Z _2m = “1”, the transistor T _2m is turned on, the output level of the output terminal 2 becomes “0” level (ground potential), and A> B It can be seen that it is. On the other hand, when A _m = B _m , Z _2m = “0”
Since Z _1m = “1”, the transistor T _2m is turned off, the transistor T _1m becomes conductive, and the output level of the output terminal 2 is determined by the potential of the ground point N _m-1. The potential at the point N _m-1 is the comparison result of A _m-1 and B _m-1 Z _{2 (m-1)} , Z
Transistor pair T controlled by _{1 (m-1)}
It is determined by _{2 (m-1)} and T1 _(m-1) .

When A _m <B _m , Z _1m = “0” and Z _2m = “0”, so that both the transistors T _1m and T _2m are turned off and the output terminal 2
Is set to "1" level and it can be seen that A <B.
The connection point N ₁ whose potential is determined by the transistor pair T ₂₁ and T ₁₁ that are switch-controlled by the comparison results Z ₂₁ and Z _{11 of} A ₁ and B ₁ bits is Z ₂₁ when A ₁ > B _1. = by "1" the transistor T ₂₁ is turned on becomes "0", a ₁ = Z ₂₁ = "0" in the case of B _1, Z ₁₁ = "1" by the transistor T ₂₁ is turned off, the transistor Since T ₁₁ becomes conductive, the potential V _R of the reference potential terminal 1 is supplied, and when A ₁ <B ₁ , Z ₂₁ = “0”, Z ₁₁ = “0” causes the transistors T ₂₁ and T ₁₁ to operate. Since they are turned off respectively, the potential is determined by the operating states of the transistors T _{22 to} T _2m and T _{12 to} T _{1m at} the higher bit positions.

Here, as a specific example, FIG. 3 shows a case where the reference potential terminal of the comparison circuit for comparing the magnitude relationship of the 4-bit input data A and B is grounded to "0". In this circuit, if one input data B is constant (0010) and the other input data A is (0100) or (0011) (that is, A> B), the operation is the second. As in the truth table shown in the table, the operation when A is (0010) (that is, when A = B) is as in the truth table shown in Table 3, and when A is (0001), for example. The operation (that is, when A <B) is as in the truth table shown in Table 4. Thus, output terminal 2 is "1" only when A <B
Can be set to a level.

As described above, the digital comparison circuit can be easily configured with a relatively small number of MOS transistors. Therefore, when it is formed on a semiconductor chip, the pattern occupation area on the chip can be small, and the chip size can be suppressed and the pattern design can be achieved. It is possible to obtain the advantage that the degree of freedom can be improved.
Further, it becomes possible to detect the prohibited address area by forming the digital comparison circuit on the same chip as the floating gate type EEPROM. That is, the lower limit value (minimum address) of the prohibited address area is, for example, the data B, and the input address data is the data A,
A first digital comparator circuit whose output level becomes “0” when A ≧ B and the upper limit value (maximum address) of the prohibited address area are the data A, the input address data is the data B, and A ≧ When B, the output level is "0"
And a second digital comparison circuit, and the "0" output of the first digital comparison circuit and the "0" output of the second digital comparison circuit
It can be realized by providing a logic circuit that determines that the input address data exists in the prohibited address area when both the output and the output are generated. Then, it becomes possible to prohibit the rewriting of the data rewrite prohibited area according to the determination result. As described above, a MOS integrated circuit such as an EEPROM is used in the MOS
When forming a digital comparison circuit including a transistor group, it is advantageous in terms of process.

By comparing the conductivity type of all or part of the MOS transistors used in each of the above embodiments and appropriately changing the potential relationship and the logic level of each node according to the change, the magnitude relationship between the two data A and B is compared. It is also possible to carry out modifications to obtain the operation.

〔The invention's effect〕

As described above, according to the digital comparison circuit of the present invention, the number of elements used is small, its configuration is simple, and the pattern occupying area when formed on a semiconductor chip is small. It is suitable for forming.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a digital comparison circuit of the present invention, and FIGS. 2 (a) and 2 (b) are respectively the first part in FIG.
A circuit diagram showing a specific example of the second logic circuit,
FIG. 3 is a circuit diagram showing an example of a digital comparison circuit for 4-bit data. 1 ...... reference potential terminal, 2 ...... output, 3 ...... load transistors, 4 ₁₁ to 4 _{1 m} ...... first logic circuit, 4 ₂₁ to 4 _2m ...... second
Logic circuit, T _{11 to} T _1m , T _{21 to} T _2m , TA ₁ , TA ₂ , TB ₁ , TB ₂
...... MOS transistor.

Claims (5)

[Claims] 1. M number (m is an integer) first MOS transistors T _{11 to} T connected in series between a reference potential terminal and an output terminal.
_1m, between each of the series connection points of the transistors in the first MOS transistors T _{11 to} T _1m and the first potential end,
And m second MOS transistors T _{21 to} T _2m connected between the output terminal and the first potential terminal in a corresponding manner.
And a load element connected between the output terminal and the second potential terminal, and bit data A _i , B _i (i) having respective corresponding weights in two binary data A, B of m bits respectively. = 1,…, m
Where m represents the maximum weight bit position) and the logical level of the 1-bit comparison output Z _1i (i = 1, ..., m) is substantially applied to the logical processing of A _i + ▲ ▼. And m first logic circuits 4 ₁₁ to 4 _1m for controlling the gate potentials of the transistors at the corresponding bit positions in the first MOS transistors T _{11 to} T _1m by the comparison output Z _1i. the bit data A _i, substantially A _i × against B _i
Performs logical processing of ▲ ▼ and outputs 1-bit comparison output Z
The logic level of _2i (i = 1, ..., m) is determined and this comparison output
Characterized by being provided with a second MOS transistor T ₂₁ through T to control the gate potential of the transistor of each corresponding bit position in _2m m-number of second logic circuit 4 ₂₁ to 4 _2m by Z _2i And a digital comparison circuit. 2. The potential at the reference potential end has a logic level "0".
Alternatively, the digital comparison circuit according to claim 1, wherein the digital comparison circuit is set to "1". 3. The m number of first logic circuits 4 ₁₁ to 41 _m and the m number of second logic circuits 4 ₂₁ to 42 _m are each constituted by a MOS transistor. The digital comparison circuit according to claim 1. 4. The m first MOS transistors T _{11 to} T
_{1 m} and the m second MOS transistors T _{21 to} T _2m
Are N-channel enhancement type MOS transistors, the first potential end is a ground potential end, and the second potential end is a positive power supply potential end. The digital comparison circuit according to item 1. 5. The digital comparison circuit is provided on the same chip as an electrically erasable / rewritable read-only memory and compares an address area corresponding to a data rewrite prohibited area with input address data. The digital comparison circuit according to any one of claims 1 to 4, wherein the digital comparison circuit is used as.