JPH07115125A - Semiconductor integrated circuit device and manufacture therefor - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, wherein a leakage current can be restrained from occurring even in an environment that gamma-ray or X-ray may impinge on the device by a method wherein a channel stopper is enhanced in an inversion layer stop capacity. CONSTITUTION:A field oxide film 2, a gate oxide film 3, and a gate electrode 4 are formed on a P-type semiconductor substrate 1, and arsenic ions are implanted for the formation of an N<+>-type diffusion layer 5 [figure (a)]. A photoresist film 6 provided with an opening located at the center of the field oxide film 2 is formed, the field oxide film 2 is selectively etched to be provided with a groove 7, and baron ions are implanted into the groove 7 to form a P<+>-type diffusion region 8 under the groove 7 [figure (b)]. A silicon oxide film 9 is formed inside the groove 7 through a liquid growth method, and an interlayer insulating film 10 is provided [figure (c)].

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device provided with a field insulating film for element isolation and a method for manufacturing the same, and particularly to a high radiation resistance of the element isolation film so that it can be used for space. And a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, it is necessary to electrically isolate elements from each other. As an element isolation technique, a field insulating film by a selective oxidation method (LOCOS method) is widely adopted. FIG. 5A is a plan view of a conventional semiconductor integrated circuit device in which element isolation is performed using a field insulating film, and FIG. 5B is a sectional view taken along the line CC '. In order to manufacture this conventional example, after forming ap ⁺ diffusion region 14 serving as a channel stopper on the surface of the p-type semiconductor substrate 1, a field oxide film 2 is formed on the p ⁺ diffusion region 14 by a selective oxidation method. A gate oxide film 3 is formed on the region where the field oxide film is not formed. After forming the gate electrode 4 on the gate oxide film 3, the gate electrode 4
And arsenic (As) using the field oxide film 2 as a mask
Are ion-implanted to form an n ⁺ type diffusion layer 5 to be source / drain regions. BPSG is formed on the n-channel MOS transistor Qn thus formed by the CVD method.
(Boro-phospho-silicate glass) is deposited to form the interlayer insulating film 10.

When high-energy radiation such as γ-rays or X-rays is incident on this semiconductor integrated circuit device, holes in the electron-hole pairs generated in the field oxide film 2 move to the vicinity of the silicon-oxide film. Then, they are trapped by the hole traps distributed near the interface, and fixed charges are accumulated under the field oxide film. A p ⁺ type diffusion region 14 is formed under the field oxide film to prevent the generation of an inversion layer. However, when the amount of fixed charges accumulated increases, the p ⁺ type diffusion region 1 is formed.
An inversion layer is generated in 4 and an abnormal current path appears, resulting in current leakage between adjacent MOS transistors.

FIG. 6 (a) is a plan view of a conventional example having means for preventing the occurrence of this abnormal current path proposed in Japanese Patent Laid-Open No. 2-192159, and FIG. 6 (b) shows the same. It is a sectional view of a DD 'line. In FIG. 6, portions similar to those of FIG. 5 are designated by the same reference numerals, and a duplicate description will be omitted. However, in this conventional example, a concave groove 15 is formed on the upper surface of the field oxide film 2. The groove 15 is filled with BPSG forming the interlayer insulating film 10. In the semiconductor integrated circuit device configured as described above, since many recombination centers and trap centers are contained in the BPSG film, positive charges generated by γ-rays or X-rays recombine or disappear due to recombination centers or trap centers. Immobilized capture,
Accumulation of fixed positive charges under the field oxide film 2 is suppressed.

[0005]

In any of the first and second conventional examples described above, the p ⁺ diffusion region 14 is formed by introducing boron ions B ⁺ into the surface of the semiconductor substrate. Thereafter, a thermal oxidation process at a high temperature for a long time is performed for forming a field oxide film, so that the above B ⁺ is largely diffused, and it is difficult to maintain this region at a sufficiently high concentration. Therefore, not only in the first conventional example but also in the second conventional example, the inversion layer generation preventing function is not sufficient, and an abnormal current path is generated between the MOS transistors due to the accumulated positive charges, causing current leakage. Further, in each of the above conventional examples, the boron ion implantation mask is the same as the nitride film patterning mask for forming the field oxide film, and the n ⁺ type diffusion layer 5 is formed using the field oxide film 2 as a mask. Therefore, the p ⁺ type diffusion region 14 is formed in direct contact with the n ⁺ type diffusion layer 5, and there is a problem that the junction breakdown voltage between both diffusion layers becomes low.

[0006]

In order to solve the above problems, according to the present invention, the first conductive type semiconductor substrate (1) or the first conductive type well is penetrated or almost penetrated through the entire film thickness. A field insulating film (2) for element isolation having a groove (7) formed therein is formed, and a high-concentration diffusion layer (8) of the first conductivity type is formed substantially only just under the groove. Provided is a semiconductor integrated circuit device, wherein at least a part of the groove is filled with an insulator (9).

According to the present invention, the step of selectively oxidizing the surface of the semiconductor substrate to form the field insulating film (2) for element isolation, and the first conductivity type semiconductor region (1).
A step of selectively removing the field insulating film above to form a groove (7) penetrating or almost penetrating the entire film thickness; and ion-implanting a first conductivity type impurity (boron) to directly under the groove. A semiconductor integrated circuit device comprising: a step of forming a high-concentration first-conductivity-type diffusion layer (8) in a semiconductor region; and a step of filling at least a part of the groove with an insulator (9). A method of manufacturing the same is provided.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a plan view showing a state before a wiring process of a first embodiment of the present invention, and FIG. 2 is a process cross-sectional view taken along the line AA 'of FIG. 2 (c). , A- in FIG.
It is a sectional view taken along the line A ′]. As shown in FIG. 1, an n-channel MOS transistor Qn having a gate electrode 4 and an n ⁺ type diffusion layer 5 serving as a source / drain region is formed in an active region surrounded by a field oxide film 2. A p ⁺ type diffusion region 8 serving as a channel stopper is formed in the semiconductor substrate surface region below the field oxide film 2.

The semiconductor integrated circuit device of this embodiment is manufactured as follows. A field oxide film 2 having a film thickness of about 5000Å is formed on the surface of the p-type semiconductor substrate 1 having a resistivity of 11.5 to 15.5 Ω · cm by the LOCOS method, and is formed on a region where the field oxide film 2 is not formed. The gate oxide film 3 is formed by the thermal oxidation method. Polycrystalline silicon having a thickness of 0.7 μm is deposited on the gate oxide film 3 and patterned to form the gate electrode 4, and then arsenic is used as an acceleration energy of 30 keV and a dose amount using the gate electrode 4 and the field oxide film 2 as a mask. N ⁺ type diffusion layer 5 to become source / drain regions by ion implantation under the condition of 5 × 10 ¹⁵ cm ^-2
Are formed [FIG. 2 (a)].

A photoresist film 6 having an opening is formed on the central portion of the field oxide film 2 by photolithography, and the field oxide film 2 is selectively removed using this as a mask to form a groove penetrating the field oxide film. Form 7. Next, using the photoresist film 6 as a mask, the groove 7 is formed.
Boron is ion-implanted under the conditions of an acceleration energy of ¹⁵ keV and a dose amount of 5 × 10 ¹⁵ cm ^-2 to form a p ⁺ -type diffusion region 8 on the surface of the semiconductor substrate 1 immediately below the groove 7 [FIG. ].

Further, using the photoresist film 6 as a mask, SiO ₂ is grown by liquid phase epitaxy to form a silicon oxide film 9 filling the groove 7 formed in the field oxide film 2. Then, the photoresist film 6 is removed by ashing, and BPSG is grown by the CVD (Chemical Vapor Deposition) method to form the interlayer insulating film 10 [FIG. 2 (c)]. After that, a contact hole is opened and aluminum is deposited by a conventional method and then patterned to form an aluminum wiring (not shown).

In the semiconductor integrated circuit device formed as described above, there is no heat treatment step at a high temperature for a long time after boron ion implantation, so that the p ⁺ type diffusion region 8 as a channel stopper is prevented from being greatly expanded. be able to.
That is, the impurity concentration of the p ⁺ type diffusion region 8 can be maintained at a predetermined high concentration, and the diffusion region 8 and the n ⁺ type diffusion layer 5 of the MOS transistor Qn are combined with the narrow boron ion implantation range. A sufficient distance can be secured. Therefore, the channel stopper (p
^The current leakage prevention function of the ⁺ type diffusion region) can be strengthened, and the extension of the depletion layer of the n ⁺ type diffusion layer 5 of the transistor Qn to the channel stopper side can be expanded, and the source of the MOS transistor Qn It is possible to prevent a decrease in the junction breakdown voltage of the drain.

Further, the formation of the SiO ₂ film by the liquid phase growth method is performed by the reaction of H ₂ SiF ₆ + 2H ₂ O ← → 6HF + SiO ₂ H ₃ BO ₃ + 4HF ← → BF ₄ ⁻ + H ₃ O ⁺ + 2H ₂ O. Therefore, BF ₄ ⁻ remains in the formed silicon oxide film 9. It is known that the fluorine F existing in the oxide film has a function of trapping and immobilizing the positive charges, and this function of the liquid phase growth silicon oxide film filling the groove 7 causes accumulation of fixed positive charges near the interface. Can be suppressed.

FIG. 3 is a plan view showing a state before a wiring process of a second embodiment of the present invention, and FIG. 4 is a process sectional view taken along the line BB 'of FIG. c) is B- in FIG.
It is a sectional view taken along the line B ′]. As shown in FIG. 3, an n-channel MOS transistor Qn having a gate electrode 4 and an n ⁺ type diffusion layer 5 serving as a source / drain region, and a p ⁺ type diffusion layer 11 serving as a gate electrode 4 and a source / drain region are provided. The p-channel MOS transistor Qp has is formed in the active region surrounded by the field oxide film 2. A p ⁺ type diffusion region 8 serving as a channel stopper is formed in the semiconductor substrate surface region below the field oxide film 2 surrounding the transistor Qn.

The semiconductor integrated circuit device of this embodiment is manufactured as follows. On the surface of the p-type semiconductor substrate 1 having a resistivity of 11.5 to 15.5 Ω · cm, phosphorus is applied with an energy of 130 k.
Ions are implanted under the conditions of eV and a dose amount of 5 × 10 ¹² cm ⁻² , and heat treatment is performed at 1200 ° C. to form the n well 12. Next, the field oxide film 2 is formed to a film thickness of about 5000Å by the LOCOS method, and the gate oxide film 3 is formed on the region where the field oxide film 2 is not formed.
A gate electrode 4 made of polycrystalline silicon is formed on the gate oxide film 3.
Then, the n well 12 is protected by a photoresist, and the arsenic is accelerated with an acceleration energy of 30 keV and a dose of 5 × 1 using the gate electrode 4 and the field oxide film 2 as a mask.
Ions are implanted under the condition of 0 ¹⁵ cm ^-2 to form the n ⁺ type diffusion layer 5 to be the source / drain regions of the transistor Qn. Subsequently, the n-channel MOS transistor side is protected by a photoresist, and the boron is accelerated with an acceleration energy of 20 ke using the gate electrode 4 and the field oxide film 2 as a mask.
Ions are implanted under the conditions of V and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form the p ⁺ type diffusion layer 11 to be the source / drain regions of the transistor Qp [FIG. 4 (a)].

Next, by photolithography technique, n
A photoresist film 6a having an opening is formed on the central portion of the field oxide film 2 surrounding the channel MOS transistor Qn, and the field oxide film 2 is selectively removed using this as a mask to form a groove 7 penetrating the field oxide film. Form. Next, using the photoresist film 6a as a mask, boron fluoride (BF ₂ ⁺ ) is passed through the groove 7 and the acceleration energy 10
Ions are implanted under the conditions of keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form a p ⁺ type diffusion region 8 serving as a channel stopper on the surface of the semiconductor substrate 1 immediately below the groove 7 [FIG. 4 (b)].

Further, using the photoresist film 6a as a mask, SiO ₂ is grown to a film thickness of about 20 nm by a liquid phase epitaxy method to fill a part of the groove 7 formed in the field oxide film 2 with the silicon oxide film 9. Next, the photoresist film 6a is removed by ashing, tungsten is deposited on the entire surface by a sputtering method, and then etched back to fill the shield plate 13 in the groove 7. Then, BPSG is grown by the CVD method to form the interlayer insulating film 10 [FIG. 4 (c)]. The shield plate 13 is used in any one of a grounded state, a negative voltage applied state, and a floating state. After that, a contact hole is opened and aluminum is deposited by a conventional method and then patterned to form an aluminum wiring.

Also in this embodiment, p ⁺ under the field oxide film formed surrounding the n-channel MOS transistor is used.
Since the impurity concentration of type diffusion region 8 can be maintained high, current leakage between adjacent n channel MOS transistors and between n ⁺ type diffusion layer 5 and n well 12 of the n channel MOS transistor can be suppressed. Further, by disposing the shield plate in the groove, the variation amount of the threshold voltage of the parasitic n-channel MOS transistor can be suppressed small.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, in the embodiment, CM
In forming the OS type semiconductor integrated circuit device, the n well was formed using the p type semiconductor substrate, but it is possible to reverse this to form the p well in the n type semiconductor substrate. Alternatively, both the n-well and the p-well can be formed on the p-type (or n-type) semiconductor substrate. In these cases, a groove is provided in the field oxide film formed on the p well, and the p ⁺ type diffusion region is formed immediately below the groove. Further, in the first and second embodiments, the groove 7 in the field oxide film reaches the surface of the semiconductor substrate, but it may be a groove in which the field oxide film is left on the order of 10 to 20 nm. Further, in the embodiment, the groove 7, the p ⁺ type diffusion region 8 and the silicon oxide film 9 are formed after the MOS transistor is formed. However, the order is reversed to form 7 to 9 and then the MOS transistor is formed. Can be

[0020]

As described above, in the semiconductor integrated circuit device according to the present invention, after the field oxide film is formed,
According to the present invention, the channel stopper is formed because a groove penetrating or almost penetrating the field oxide film is formed and boron is injected through the groove to form a p ⁺ -type diffusion region serving as a channel stopper. It is possible not to go through a high temperature heat treatment for a long time after the formation.
Therefore, according to the present invention, it is possible to form a channel stopper having a sufficiently high concentration and prevent the generation of the inversion layer even in an environment such as space where γ-rays and X-rays are incident to prevent current leakage. Can be suppressed. Further, according to the present invention, since the impurity introduction region for forming the channel stopper is limited to a narrow range and the high temperature history after the impurity introduction is small, the channel stopper does not come into contact with the source / drain region of the transistor. Thus, it is possible to maintain a high junction breakdown voltage in these regions.

Further, according to the present invention, since the silicon oxide film containing F is buried in the groove formed in the field oxide film, the positive charge generated by the radiation such as γ-rays is trapped in F ⁻ . Therefore, it is possible to more reliably suppress the generation of the abnormal current leakage path between the elements.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a plan view showing a second embodiment of the present invention.

FIG. 4 is a process sectional view for explaining the manufacturing method of the second embodiment of the present invention.

FIG. 5 is a plan view and a cross-sectional view of a first conventional example.

FIG. 6 is a plan view and a sectional view of a second conventional example.

[Explanation of symbols]

1 p-type semiconductor substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 n ⁺ type diffusion layer (source / drain region of transistor Qn) 6, 6a photoresist film 7 groove formed in field oxide film 8 p ⁺ type diffusion layer Region (channel stopper) 9 Silicon oxide film formed by liquid phase growth method 10 Interlayer insulating film 11 p ⁺ type diffusion layer (source / drain region of transistor Qp) 12 n well 13 Shield plate 14 p ⁺ type diffusion region (channel stopper) ) 15 Groove formed in field oxide film Qn n-channel MOS transistor Qp p-channel MOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 7514-4M H01L 29/78 301 R

Claims (9)

[Claims] 1. A field insulating film for element isolation, in which a groove penetrating or almost penetrating the entire film thickness is formed on a first conductive type semiconductor substrate or a first conductive type well, and directly below the groove. A semiconductor integrated circuit device comprising: a first-conductivity-type high-impurity-concentration diffusion layer formed substantially only; and at least a part of the groove is filled with an insulator. 2. The semiconductor integrated circuit device according to claim 1, wherein the insulator filling the groove contains fluorine. 3. The semiconductor integrated circuit device according to claim 1, wherein the insulator filling the groove is a silicon oxide film formed by a liquid phase epitaxy method. 4. The semiconductor integrated circuit device according to claim 1, wherein the groove is filled with a silicon oxide film formed by a liquid phase epitaxy method and a metal layer forming a shield plate. 5. A step of selectively oxidizing the surface of a semiconductor substrate to form a field insulating film for element isolation, and the field insulating film on the first conductivity type semiconductor region is selectively removed to form the entire film. Forming a groove penetrating or almost penetrating the thickness, forming a first-conductivity-type diffusion layer having a high impurity concentration in the semiconductor region immediately below the groove by ion-implanting a first-conductivity-type impurity, and the groove And a step of burying at least a part of the insulating layer with an insulating material. 6. A step of selectively oxidizing a surface of a semiconductor substrate to form a field insulating film for element isolation, a step of forming a MOS transistor in a region partitioned by the field insulating film, and a first conductive method. Selectively removing the field insulating film on the semiconductor region to form a groove penetrating or almost penetrating the entire film thickness, and ion-implanting a first conductivity type impurity into the semiconductor region immediately below the groove. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of forming a first-conductivity-type diffusion layer having a high impurity concentration; and a step of filling at least a part of the groove with an insulator. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step of filling at least a part of the groove with an insulator is performed by liquid phase growth of a silicon oxide film. 8. A step of selectively removing the field insulating film to open a groove, and a step of forming a high-concentration first conductivity type diffusion layer in the semiconductor region directly below the groove by ion implantation, 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step of filling at least a part of the groove with an insulator is performed using the same photoresist film as a mask. 9. After partially filling the inside of the groove with a silicon oxide film by a liquid phase growth method, a metal layer is deposited on the entire surface and is etched back to fill the remaining portion of the groove with the metal layer. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein.