JPH07114799A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To relieve a defective bit with a simple method without performing laser processing and without increasing chip area. CONSTITUTION:An address data of a defective bit stored in a flash memory 10 is compared with an address signal from the outside (CPU), it is decided whether reading/writing of data based on the address signal is to be performed for a normal area 21A or for a redundant area 21B. Increasing a chip area can be suppressed without providing a fuse for relieving and the like conventionally required. Also, relieving of the defective bit can be simply performed by only storing address data of the defective bit in the flash memory 10. In order to discriminate whether an address signal indicates a defective bit or not, it is divided into the upper bit and the lower bit and compared, when both upper bits are not coincident, a normal area is immediately accessed, and processing speed is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is particularly effective when applied to a semiconductor memory device in which two memory parts having different functions are formed on the same chip. The present invention relates to a technique useful for a random access memory.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory, a redundant circuit is provided in the chip in case a defective bit occurs. Then, when the defective bit is detected in the inspection performed before the packaging of the LSI, the spare decoder provided in the redundant circuit is programmed based on the address data of the defective bit, and the address of the defective bit is input. At this time, the spare decoder is selected, the redundant bit in the redundant circuit corresponding to this defective bit is selected, and the defective bit is relieved. When programming the spare decoder, for example, a method of cutting a predetermined relief fuse element provided on the chip with a laser beam or the like before packaging is used.

Further, conventionally, in designing a semiconductor memory, the standard specifications such as the mode of the rise processing of the word line of the memory mat are determined by the wiring pattern of the semiconductor memory device. For example, in a semiconductor memory device whose memory area is divided into four memory mats, a word line is simultaneously activated for four memory mats when performing a read / write operation. Specification for performing word line startup by selecting two mats (referred to as "x2 specification") Specification for performing word line startup by selecting one mat (referred to as "x2 specification" (referred to as "x2 specification") × 1
It is possible to change the way of access in the manner of "specification"). Which of the “× 4 specifications”, “× 2 specifications”, and “× 1 specifications” should be selected was determined in advance by preparing three types of wiring patterns and using which of them. . Further, in the conventional semiconductor memory, if the memory is a dynamic RAM, the storage / reproduction operation (refresh operation) must be performed, and in order to perform this refresh operation, the user must It was necessary to input a control signal for refresh from the CPU.

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, in the above-mentioned conventional redundant circuit technology, when repairing a defective bit, the fuse must be cut by the laser beam as described above, and if the number of bits to be repaired is increased, the fuse area becomes large. The problem of occurs.

Further, as described above, in the technique of selecting the "x1 specification", "x2 specification", and "x4 specification" of the memory by the wiring pattern, which specification is the memory concerned? Accordingly, it is necessary to design a plurality of different wiring mask patterns, which requires a long time to manufacture an LSI that meets the user's request, and also causes an increase in cost.

Further, in the above-described conventional refresh operation technique, the user has to design a circuit for causing the DRAM to perform the refresh operation, which is inconvenient. Further, if the refresh operation is stopped during the operation, the refresh operation must be restarted from the first bit, and the stored contents may be lost during that time.
Therefore, once the refresh operation is started, access during the operation is prohibited and the throughput of the system is reduced.

The present invention has been made in view of the above circumstances. A first object of the present invention is to increase the chip area with a simple method for repairing a defective bit without performing laser processing. It is an object of the present invention to provide a semiconductor memory device that can be carried out without the need. A second object is to provide a semiconductor memory device that can easily change the standard specifications relating to the read / write operation of the memory mat according to the user's request. A third object of the present invention is to provide a semiconductor memory device which, when the memory is a DRAM, enables the access operation even during the refresh operation to increase the throughput of the system using the DRAM. Is. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in order to achieve the first object, in the semiconductor memory device according to claim 1, the main memory unit including the redundant circuit and the sub memory unit configured by the rewritable nonvolatile memory are the same. Defective address data that is formed on a chip and that specifies a defective bit occurrence location is stored in the sub-memory section, and a defective bit position is determined based on the defective address data to relieve the defective bit position. There is. In order to achieve the second object, in the semiconductor memory device according to claim 2, a drive circuit for performing a read / write operation of the plurality of memory mats is provided for each memory mat, and Data for controlling the operation of the drive circuit is stored in a rewritable nonvolatile memory provided on the same chip as the memory mat. Further, in order to achieve the third object, in the semiconductor memory device according to claim 3, a non-volatile sub memory unit is formed on the same chip as a main memory unit constituting a DRAM, and a memory reproducing operation is performed. When is stopped,
The stopped bit position is stored in the sub storage unit.

[0009]

According to the semiconductor memory device of the first aspect, by only storing the address data of the defective bit in the sub storage unit, the defect relief such as the bit defect, the bit line defect, the word line defect, the mat defect, etc. can be relieved. It can be done as appropriate. or,
According to the semiconductor memory device of claim 2, the specifications (“× 1 specification”, “× 2 specification”, “× 4 specification” relating to the start-up operation of the word line are based on the stored contents of the sub storage unit. )) Can be selected, and it is not necessary to design a plurality of wiring patterns as in the conventional case. Further, according to the semiconductor memory device of the third aspect, when a read / write operation is accessed during the refresh operation, the bit position at which the memory reproducing operation is being performed is stored in the sub memory unit. When the access is completed, the refresh operation can be restarted from the bit position.

[0010]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram schematically showing the structure of a dynamic random access memory (DRAM) according to the first embodiment, and FIG. 2 is a block showing a procedure for comparing defective bit address data and address signal data. It is a figure.

In this embodiment, the flash memory 10 and D
The RAM 20 is formed on the same chip 1. Among them, the flash memory 10 stores defective address data relating to defective bits (defective bit line, defective word line, defective mat) generated in the memory area of the DRAM 20. The DRAM 20 includes a memory area 21 divided into a normal area 21A and a redundant area 21B, and a comparison circuit 2
It is composed of 3. Then, based on the address signal from the outside (CPU), the read / write of the DRAM 20 is performed.
When the write operation is performed, the address signal is sent to the comparison circuit 23, and the defective address data stored in the flash memory 10 is compared with the address signal. When the result of this comparison does not match, the data is read from the normal area 21A or the data is written in the area 21A according to the address. On the other hand, as a result of the comparison, when the two address data match, that is, when the bit accessed by the address signal is a defective bit, the redundant data is read from the redundant area 21B and the area 21 is read.
Data is written to B.

Next, a method of comparing the address signal and the defective address data by the switching circuit 23 will be described. As shown in FIG. 2, the comparison circuit 23 includes a first comparator 23A and a second comparator 23B. Of these, the first comparator 23A sends a signal (indicated by the flash memory) indicating a defective address to the first comparator 23A. The defective address data related to the upper bits of the defective address signal) is input, and the defective address data related to the lower bits is input to the second comparator 23B. Now, suppose the outside (CP
U) to DRAM 20 (for example, x4 specification 16 mega DR
Consider the case where the address signal input to (AM) is 24 bits. In this case, 11 bits are assigned to both the X address data and the Y address data. And
When the RAS signal is input, the signal related to the X address is input, and when the CAS signal is input, the signal related to the Y address is input.

Then, when the RAS signal is input, the data associated with the X address of the defective address data is read from the flash memory 10 and its upper bit (4
The bit data is sent to the first comparator 23A, and the lower bit data (remaining bits) is sent to the comparator 23B.
On the other hand, the X address signal is input to the first comparator 23A, and its upper bit data is compared with the upper bit data of the defective address data. If the result of this comparison shows that they do not match, the normal area 21A is accessed by the address signal. On the other hand, if the higher-order bit data of the address signal matches the higher-order bit of the defective address data, a match signal is sent to the second comparator 23B, and the comparator 23B causes the remaining bit data ( The lower bit) is compared with the lower bit data of the defective address data. As a result of this comparison, if it is determined that the lower bit data does not match the defective address data, the normal area 21A is accessed based on the address signal, and the lower bit data matches the defective address data. Then, the redundant area 21B is accessed based on the address signal. Also, the above C
When the AS signal is input, the Y address signal and the defective address data are compared in the same procedure.

In comparing the address signal with the defective address data in this manner, the comparison is performed for the upper bits and the lower bits, thereby making it possible to quickly determine which area to access. The processing speed can be improved.

As described above, according to the semiconductor memory of the first embodiment, the address data of the defective bit stored in the flash memory 10 is compared with the address signal input from the outside (CPU), According to the result of the comparison, whether to read or write the data based on the address signal to the normal area or the redundant area is determined. It is possible to suppress the increase of the chip area by not providing the above. Moreover, the defective bit can be relieved simply by storing the address data of the defective bit in the flash memory 10. In addition, since whether the address signal indicates a defective bit or not is divided into upper bits and lower bits and compared, if there is a mismatch at the time of comparing the upper bits, the normal area is immediately displayed. Access can be made and processing speed becomes faster. In this embodiment, the redundant area 21B is set to the DRAM
Although the example in which it is formed separately from the normal area 21A has been described, a redundant area may be provided on the same mat as the normal area. The flash memory is formed in a vacant area (for example, a vacant area in the area in which the peripheral circuit is formed) of the semiconductor chip in which the DRAM is formed, and its storage capacity of about 1 kbit is sufficient. In the above embodiment, the semiconductor memory device having the RAM as the main memory portion has been described as an example, but it may be used for repairing a defective bit in the memory device including the ROM.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In the DRAM 30 of the second embodiment, the memory area is divided into a plurality of areas (for example, four memory mats), and a drive circuit for raising the word line is provided for each memory mat. The DRAM 30 has a specification (referred to as “× 1 specification”) in which four memory mats are simultaneously activated for read / write operations (referred to as “× 1 specification”). One of the specifications (I) for raising the word line (referred to as “× 2 specification”) and the specification for raising one word line by selecting one mat (referred to as “× 2 specification”) (I
(/ O specification) can be appropriately selected according to the stored contents of the flash memory 31.

Specifically, in the flash memory 31,
Data relating to the specifications selected by the user is stored, and the standby voltage Vcc applied to the DRAM 30 is also applied to the flash memory 31. Then, when the standby voltage is applied, an output signal based on the stored data indicating the I / O specifications is sent to the DRAM 30. In the DRAM 30 receiving the output signal, the switching circuits 32, 33 ... Are turned on / off according to the output level. Then, based on the ON / OFF signal, a plurality of pads (two pads 34 and 35 in the drawing are provided in the RAM 30.
(Only shown) is selected.

Assuming that the I / O specifications selected by the user are:
If the pad 34 is not required, the signal line L1
A higher level signal is input. At this time, the high level signal is also sent to the main amplifier 36 of the RAM 30. Conversely, if the selected I / O specification requires pad 34, then signal line L
A low level signal is input from 1 (at this time, the low level signal is sent to the main amplifier 36). As described above in detail, according to the semiconductor memory device of the second embodiment, I
Since the / O specification can be selected based on the data stored in the flash memory, the structure (wiring pattern) of the semiconductor memory device is not changed for each specification, and the cost is reduced. In addition, in the semiconductor memory device having the above configuration, even after the packaging, even if a specific mat is unusable due to defective bits in the memory,
A semiconductor memory device in which a so-called “mat missing” has occurred due to a change in I / O specifications according to stored data in a flash memory can be used like any other semiconductor memory device. Furthermore, since the I / O specifications of the semiconductor memory device are not determined until it is delivered to the user, product management on the manufacturer side becomes easy. Incidentally, also in this second embodiment,
Although the semiconductor memory device in which the main memory portion is configured by the RAM has been described as an example, the semiconductor memory device may be used for relieving a defective bit in the memory device including the ROM.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the flash memory 41 formed on the same chip as the DRAM 40 stores data relating to the control of the refresh operation (storage / reproduction operation). That is, the conventional refresh operation is performed every predetermined time based on a control signal from the outside of the DRAM (for example, a CPU). For this reason, users need to install a refresh drive circuit for performing a refresh operation in the DRAM.
It was set up separately from. Therefore, in the DRAM of the present embodiment, the refresh operation is performed by the DRAM 40 itself by writing the data required for the refresh operation in the flash memory 41 provided on the same chip. That is, the flash memory 41 stores the refresh time according to the usage status of the user, and when the standby voltage Vcc is applied to the flash memory 41, the stored data is determined. Then, a signal (refresh control signal) representing the stored content is sent to the refresh control circuit 43 of the DRAM 40. This refresh control circuit 43
For example, the memory mat 45 is provided for each memory mat of the DRAM 40 (only one is shown), and the elapse of the refresh time is detected based on the value stored in the flash memory 41 and the clock signal from the timer 42 to detect the memory mat 45. Then, the refresh operation is performed.

Further, in the flash memory 41, when an access is made from the outside (CPU) during the refresh operation, the memory position where the refresh is being performed at that time is stored. . Then,
When an address signal is input during the refresh operation, the refresh operation is interrupted and data read / write processing is performed based on the input address signal. When this read / write processing is completed, the refresh operation is performed again from the memory location stored in the flash memory 41. By storing the memory location in the flash memory 41 in this manner, it becomes possible to perform an access process which is conventionally prohibited during the refresh operation.

As described above, according to the semiconductor memory device of the third embodiment, the refresh control circuit 43 provided for each memory mat performs its refresh operation based on the data stored in the flash memory 41. Since it is automatically performed, the user does not need to prepare a refresh drive circuit which has been conventionally required. Further, by setting the storage data of the flash memory 41 according to the usage status of the user, it becomes possible to perform an appropriate refresh operation according to the usage status. Also, during the refresh operation of the DRAM 40,
When the address signal is input, the memory location where the refresh is being performed at that time can be stored in the flash memory 41, so that access can be made during the refresh operation, which has been conventionally prohibited, and the processing speed of the DRAM can be increased. Is improved.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, the memory area of the DRAM is divided into a plurality of memory mats, and a special area is provided in each memory mat so that one DRAM can function as two different storage units. ing.

That is, as shown in FIG. 5, the DR of this embodiment is
The AM 50 has a memory area 51 with a storage capacity of 16 Mbits, and the memory area is divided into four memory mats 51A, 51A, 51A, 51A for 4M bits. Then, a storage area for 1 mega of each memory mat is secured as the special area 51a, 51a, 51a, 51a. In the DRAM 50 having such a configuration,
The flash memory 55 is provided on the same chip, and the control mode when the read / write operation of the DRAM 50 is performed is performed based on the data stored in the flash memory 55. That is, the data stored in the flash memory 55 is sent to the control unit 52 of the DRAM 50. Based on the above-mentioned data, the control unit 52 uses a normal memory area (a memory area for 3 megabytes)
And the special area are distinguished and the read / write operation is performed. As an example thereof, the flash memory 55
The address data indicating the specific area 51a is stored in advance, and the normal read / write operation by the control section 52 is prohibited in this area. Then, in the microcomputer system, the D
When the RAM 50 is used for storing control data during the processing, the normal memory area is assigned to the storage processing. With regard to the special areas 51a, ..., For example, if a part of the storage contents of the hard disk connected to the microcomputer is stored, the RRAM 50 is used for storing control data. Then, it becomes possible to separately use it for the purpose of reading out and storing a part of the data in the hard disk. As described above, in the semiconductor memory device of the fourth embodiment, the RAM is used as the conventional RAM for holding the control data, and a part (special area) thereof is used.
Can be used for separate functions, and high efficiency of the entire system can be achieved. Flash memory is DRAM
50 is formed in a vacant area of the semiconductor chip (for example, a vacant area in a region where peripheral circuits are formed),
A storage capacity of about 1 kbit is sufficient.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the present embodiment, an example in which the rewritable nonvolatile memory is a flash memory has been described, but another EPROM may be used. Further, in the above-mentioned embodiment, the main memory (D
The example in which the RAM or the like) and the sub storage unit (flash memory) are formed on the same semiconductor chip has been described, but they may be formed on different chips and electrically connected to each other. In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor memory device which is the background field of application has been described. However, the present invention is not limited to this, and a semiconductor having a memory portion is used. It can be used for general integrated circuit devices.

[0025]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, by writing desired data in a rewritable nonvolatile memory formed on the same chip as the main memory unit, relief of a defective bit, setting / change of standard specifications relating to read / write operation of a memory mat, DRA
M refresh operation control and the like can be appropriately performed,
The burden on the user is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a structure of a DRAM of a first embodiment.

FIG. 2 is a block diagram showing a procedure for comparing address data of a defective bit and data of an address signal.

FIG. 3 is a block diagram showing a configuration example of a switching circuit of a second embodiment in which a flash memory is used for determining I / O specifications of DRAM.

FIG. 4 is a block diagram showing a configuration example of a refresh drive circuit of a third embodiment in which a flash memory is used for controlling a refresh operation of DRAM.

FIG. 5 is a diagram showing a D of a fourth embodiment in which a flash memory is used for access processing to a special area provided in the memory area.
It is a block diagram which shows the structural example of RAM.

[Explanation of symbols]

 1 Semiconductor Chip 10 Flash Memory (Sub-Memory) 20 DRAM 21A Normal Area 21B Redundant Area 23 Comparison Circuit 23A First Comparator 23B Second Comparator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/82 27/10 471 7210-4M 8122-4M H01L 21/82 R

Claims (3)

[Claims] 1. In an address multiplex type semiconductor memory device in which a redundant circuit is provided in a main memory section, a sub memory section is formed in a rewritable non-volatile memory in the semiconductor chip to identify a defective bit. Defective address data for storing the defective address data is stored in the sub storage unit, and a part of the defective address data is first compared with the upper bits (or lower bits) of the address signal. A semiconductor memory characterized by comprising defective bit judging means for judging defective bit by comparing all or a part of address data with a lower bit (younger upper bit) of an address signal inputted later. apparatus. 2. A semiconductor memory device in which a memory region formed on a semiconductor chip is divided into a plurality of regions, and a drive circuit for raising a word line is provided for each of the divided regions. In the semiconductor memory device described above, a rewritable non-volatile memory is provided, and operation control of the drive circuit is performed based on data stored in the non-volatile memory. 3. A semiconductor memory device comprising a volatile memory whose main memory section is readable / writable, wherein a rewritable non-volatile memory is provided in the semiconductor chip, and the stored contents of the main memory section are stored. A storage / reproduction means for performing a storage / reproduction operation for holding every fixed time, a storage / reproduction operation by the storage / reproduction means are temporarily stopped, and the stopped bit position is stored in the nonvolatile memory, and thereafter, A semiconductor memory device, comprising: a memory reproduction control means for restarting a memory reproduction operation from a bit position.