JPH07114759A - Tracking error detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a tracking error detecting circuit having a simple constitution in which a tracking error detecting gain does not depend on the reproducing level of a head and which is made into IC easily. CONSTITUTION:Only pilot singal components are extracted by eliminating an information signal, etc., from a reproduced signal obtained from a reproducing head 1 wiht a BPF13 and the signal is compared with a prescribed level by a comparator 12 and the signal of level of H or L is outputted. A pilot signal component of an f1 and a pilot signal component of an f2 are detected respectively by a BPF3a having a center frequency being a frequency f1 and an amplitude detecting circuit 4a and by a BPF3b having a center frequency being a frequency f2 and an amplitude detecting circuit 4b and then the deviated direction and the deviated amount of a track being traced at present are detected with high accuracy by obtaining a different signal between these pilot signal components.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracking error detection circuit for a magnetic recording / reproducing apparatus using a pilot signal.

[0002]

2. Description of the Related Art As one of tracking control methods of a helical scan type magnetic recording / reproducing apparatus, a pilot signal and an information signal are multiplexed and recorded, and at the time of reproducing, the reproduced pilot signal is used to control the running of a magnetic tape. Is known, or the head is swung in the track width direction to maintain the relative positional relationship between the head and the track normally. An example of a conventional tracking error detection circuit used in the above tracking control method will be described below with reference to the drawings.

FIG. 12 shows the principle of a conventional tracking control system used in an 8 mm format VTR or the like. In FIG. 12, 116 is a magnetic tape, 104 is a read head, 101 is a main track traced by the read head 104, 102 is a left adjacent track, 103 is a right adjacent track, 105 is a multiplication circuit, and 106 is a reference signal generation circuit. , 107 is a first bandpass filter, 108 is a first amplitude detection circuit, 109 is a second bandpass filter, 110 is a second amplitude detection circuit,
111 is a differential circuit, 115 is a switch, 112 is a capstan control circuit, and 113 is a capstan motor.

The operation of the tracking control system configured as described above will be described below.

In FIG. 12, in addition to information signals such as video signals, the tracks recorded on the magnetic tape 116 are
Four types of tracking pilot signals of f1 to f4 having different frequencies are repeatedly recorded in multiplex in sequence for each track. Here, the frequency difference between the tracks of the pilot signal is
They are chosen to be fh and 3fh respectively. Specifically, f1 = 6.5fh, f2 = 7.5fh, f3 = 1
It is 0.5fh and f4 = 9.5fh.

Now, when the reading head 104 is scanning on the intended main track 101, the reproduction signal from the reading head 104 having a width larger than the track width has a pilot signal f1 = 6.5fh from adjacent tracks on both sides. f3 =
10.5 fh is leaking and crowded. Therefore, the reproduced signal includes a reference signal 7. of the same frequency as the pilot f2 of the main track.
When 5fh is multiplied by the multiplication circuit 105, the pilot components from the tracks on both sides are changed into beat components with frequencies of fh and 3fh. Therefore, by detecting and comparing each amplitude level, the read head 104 is adjacent to either the left or right side. It is possible to detect whether there is a large amount of leaked pilot component leaked from the track, that is, whether the read head 104 is displaced to the left or right.

In practice, the reference signal generating circuit 1 is added to the reproduced signal.
The reference signal from 06 is multiplied by the multiplication circuit 105. A first bandpass filter 107 having a frequency center at fh from the output of the multiplication circuit, and a second bandpass filter having a frequency center at 3fh by the first amplitude detection circuit 108 for detecting the output level of the first bandpass filter 107. 109, the second amplitude detection circuit 110 may detect the 3fh component, and the difference circuit 111 may detect the level difference. Therefore, the output of the difference circuit 111 becomes a relative positional relationship between the head and the main track, that is, a tracking error signal.
Reference numeral 117 is a tracking error detection circuit.

Since the tracking error signal thus obtained has a different polarity for each scan, it is applied to the capstan control circuit 112 with the polarity aligned by the switch 115 according to the head switching signal. The capstan control circuit drives the capstan motor 113 to control the speed of the tape so that the relative positional relationship between the reading head and the target track is maintained correctly. 114 is a reel for winding the tape (for example, Japanese Patent Laid-Open No. 54-350).
(See Japanese Patent Publication No. 7).

[0009]

However, in the above-mentioned structure, the reproduction level of the pilot signal is not limited to the tracking error, but is also affected by the equivalent reactance of the head, the transfer characteristic of the rotary transformer, the variation of the reproduction sensitivity such as the gain of the head amplifier. It will change greatly. Therefore, there is a drawback that the gain of tracking error detection also changes according to the reproducing sensitivity of the head or the like. Therefore, the control performance is deteriorated, and the error detection circuit requires an automatic gain control circuit that changes the detection gain according to the reproduction level of the head.

In view of the above problems, it is an object of the present invention to provide a tracking error detection circuit which has a simple structure, in which the tracking error detection gain does not depend on the reproduction sensitivity of a head or the like, and which can be easily digitized. .

[0011]

In order to solve the above problems, the tracking error detection circuit of the present invention comprises a comparator for comparing the reproduction signal from the head with a predetermined level and outputting an H or L signal. , A level detection circuit for detecting the level of the pilot signal from the output of the comparator.

[0012]

According to the present invention, since the reproduced pilot signal is converted into two levels of H and L by the comparator and the level of the pilot signal is detected by the above structure, a tracking error detection circuit which is not affected by the reproduced level is provided. can do. Further, since it is binarized by the comparator, it is not necessary to use an expensive AD converter in digitizing, and the IC
It is easy to convert.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A tracking error detection circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram of a tracking control system including a tracking error detection circuit according to the first embodiment of the present invention. As in the conventional example, the pilot signal and the information signal are multiplexed and recorded, and at the time of reproduction, the reproduced pilot signal is used to control the running of the magnetic tape or the head is shaken in the track width direction to form a head. This is a system that maintains the relative positional relationship with the track normally. In this example, pilot signals of two frequencies f1 and f2 are sequentially multiplexed every other track.

Now, when the head 1 is scanning over the target main track 2a, the output signal of the reading head 1 having a width larger than the track width is contaminated with pilot signals from adjacent tracks 2c and 2b. There is. Therefore, the relative positional relationship between the main track 2a and the reading head 1 can be known by detecting and comparing the leak levels of the respective pilot signals.

The output of the reading head 1 is input to a comparator 12 after removing signals other than pilot signals, for example, a large part of information signal components, by a bandpass filter 13. The outputs of the comparator 12 are input to the first bandpass filter 3a and the second bandpass filter 3b, respectively. The first bandpass filter 3a and the first amplitude detection circuit 4a are level detection circuits that tune to the frequency f1 of the pilot signal from the left adjacent track 2b and extract its level. Similarly, the second band pass filter 3b and the second amplitude detection circuit 4b are level detection circuits for extracting the level of the pilot signal f2 from the right adjacent track 2c. Therefore, the output of the difference circuit 5 becomes a relative positional relationship between the head and the main track, that is, a tracking error signal. This tracking error signal is input to the capstan control circuit 6, drives the capstan motor 7, and is controlled so that the head comes to the center of the track. Reference numeral 8 is a magnetic tape, and 9 is a reel for winding the tape.

FIG. 2 is a signal waveform diagram of each part in FIG. The input signal 120 to the comparator 12 is, as shown in FIG. 3A, in addition to pilot signals f1 and f2, sliding noise with the tape generated from the head, amplifier noise generated by a head amplifier (not shown), Noise such as low frequency leakage component of the information signal is mixed. The output signal 121 of the comparator 12 is a signal which becomes H when the input is positive and L when the input is negative as shown in (b). B
The signal 122 after passing through the PF 3a is a pilot component in the output signal 121 of the comparator 12, as shown in (c). Since the output of the comparator 12 is density-modulated according to the magnitude of the pilot component by the pilot component and the noise component described above, the output levels of the digital level detection circuits of f1 and f2 are the same as those of the comparator input. It changes according to the pilot level of.

FIG. 3 shows the positional relationship between the head and each track and the spectrum of the comparator input at that time.
In (a), the f1 component becomes large due to the left side of the head.
Two components are reduced, (b) the head is in the center of the target track and each pilot level is balanced, (c) the head is shifted to the right, and the f1 component is the opposite of (a). This is a state in which the f2 component has decreased and the f2 component has increased. That is, it can be seen that the S / N ratio of each pilot changes complementarily due to the tracking error.

FIG. 4 is a graph obtained by actually measuring the relationship between the pilot input S / N ratio of the comparator and the level of the pilot frequency component of the comparator output. From this figure, it can be seen that the level of the pilot component of the comparator output is proportional to the S / N ratio of the input pilot when some noise is present. That is, when there is some noise in the input, the tracking error can be detected even if the input signal is converted into a binary value of H and L by the comparator. At this time, the output of the comparator is irrelevant to the input signal level, so that even if the reproduction level from the head changes, the detection gain is not affected. A limiter circuit that sufficiently amplifies the input signal and limits the amplitude may be used as the comparator.

FIG. 5 is a graph showing the frequency spectrum of the output of the comparator 12. Since the operation of the comparator is non-linear, the input harmonic components (2f1, 3f) are generally output.
, ..., 2f2, 3f2, ...) and intermodulation components (f2-f1, f1 + f2, 2f1 + f2, ...) Appear.

Even when there is no noise or very small noise at the input, the two pilot signals change in a complementary manner as shown in FIG. 3, so the pilot component at the output of the comparator similarly has the input level of each pilot. It changes according to the ratio. FIG. 6 is an actual measurement diagram showing each input pilot level ratio and each pilot component of the output of the comparator. Therefore, even in such a case, the tracking error can be detected. or,
Since the output of the comparator is determined by the input level ratio of each pilot, the detection gain is not affected even if the reproduction level from the head changes, regardless of the input signal level, as described above.

In the above description, the structure of the level detection circuit is not limited to this embodiment, and may be, for example, a synchronous detection type detection circuit. If the output of the comparator is discretized with an appropriate clock using a D flip-flop circuit or the like,
It is also easy to detect the level of the pilot signal with a digital circuit.

FIG. 7 shows the configuration of a tracking error detection circuit according to the second embodiment of the present invention. Components having the same functions as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The signal passed through the band pass filter 13 is
After being converted into H and L digital signals by the comparator 12, they are discretized by the sampling circuit 200. 21
Reference numeral 4 is a clock generation circuit that generates a sampling clock. The output of the sampling circuit is input to the digital level detection circuits 201a and 201b of f1 and f2, respectively, to detect the pilot signal component, and the difference circuit 202
In order to obtain the tracking error signal, the difference between them is calculated.

The frequency of the sampling clock of the sampling circuit 200 is set in consideration of the subsequent level detection processing.
It is convenient to choose a common multiple of each pilot frequency. The sampling circuit 200 may simply use a D flip-flop and synchronize the output of the comparator with the sampling clock described above.

As shown in FIG. 5, the output of the comparator has a wider frequency band than that of the input because of the presence of harmonic components and intermodulation components. Therefore, when the sampling frequency is low, aliasing distortion occurs, so it is necessary to select a sampling frequency that is high to some extent. Therefore,
The operating frequency of the level detection circuit that will be connected later also increases,
In some cases, it may not be preferable in terms of hardware scale and power consumption.

FIG. 8 shows a third embodiment of the tracking error detection circuit of the present invention. Components having the same functions as those in the second embodiment are designated by the same reference numerals and the description thereof will be omitted. After the comparator output is synchronized by the D flip-flop 210 using the high-frequency clock CK1, the harmonic component is converted by the digital low-pass filter 211.
The intermodulation component and the high frequency component of the quantization noise are removed, and the latch circuit 212 resamples at a frequency lower than CK1. According to this configuration, since sampling is performed at a high frequency, it is unlikely to be affected by aliasing distortion, and re-sampling is performed after filtering, so that the effect of quantization noise is reduced. Furthermore, because it is latched with a low clock, subsequent processing is easy,
It has a remarkable effect on reduction of hardware scale and power consumption.

FIG. 9 shows a concrete example of the configuration of the digital LPF 211 shown in FIG. D flip-flops D ₁ , D ₂ , D
_3, · · ·, D _n, the delay element is delayed driven by the clock CK1 time _{T, a 1, a 2,} a 3, ···, a n is a coefficient multiplier, FIR filter in the addition circuit 230 Is configured.

FIG. 10 shows a fourth embodiment of the tracking error detection circuit of the present invention. When the output of the D flip-flop 210 for sampling the output of the comparator 12 is H, the counter 310 is counted up by the clock CK1. . The clock CK1 is divided by the frequency dividing circuit 213 in a division ratio m (m is an integer).
Is divided by and becomes the clock CK2. The output of the counter 310 is sent to the first latch circuit 311 and the first latch circuit 311.
The output of 11 is latched by the second latch circuit 312 by the clock CK2. The difference between the outputs of the latch circuit 311 and the latch circuit 312 is calculated by the difference circuit 313.
That is, since the output of the latch circuit 312 is the value of the counter latched last time, the output of the difference circuit 313 is CK.
2 is an average value of the lengths of H and L periods of the comparator included in one cycle of 2. In other words, the output of the comparator is equivalent to being converted into the rate of the clock CK2 through the LPF by averaging. Therefore, even in this configuration, the output of the comparator is sampled at a high clock and is not affected by aliasing noise. LPF by averaging
Since it is resampled to a low rate through, the subsequent processing is simplified, and it is effective in reducing power consumption and hardware scale.

The operation principle of an example of the digital level detection circuits for f1 and f2 described in the second, third and fourth embodiments will be described below with reference to FIG. 11 in which the level of f1 is detected. Explained.

Reference numeral 25 is a reference signal generator connected to a clock CK1 for sampling the output of the comparator, and outputs a signal of the same frequency f ₁ 'as the reproduction pilot f ₁ . Among them, 25a and 25b serve as first and second reference signal generators, respectively, and output two-phase signals having frequencies f ₁ 'which are 90 degrees out of phase with each other. Clocks CK1 and CK
If 2 is selected in advance as an integral multiple of the pilot frequency,
The configuration of the reference signal generator becomes very simple. For example,
When CK2 is selected to be four times the pilot frequency, the output of the first reference signal generator 25a is 0, 1, 0, -1, ...
.. Also, the output of the second reference signal generator is 1, 0,-
It is a simple repetition of 1, 0, ... And can be configured only with a counter and a decoder using CK1 as a clock. The outputs D _1a and D _1b of the first and second reference signal generators 25a and 25b are expressed by the following equations, respectively.

[0032] _{D 1a = sin (2πf 1 '} t) D 1b = cos (2πf 1' t) 20a is a first multiplier, and an output D _1a of the input signal and the first reference signal generator 25a Multiply. Also, 20
b is a second multiplier, which similarly multiplies the input signal by the output D _{1b of} the second reference signal generator 25b. Now, assuming that the pilot f ₁ component H ₁ of the input signal is H ₁ = A ₁ sin (2πf ₁ t) (where A _{1 is the} pilot f ₁ amplitude and t is the time), the output of the first multiplier 20 a M _1a is given by the following equation.

[0033] _{M 1a = H 1 × D 1a} = A 1/2 {cos (2πf 1 t-2πf 1 't) -cos (2πf 1 t + 2πf 1' t)} = A 1/2 {cos (θ 1) _{-cos (2πf 1 t + 2πf 1} 't)} Further, the output M _1b of the second multiplier 20b is given by the following equation.

[0034] _{M 1b = H 1 × D 1b} = A 1/2 {sin (2πf 1 t-2πf 1 't) + sin (2πf 1 t + 2πf 1' t)} = A 1/2 {sin (θ 1) + sin (2πf ₁ t + 2πf ₁ ′ t)} where θ ₁ represents the phase difference between the reproduction pilot f ₁ and the output clocks f ₁ ′ of the first and second reference signal generators. Here, if CK2 is selected to be an integral multiple of f1 ', for example, four times as in the previous case, the reference signals to be multiplied are only 1, 0, and -1, so that the multiplication circuit becomes very simple.

Reference numeral 21a is a first low pass filter,
Only the low frequency signal of the output M _1a of the first multiplier 20a is transmitted. Similarly, 21b is a second low pass filter, which passes only the low band of the output M _1b of the second multiplier 20b. Therefore, the output L of the first low pass filter 21a
_1a transmits only the first term of the above M _1a , and the second term
The output L _1b of the low-pass filter 21b of 1 passes through only the first term of the above M _1b . That is, the _{L 1a = A 1/2 {} cos (θ 1)} L 1b = A 1/2 {sin (θ 1)}. Therefore, the outputs of the above-mentioned first and second low-pass filters are respectively calculated by squaring operation circuits 22a and 2a as follows.
2b, the signals are squared, added together by the adder circuit 23, and routed by the route calculation circuit 24. As a result, the output P _D1 of the first pilot detector 201a is a component of 1/2 of the amplitude of the reproduced pilot f _1. Is obtained.

[0036] ^{_{P D1 = (L 1a 2 +}} L 1b 2) 1/2 = A 1/2 or more is described in the example of the frequency f1, digital level detecting circuit of the frequency f2 is the same. Each detected pilot level is subtracted by the difference circuit 202, resulting in a tracking error that is positive or negative in accordance with the relative positional deviation between the head and the track.

As described above, in the tracking error detection circuit of the present invention, since the binary signal of H and L is converted by the comparator, the detection gain is not affected by the reproduction sensitivity from the head. Further, by selecting the clock as an integral multiple of the pilot frequency, it becomes easy to digitize it as in this embodiment.

In this embodiment, the error detection circuit after the comparator is digitized, but the capstan control circuit can also be digitally processed by using a CPU or the like.

The structure of the level detection circuit is not limited to this embodiment, and may be, for example, a synchronous detection type detection circuit.

As described above, in the embodiment of the present invention, unlike the conventional case, the level detecting circuit does not require large externally attached / adjusting elements such as coils and capacitors, and the error detecting circuits after the comparator are all digital circuits. Therefore, it is highly resistant to variations and can be easily integrated into an IC.

Further, since expensive components such as an AD converter and the like are not required and the comparator and the D flip-flop can be simply digitized, the configuration can be made very cheaply.

The method of inserting the pilot signal is not limited to the case of adding to the information signal and frequency-multiplexing as in the above-described embodiment. For example, in the case of digital recording, the information signal is modulated to obtain 1, 0. It is also possible to change the density depending on the location and to construct the pilot component in the low frequency range. Moreover, it is not always necessary to multiplex the pilot signal over the entire track.

Further, the pilot frequency is a system in which four kinds of pilots are sequentially multiplexed like the 8 mm format,
Alternatively, as in the case of DAT, one type of pilot signal may be changed in location and time-multiplexed on a track, and each pilot level may be sampled and used. The method and number of pilot signals are not limited. Particularly, in the system using one type of pilot such as DAT, only one level detection circuit is required.

[0044]

As described above, the present invention includes a comparator for comparing the reproduced signal from the head with a predetermined level and outputting H and L signals, and a sampling circuit for sampling the output of the comparator. And a level detection circuit for detecting the pilot level from the output of the sampling circuit, the tracking error detection circuit which is not dependent on the reproduction level of the pilot signal and can be easily integrated into an IC. it can.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a tracking control system using a tracking error detection circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part in the first embodiment of the present invention.

FIG. 3 is a diagram showing a positional relationship between a head and each track and a spectrum of a comparator input at that time.

FIG. 4 is a diagram showing a relationship between a pilot S / N ratio of a comparator input and a pilot component of a comparator output.

FIG. 5 is a diagram showing a frequency spectrum of a comparator output.

FIG. 6 is a diagram showing a relationship between a pilot level ratio of a comparator input and a pilot component of a comparator output.

FIG. 7 is a configuration diagram of a tracking error detection circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a tracking error detection circuit according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a digital LPF according to a third embodiment.

FIG. 10 is a configuration diagram of a tracking error detection circuit according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing an example of a digital level detection circuit according to the present invention.

FIG. 12 is a principle diagram of a conventional tracking control method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 read head 2a-2c track 13 band pass filter 12 comparator 200 sampling circuit 211a, 201b digital level detection circuit 202 difference circuit

Front page continuation (72) Inventor Kenichi Honjo 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Makoto Goto 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (9)

[Claims] 1. A magnetic reproducing apparatus which is formed obliquely with respect to a longitudinal direction of a magnetic tape, and in which a head is sequentially rotationally scanned and reproduced from a track on which a pilot signal is selectively multiplex-recorded together with an information signal. And a level detection circuit for detecting the level of the pilot signal from the output of the comparator. Tracking error detection circuit. 2. A magnetic reproducing apparatus which is formed obliquely with respect to a longitudinal direction of a magnetic tape, and in which a head is sequentially rotationally scanned and reproduced from a track on which a pilot signal is selectively multiplex-recorded together with an information signal. Comparing the reproduced signal of 1 with a predetermined level and outputting a binary signal of H and L, a clock generating circuit for generating a clock, and a sampling circuit for discretizing the output of the comparator with the clock. And a level detection circuit for detecting the level of the pilot signal from the output of the sampling circuit. 3. The tracking error detection circuit according to claim 2, wherein the clock frequency of the clock generation circuit is selected to be an integral multiple of the pilot frequency. 4. A magnetic reproducing apparatus which is formed obliquely with respect to the longitudinal direction of a magnetic tape and in which a head is sequentially rotationally scanned and reproduced from a track on which a pilot signal is selectively multiplex-recorded together with an information signal. Of the reproduction signal of (1) is compared with a predetermined level to output a binary signal of H and L, a first clock generation circuit for generating a first clock, and an output of the comparator is input to the first clock generation circuit. A first sampling circuit that discretizes with one clock; and a low-pass filter that inputs the output of the first sampling circuit,
A frequency dividing circuit for dividing the first clock to generate a second clock, a second sampling circuit for re-sampling the output of the low pass filter with the second clock, and the second sampling A tracking error detection circuit comprising a level detection circuit for detecting the level of a pilot signal from the output of the circuit. 5. The tracking error detection circuit according to claim 4, wherein the frequency of the second clock is selected to be an integral multiple of the pilot frequency. 6. A magnetic reproducing apparatus which reproduces by rotationally scanning a head sequentially from a track which is formed obliquely with respect to the longitudinal direction of a magnetic tape and on which a pilot signal is selectively multi-recorded together with an information signal. A reproduction signal from the head is compared with a predetermined level to output a binary signal of H and L, a first clock generating circuit for generating a first clock, and an output of the comparator is input. Then, a first sampling circuit that discretizes with the first clock, a counter that counts up or down with a period of H of the output of the sampling circuit with the first clock, and the first clock is divided. A frequency dividing circuit for generating a second clock, and a differential circuit for latching the output of the counter based on the second clock and taking a difference from the previous latch output. Tracking error detection circuit, characterized by comprising a level detecting circuit for detecting the level of the pilot signal from the output of the differential circuit. 7. The tracking error detection circuit according to claim 6, wherein the frequency of the second clock is selected to be an integral multiple of the pilot frequency. 8. A level detection circuit includes first and second reference signal generation circuits for generating signals having phases different from each other by 90 degrees from a first clock, an output of a difference circuit, and the first and second reference signals. First to multiply the outputs of the signal generation circuit,
A second multiplication circuit, first and second low-pass filters for extracting only low-pass components from the outputs of the first and second multiplication circuits, and the first and second low-pass filters, respectively. The first and second squaring circuits for squaring the outputs of the pass filters, the adder circuit for summing the outputs of the first and second squaring circuits, and the output of the summing circuit are set to 1 7. The tracking error detection circuit according to claim 6, wherein the tracking error detection circuit is composed of a root calculation circuit that squares / 2. 9. A magnetic reproducing apparatus for obliquely forming a tape with respect to a longitudinal direction of a magnetic tape, wherein the head is sequentially rotationally scanned and reproduced from a track on which a pilot signal is selectively multiplex-recorded together with an information signal. And a comparator for outputting a binary signal of H and L whose pulse width changes according to the pilot level in the reproduced signal, and the level of the pilot from the output of the comparator. And a level detection circuit for detecting a tracking error detection circuit.