JPH04276345A - Tracking error detecting circuit - Google Patents

Abstract

PURPOSE:To cope with variations of parts in specification and to easily promote a filter in Q and then to follow even a fluctuation of a regenerative pilot fre quency. CONSTITUTION:An n-phase signal of the same frequency as each detecting pilot signal is generated by an n-phase signal generating means 2, and similarly an m-phase signal by an m-phase signal generating means 3. These signals are multiplied by a regenerative signal S respectively by 1st and 2nd multiplication circuit groups 4 and 5, and their low band components are extracted by 1st and 2nd low band pass filter groups 6 and 7, and then absolute values are calculated by 1st and 2nd absolute value calculation circuit groups 8 and 9. These calculated results are added by 1st and 2nd addition circuits 10 and 11 respectively, and these output are compared by a difference circuit 12.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracking error detection circuit for a magnetic recording/reproducing apparatus using a pilot signal.

0002

[Prior Art] As one of the tracking control methods for a helical scan type magnetic recording/reproducing device, a pilot signal and an information signal are multiplexed and recorded, and during reproduction, the reproduced pilot signal is used to control the running of a magnetic tape. Alternatively, a method is known in which the relative positional relationship between the head and the track is maintained normally by swinging the head in the track width direction. An example of a conventional tracking error detection circuit used in the above-described tracking control method will be described below with reference to the drawings.

FIG. 5 shows the principle of tracking error detection, and FIG. 6 shows the basic configuration of a conventional tracking error detection circuit. In FIG. 5, 101 is a main track, 102 is a left adjacent track, 103 is a right adjacent track, and 104 is a read head. Also (Figure 6)
105 is a first band-pass filter, 106 is a first amplitude detection circuit, 107 is a second band-pass filter, 108 is a second amplitude detection circuit, and 109 is a difference circuit.

The operation of the tracking error detection circuit configured as described above will be explained below.

In FIG. 5, the left adjacent track 102
, and the right adjacent track 103, in addition to the information signal, pilot signals of different frequencies are frequency-multiplexed and recorded. Now, when the read head 104 is scanning over the main track 101, the output signal from the read head 104, which is larger than the track width, is contaminated with pilot signals from adjacent tracks on both sides. Therefore, by detecting and comparing the leakage levels of the respective pilot signals, the relative positional relationship between the main track 101 and the reading head 104 can be known. In FIG. 6, the first band pass filter 105 and the first amplitude detection circuit 106 function to tune to the frequency of the pilot signal from the left adjacent track and extract its level, for example. Similarly, a second bandpass filter 107,
A second amplitude detection circuit 108 extracts the pilot signal level from the right adjacent track. Therefore, the differential circuit 109
The output indicates the relative positional relationship between the head 4 and the main track 101, that is, a tracking error signal (see, for example, Japanese Patent Application Laid-Open No. 54-3507).

[0006]

[Problems to be Solved by the Invention] However, with the above configuration, it is difficult to increase the band Q of the band-pass filter, there are large variations in the filter, and when the relative speed of the head and tape changes during special playback, the playback pilot may be affected. It had problems such as frequency shift and difficulty in converting it into an IC.

In view of the above-mentioned problems, it is an object of the present invention to provide a tracking error detection circuit that is resistant to component variations, can easily increase the Q of the filter, and can follow fluctuations in the reproduced pilot frequency. purpose.

[0008]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the tracking error detection circuit of the present invention includes a clock generating means, and generates an n-phase signal of a first frequency from an output signal of the clock generating means. n-phase signal generation means, a first multiplication circuit group that performs a multiplication operation of n output signals from the n-phase signal generation means and a reproduced signal, and n outputs from the first multiplication circuit group. a first low-pass filter group for extracting each low-pass component of the signal; and a first low-pass filter group for calculating the absolute value of each of the n outputs from the first low-pass filter group.
a first adding circuit that calculates the sum of n output signals from the first absolute value calculation circuit group; and m phases of a second frequency from the output signal of the clock generation means. m-phase signal generating means for generating a signal; and a second circuit for performing a multiplication operation between the m output signals from the m-phase signal generating means and the reproduced signal.
a second low-pass filter group that extracts the low-frequency components of each of the m output signals from the second multiplier circuit group; a second absolute value calculation circuit group that calculates the absolute value of each of the m outputs; a second addition circuit that calculates the sum of the m output signals from the second absolute value calculation circuit group; The second adder circuit includes a difference circuit that calculates the difference between the output of the first adder circuit and the output of the second adder circuit.

[0009]

[Operation] With the above-described configuration, the present invention can eliminate the band-pass filter conventionally made using a resonant circuit.
It is resistant to variations, and the equivalent Q can be increased freely using the output low-pass filter. Further, by configuring the clock generating means from a PLL circuit that generates a clock synchronized with the reproduced signal from the reproduced signal, it is possible to provide a tracking error detection circuit that can follow fluctuations in the reproduced pilot frequency. Further, by providing a circuit for adjusting the output level of the first or second adding circuit, it is possible to absorb differences in frequency characteristics of each pilot frequency of the recording/reproducing system.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A tracking error detection circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of a tracking error detection circuit according to an embodiment of the present invention. (FIG. 1), 1 is a clock generation means, 2 is an n-phase signal generation means, 3 is an m-phase signal generation means, 4 is a first multiplication circuit group, 5 is a second multiplication circuit group, and 6 is a first multiplication circuit group. 7 is a second low-pass filter group, 8 is a first absolute value calculation circuit group, 9 is a second absolute value calculation circuit group, 10 is a first
11 is a second addition circuit, and 12 is a differential circuit.

The operation of the tracking error detection circuit configured as described above will be explained below using (FIG. 1) and (FIG. 2).

From the output of the clock generating means 1, the n-phase signal generating means 3 outputs an n-phase signal having substantially the same frequency as the pilot signal recorded on the left adjacent track. Now, of the reproduced signal, the pilot component from the left adjacent track is
1SIN(ω1t+θ), and one of the outputs of the n-phase signal generating means 3 is SIN(ω1t+φ), then the output of the corresponding multiplier circuit of the first multiplier circuit group is A1SIN(ω1t+θ)×SIN(ω1t+φ)
=-0.5A1{COS(2ω1t+θ+φ)-COS
(θ−φ)}. The first term is a high signal component and is attenuated by a corresponding low-pass filter of the first low-pass filter group 6 that is connected next. Therefore, the output of this low-pass filter has the amplitude A of the input pilot.
A DC signal of 0.5A1COS (θ-φ) proportional to 1 is obtained. However, since the level of this signal changes depending on the phase of the input pilot signal, this does not mean that the amplitude of the input pilot has been detected. However, since the output of each low-pass filter is shifted according to the phase of the output of the n-phase signal generating means 3, the output of this low-pass filter is inputted to the first absolute value calculation circuit group 8, If the sum of each n outputs is collected by the first adding circuit 10, it is possible to suppress level fluctuations due to the phase of the input pilot signal.

FIG. 2 is a diagram showing the principle of FIG. 1, and shows the state of the signal at each point with respect to the phase of the input pilot signal when n=3. 201, 202, and 203 are the outputs of the first low-pass filter group, and 204 is the output of the first adder circuit 10. As in this example, when n=3, it is approximately 1.2 dB
The output fluctuation can be suppressed to . Further, when n=4, the output fluctuation can be suppressed to about 0.4 dB, and n can be selected according to the required specifications.

Similarly, the pilot component from the adjacent track on the right is transmitted to the m-phase signal generating means 3, the second multiplier circuit group 5, the second low-pass filter group 7, and the second absolute value calculation circuit group 9.
, can be similarly detected by the second addition circuit 11. At this time, the frequency of the m-phase signal generating means 3 may be approximately matched to the pilot frequency of the right adjacent track. The detection level of each pilot signal obtained in this way, that is, the output of the first adder circuit 10 and the second adder circuit 11, is input to the difference circuit 12 and the difference is taken, thereby extracting the tracking error signal. Can be done.

As described above, according to this embodiment, an equivalent band-pass filter determined by the cutoff frequencies of the first and second low-pass filters is realized, so there is little variation in the filters, and the circuit configuration is improved. It is possible to obtain the effects of easily increasing the Q and making it easy to integrate into an IC.

A second embodiment of the present invention will be described below with reference to the drawings. (FIG. 3) is another configuration diagram of the clock generating means 1 of the tracking error detection circuit showing the second embodiment of the present invention. In this example, a PLL circuit is used to synchronize the clock with the reproduced signal, and the center frequency in synchronous detection follows fluctuations in the reproduced pilot frequency. Therefore, the equivalent Q can be set higher, and a tracking error detection circuit that is stable even during special playback can be achieved.

(FIG. 4) is a configuration diagram of the first addition circuit 10 of the tracking error detection circuit showing a third embodiment of the present invention. (FIG. 4), 401 is an adder circuit, 402
is a level adjustment circuit. In this example, a level adjustment circuit 402 that adjusts the output level of the first adder circuit 10
By providing this, it is possible to adjust the pilot level from the adjacent track on the left, and it is possible to absorb differences in frequency characteristics of each pilot frequency of the recording/reproducing system.

In the first embodiment, the n-phase signal generating means 2 and the m-phase signal generating means 3 do not have to have the same number of phases, but may have different numbers of phases. Further, the phases between each phase do not need to be exactly evenly spaced.

Furthermore, in the third embodiment, the first addition circuit is provided with a level adjustment circuit for adjusting its output level, but it goes without saying that the same effect can be obtained even if the second addition circuit is provided with a level adjustment circuit. stomach.

[0021]

As described above, the present invention provides a clock generating means, an n-phase signal generating means for generating an n-phase signal of a first frequency from an output signal of the clock generating means, and a clock generating means for generating an n-phase signal of a first frequency. a first multiplier circuit group that performs a multiplication operation between the n output signals from the means and the reproduced signal; and a first multiplier circuit group that extracts low-frequency components of each of the n output signals from the first multiplier circuit group. 1 low-pass filter group, a first absolute value calculation circuit group that calculates the absolute value of each of the n outputs from the first low-pass filter group, and the first absolute value calculation circuit. a first adder circuit that sums n output signals from the group; m-phase signal generating means that generates an m-phase signal of a second frequency from the output signal of the clock generating means; and the m-phase signal. a second multiplier circuit group that performs a multiplication operation between the m output signals from the generating means and the reproduced signal; and extracting low-frequency components of each of the m output signals from the second multiplier circuit group. a second low-pass filter group; a second absolute value calculation circuit group that calculates the absolute value of each of the m outputs from the second low-pass filter group; and the second absolute value calculation By comprising a second addition circuit that takes the sum of m output signals from the circuit group, and a difference circuit that calculates the difference between the output of the first addition circuit and the output of the second addition circuit, It is possible to eliminate the band-pass filter conventionally used in a resonant circuit, and it is resistant to variations, and the equivalent Q can be freely increased using the output low-pass filter.

Furthermore, by configuring the clock generating means from a PLL circuit that generates a clock synchronized with the reproduced signal, it is possible to provide a tracking error detection circuit that can follow fluctuations in the reproduced pilot frequency. Also, the first
Alternatively, by configuring the second adder circuit to include a level adjustment circuit that adjusts its output level, differences in frequency characteristics of each pilot frequency of the recording/reproducing system can be absorbed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a tracking error detection circuit in one embodiment of the present invention.

FIG. 2 is a principle diagram for explaining the operation in the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a clock generating means of a tracking error detection circuit showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a first addition circuit of a tracking error detection circuit showing a third embodiment of the present invention.

FIG. 5 is a diagram showing the principle of tracking error detection.

FIG. 6 shows a basic configuration diagram of a conventional tracking error detection circuit.

[Explanation of symbols]

1 Clock generation means 2 N-phase signal generation means 3 M-phase signal generation means 4 First multiplication circuit group 5 Second multiplication circuit group 6 First low-pass filter group 7 Second low-pass filter group 8 First absolute value calculation circuit group 9 Second absolute value calculation circuit group 10 First addition circuit 11 Second addition circuit 12 Differential circuit

Claims (3)

[Claims] Claim 1: A rotary head reproduces a track formed obliquely with respect to the longitudinal direction of the magnetic tape and in which a pilot signal is multiplexed with an information signal, and the rotary head reproduces and scans tracks on both sides of the main track to be scanned for reproduction. A tracking error detection circuit that generates a tracking error signal for correcting a deviation in the scanning locus of the rotary head with respect to the main track based on a level difference between respective pilot signals reproduced from the tracks, the tracking error detection circuit includes a clock generating means; n-phase signal generation means for generating an n-phase signal of a first frequency from the output signal of the generation means; and a first multiplication operation for multiplying the n output signals from the n-phase signal generation means and the reproduced signal. a first low-pass filter group for extracting low-frequency components of each of the n output signals from the first multiplication circuit group; a first absolute value calculation circuit group that calculates the absolute value of each of the outputs; a first addition circuit that takes the sum of n output signals from the first absolute value calculation circuit group; and the clock generation means. m to generate an m-phase signal of a second frequency from the output signal of
phase signal generation means, a second multiplication circuit group that performs a multiplication operation of the m output signals from the m-phase signal generation means and the reproduced signal, and m output signals from the second multiplication circuit group. a second low-pass filter group for extracting low-pass components of each of;
a second absolute value calculation circuit group that calculates the absolute value of each of the m outputs from the second low-pass filter group; A tracking error detection circuit comprising: a second addition circuit that calculates a sum; and a difference circuit that calculates a difference between an output of the first addition circuit and an output of the second addition circuit. 2. The tracking error detection circuit according to claim 1, wherein the clock generation means comprises a PLL circuit that generates a clock synchronized with the reproduced signal. 3. The tracking error detection circuit according to claim 1, wherein the first or second addition circuit includes a level adjustment circuit that adjusts the level of the output thereof.