JPH07114511A - Inter-memory data transfer device and its data transfer method - Google Patents

Abstract

PURPOSE:To enable fast inter-memory data transfer by sufficiently bringing out the throughput that the device itself has latently. CONSTITUTION:In a DMAC(direct access controller) 10', an FIFO(first-in first- out) memory 30 which can be stored by a certain amount is provided, an address for data reading is outputted to the memory 1 to repeatedly read data out, and a certain amount of data are stored within the range of the capacity of the FIFO memory 3. Then an address for data writing is outputted to the memory 2 and writing operation is repeated by as many as the data stored in the FIFO memory 30 in synchronism with the timing of said output, thereby transferring the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-memory data transfer device used in a computer or the like, and more particularly to an inter-memory data transfer device capable of performing high-speed data transfer between memories and a data transfer method thereof.

[0002]

2. Description of the Related Art First, a conventional inter-memory data transfer device will be described with reference to FIG. FIG. 10 is a configuration block diagram of a conventional inter-memory data transfer device. As shown in FIG. 10, a conventional memory-to-memory data transfer device includes two memories 1 and 2 and a DMAC (Direct Memory Controller) that controls access to the memories.
10 and a system bus 20 connecting the DMAC 10 and the memories 1 and 2.

An address counter (Memory Address) of a data read destination is provided inside the DMAC 20.
Counter (hereinafter referred to as MAC) 11 and an address counter (Destination Addre) of a data write destination
ss Counter (hereinafter referred to as DAC) 12 and a data buffer 15 for storing one-time data of memory input / output
And a transfer counter (Transmission Counter, hereinafter TC)
16), a control unit 19 for controlling the MAC 11, the DAC 12, the data buffer 15, and the TC 16.

Next, the function of each part will be specifically described.
The memory 1 is a memory for reading data in the memory-to-memory data transfer, the memory 2 is a memory for writing data, and the system bus 20 connects the memories 1 and 2 and the DMAC 10 to store addresses and data. It is to be transferred.

The DMAC 10 is the system bus 2
A controller that controls access to the memories 1 and 2 through 0, an internal MAC 11 is a counter that sets a read address of the memory 1, and a DAC 12 is
The data buffer 15 is a counter for setting the write address of the memory 2, the data buffer 15 is a data buffer for one transfer for temporarily storing the data read from the memory 1, and the TC 16 is a counter for counting the number of transfer data. .

The control section 19 is a section for controlling each counter and the data buffer 15, and more specifically, T
Addresses of the memories 1 and 2 corresponding to the number of transfer data counted in C16 are set in the MAC 11 and the DAC 12 and supplied to the memories, and further, input / output to / from the data buffer 15 is controlled via the system bus 20. It is like this.

Next, a data transfer method in the conventional memory-to-memory data transfer device will be described with reference to FIG.
FIG. 11 shows D- in the conventional memory-to-memory data transfer device.
It is a schematic explanatory drawing which shows the data transfer method between RAMs.

In the data transfer method of the conventional memory-to-memory data transfer device, when transferring data from the memory 1 to the memory 2, the control unit 19 of the DMAC 10 counts up the TC 16 and the memory 1 corresponding to the value of the TC 16 is transferred. Is set in the MAC 11 and is supplied to the memory 1 via the system bus 20. The memory 1 reads the data from the supplied address and outputs the data to the system bus 20. A data read operation for fetching data from the memory and storing it in the data buffer 15,
The control unit 19 sets the address of the memory 2 in the DAC 12 according to the value of the TC 16 and supplies the address to the memory 2 via the system bus 20.
The data write operation of outputting data to the bus 20, the memory 2 fetching the data from the system bus 20, and writing the data to the supplied address is alternately repeated.

The address of the memory 1 set in the MAC 11 and the address of the memory 2 set in the DAC 12 are
It is set in advance in a table or the like managed by the control unit 19, and upon the count-up of the TC 16, the control unit 19 reads the address of this table and sets it in the MAC 11 or the DAC 12. Specifically, when the control unit 19 of the DMAC 10 receives an instruction as to which portion of the memory 1 to transfer data to which portion of the memory 2, the address of the memory 1 is set in the table portion for the MAC 11, and the DAC 12 The address of the memory 2 is set in the table portion for use, and thereafter, the address is sequentially set in the MAC 11 or the DAC 12 while referring to this table.

Here, the memories 1 and 2 are a D-RAM (Dynamic-RA) used exclusively for a large-capacity memory device.
If it is M), two addresses, a column address and a row address, are used as MAC addresses in the MAC 11
And DAC 12 must be set.

Therefore, by using the conventional data transfer method, D
When performing data transfer between RAMs, as shown in FIG. 11, the control unit 19 of the DMAC 10 first sets the column address of the data read destination of the memory 1 in the MAC 11 and sends it via the system bus 20, Next, when the row address is set and sent, the memory 1 reads the data from the address designated by the column address and the row address and outputs it to the system bus 20, and the control unit 19 fetches this data and stores it in the data buffer 15. Store.

Then, the column address of the data write destination of the memory 2 is set in the DAC 12 and the system
Data is output from the data buffer 15 to the system bus 20 by sending the data via the bus 20, then setting and sending the row address, and the memory 2 fetches the data from the system bus 20 and uses the column address and the row address. It is designed to write data to the specified address,
After that, a series of operations are similarly repeated.

In the D-RAM, a block (page) which is a physical access unit is supported in order to support reduction of the cycle time of sequential memory access.
There is a high-speed page mode that enables unit operation, and in the high-speed page mode, for example, when sequentially accessing the data portion indicated by consecutive column addresses on the same row address, once set the row address, Sequential high-speed memory access is possible by continuously setting only column addresses that change.

Next, the conventional memory-to-memory data transfer device D
The operation of the control unit 19 in the MAC 10 will be described with reference to FIGS. FIG. 12 is a flowchart showing the flow of the operation of the conventional control unit 19. The conventional control unit 19 first clears TC16 (100), and then TC
Add 1 to 16 (110) and MAC address of memory 1
11 is set (112), the value of the MAC 11 is output to the system bus 20 (114), data is input from the system bus 20 (116), and the data is stored in the data buffer 15 (118).

Then, the address of the memory 2 is set to the DAC 12
(120), the value of the DAC 12 is output to the system bus 20 (122), the data is output from the data buffer 15 to the system bus 20 (124), and it is determined whether or not all data has been transferred. Then (130), if not completed, the process returns to step 110. If the data transfer is completed, the process ends.

[0016]

However, in the above-described conventional memory-to-memory data transfer device and data transfer method thereof, since transfer data is temporarily stored in the data buffer 15 in the DMAC 10, direct data transfer between the memory and the memory is not possible. Compared with this, there is a problem that the transfer time is more than twice as long and the transfer speed is slow.

Further, even when the memories 1 and 2 are D-RAMs capable of operating in the high speed page mode, since data is transferred for each data for one address, alternate access 1 to both memories is performed. Since the row address and the column address must be set every time, the high speed access in the high speed page mode cannot be utilized, and there is a problem that the processing capacity that the device itself has potentially cannot be fully utilized. It was

The present invention has been made in view of the above circumstances, and a memory-to-memory data transfer apparatus and a memory-memory data transfer apparatus capable of realizing a high-speed data transfer between memories by sufficiently utilizing the processing capacity of the apparatus itself. The purpose is to provide a data transfer method.

[0019]

According to a first aspect of the present invention for solving the problems of the conventional example, a first memory for storing data to be transferred and a second memory for transferring the data are provided. A data read address is output to the memory and the first memory, data of the data read address portion is read from the first memory, a data write address is output to the second memory, and the read data is stored. An inter-memory data transfer device comprising: a memory access controller for writing in the data write address portion of the second memory; and a system bus connecting the memory access controller and the first and second memories. A FIFO memory for storing a fixed amount of data is provided in the access controller, and the memory access controller is provided. The tracker repeats the output of the data read address and the reading of the data from the first memory to store the data in the FIFO memory, and the FIFO is synchronized with the timing of outputting the data write address to the second memory. The controller is characterized in that it is a controller for writing the data stored in the memory to the second memory.

According to a second aspect of the present invention for solving the problems of the conventional example, in the data transfer method of the inter-memory data transfer device according to the first aspect, the memory access controller sets the data read address to the first data read address. The data output to the memory and read from the first memory is FI.
Store in the FO memory, repeat the output of the data read address and the data storage in the FIFO memory, output the data write address to the second memory, and store in the FIFO memory in synchronization with the output of the data write address. The written data is written to the data write address of the second memory, and the output of the data write address and the data write to the second memory are repeated to perform data transfer.

According to a third aspect of the present invention for solving the problems of the conventional example, an inter-memory data transfer device is provided.
A first memory that stores data to be transferred, a second memory to which the data is transferred, and a data read address are output to the first memory and a data write address is output to the second memory. A memory access controller; a first address bus for transmitting the data read address output from the memory access controller to the first memory; and a data write address output from the memory access controller for the second memory bus. Second address bus for transmitting to the memory, a data bus for transmitting data from the first memory to the second memory, and the first memory for reading data at the data read address location Output the data read operation instruction and write the data to the data write address. It is characterized by a control circuit which outputs a data write operation instruction to said second memory so that burn them.

According to a fourth aspect of the present invention for solving the above-mentioned problems of the conventional example, in the data transfer method of the inter-memory data transfer device according to the third aspect, the memory access controller stores the first data in the first memory. Of the data read address via the address bus of the second memory and the data write address of the second memory via the second address bus, and the control circuit outputs the data read operation instruction to the first memory. The first memory reads the data at the data read address location according to the data read operation instruction and outputs it to the data bus, and the control circuit outputs a data write operation instruction to the second memory,
The second memory writes the data output to the data bus to the data write address location in accordance with the data write operation instruction and transfers the data.

According to a fifth aspect of the present invention for solving the problems of the conventional example, a plurality of memories, a memory access controller for outputting a single access address to all the plurality of memories, and the memory access controller. In a memory-to-memory data transfer device having a system bus connecting the memory and each of the memories, an address conversion for converting the access address between the system bus and each of the memories into an address corresponding to each of the memories And a control circuit for outputting a data read operation instruction and a data write operation instruction to the plurality of memories.

According to a sixth aspect of the present invention for solving the problems of the conventional example, in the data transfer method of the inter-memory data transfer device according to the fifth aspect, the memory access controller uses a single access address as a system. Data output to the bus, the access address converted into an address for each memory by each address converter and output to each memory, and the memory to which the data read operation instruction is given from the control circuit is the data at the converted address location. Read out and output to the system bus, and the memory to which the data write operation instruction is given from the control circuit writes the data output to the data bus to the converted address location to transfer the data. It has a feature.

[0025]

According to the first and second aspects of the present invention, the FIF for storing a fixed amount of data in the memory access controller.
An O memory is provided, a data read address is output to the first memory, the data read operation is repeated from the first memory, a fixed amount of data is stored in the FIFO memory, and then data is written to the second memory. The inter-memory data transfer device and the data transfer method for performing the data transfer by repeatedly performing the write operation to the second memory for the data stored in the FIFO memory in synchronization with the timing of outputting the address. D-RA
When M is used, high-speed page mode access can be utilized and data transfer between memories can be speeded up.

According to the third and fourth aspects of the present invention, the data read address to the first memory and the data write address to the second memory are set to the first address bus and the second address bus. To the data bus from the data read address portion of the first memory according to the data read operation instruction output from the control circuit and output to the data bus. Since the inter-memory data transfer device and the data transfer method for writing the data output to the data bus to the data write address portion of the memory and the data transfer method are used, it is possible to save the trouble of temporarily storing the transfer data in the memory access controller. Omit, and when using D-RAM as memory, utilize high-speed page mode access. It can be a data transfer between the memory at high speed.

According to the fifth and sixth aspects of the present invention, a single access address is output from the memory access controller, converted into an address for each memory by each address converter, and output to each memory. The memory that receives the data read operation instruction reads the data at the converted address location and outputs it to the system bus, and the memory that receives the data write operation instruction from the control circuit outputs the converted address location to the system bus. Since an inter-memory data transfer device and a data transfer method for writing the written data to transfer the data are used, it is possible to save the trouble of temporarily storing the transfer data in the memory access controller, and to use the high-speed page when using the D-RAM as the memory. Mode access can be used to speed up data transfer between multiple memories.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram of an inter-memory data transfer device according to an embodiment of the present invention. It should be noted that portions having the same configuration as in FIG.

The memory-to-memory data transfer apparatus of this embodiment is similar to the conventional memory-to-memory data transfer apparatus in that it has two memories 1 and 2 and a DMAC (Direct Memory Access Controller) for controlling access to the memories.
10 ', a system bus 20 for connecting the DMAC 10' and the memories 1 and 2, and the DMAC1
Inside 0, an address counter (Memory Address Counter, hereinafter referred to as MAC) 11 for reading data and an address counter (Destination Address Counter, hereinafter referred to as DAC) 12 for writing data are provided. Further, as a characteristic part of the present embodiment, a FIFO (First In First Out) memory 30 capable of storing a fixed amount of data inside the DMAC 10, a transfer counter for reading (hereinafter referred to as TC (1)) 17, Transfer counter for writing (TC
18 and a control unit 19 'for controlling various counters and the FIFO memory 30.

Next, the function of each part will be specifically described. The memory 1 is a memory for reading data in the memory-to-memory data transfer, and the memory 2 is a memory for writing data in the same manner as the conventional one.
0 connects the memories 1 and 2 with the controller DMAC 10 'to transfer addresses and data.

The DMAC 10 'is also a controller for controlling access to the memories 1 and 2 through the system bus 20 as in the conventional case, and the internal MAC 11 is a counter for setting the read address of the memory 1.
The DAC 12 is a counter that sets the write address of the memory 2.

The DMA, which is a characteristic part of this embodiment,
The FIFO memory 30 in the C10 'stores the data read from the memory 1 continuously, and when a certain amount is reached, the data stored earlier can be successively and sequentially output from the first memory. It is a memory.

Transfer counter for reading (TC (1)) 1
Reference numeral 7 is a counter for counting the number of transfer data read from the memory 1 and stored in the FIFO memory 30, and write transfer counter (TC (2)) 18 is for the FIFO.
It is a counter that counts the number of transfer data output from the memory 30 and written in the memory 2.

The control unit 19 'is a control unit for controlling various counters and the FIFO memory 30, and specifically, causes the TC (1) 17 to count the number of data read from the memory 1, The address of the memory 1 corresponding to the value of TC (1) 17 is set in the MAC 11 and supplied to the memory 1, the data read from the memory 1 is fetched from the system bus 20 and stored in the FIFO memory 30, and , TC (2) 18 counts the number of data to be written in the memory 2, sets the address of the memory 2 according to the value of TC (2) 18 in the DAC 12 and supplies it to the memory 2, and synchronizes with this. By outputting the data from the FIFO memory 30 to the system bus 20, the data transfer from the memory 1 to the memory 2 is controlled. Incidentally, T
Depending on the values of C (1) 17 and TC (2) 18, MAC 11, D
The address set in the AC 12 is managed in advance in a table format by the control unit 19 ′.

Next, a data transfer method in the inter-memory data transfer device of this embodiment will be described with reference to FIG. FIG. 2 is a schematic explanatory diagram showing a data transfer method between D-RAMs in the inter-memory data transfer device of this embodiment. Note that FIG. 2 shows an example of data transfer in a portion in which the row address of the D-RAM is constant and the column address continuously changes.

In the data transfer method of the memory-to-memory data transfer apparatus of this embodiment, when transferring data from the memory 1 to the memory 2, the control unit 19 'of the DMAC 10' controls the TC (1) 1
7 is counted up, the address of the memory 1 corresponding to the value of TC (1) 17 is set in the MAC 11, and it is supplied to the memory 1 via the system bus 20, and the data is supplied from the address to which the memory 1 is supplied. When the storage amount of the FIFO memory 30 reaches a certain amount by repeating the data read operation of reading out and outputting to the system bus 20 and storing the data in the FIFO memory 30 by the control unit 19 ′. Then, the control unit 19 'sets TC (2) 1
8 is counted up, the address of the memory 2 corresponding to the value of TC (2) 18 is set in the DAC 12, and it is supplied to the memory 2 via the system bus 20.
The data stored first in the FO memory 30 is sequentially output to the system bus 20, and the memory 2 outputs the data to the system bus 2.
The FIFO memory 30 performs a data write operation that takes in data from 0 and writes the data to the supplied address.
It is arranged to repeat the same amount of storage capacity as in the above, and to similarly repeat a series of read and write operations.

Here, the memories 1 and 2 are a D-RAM (Dynamic-RA) used exclusively for a large-capacity memory device.
In the case of M), if the high speed page mode access of the D-RAM is used, when the data in the same row is continuously accessed, only the column address is sequentially counted up after the row address is set and the column address is continuously incremented. It is possible to perform various reading and writing at high speed.

The data transfer flow between the D-RAMs which can operate in the high speed page mode using the data transfer method of this embodiment will now be described. As shown in FIG.
The control unit 19 'of the MAC 10' first sets the row address of the data read destination of the memory 1 in the MAC 11 and sends it via the system bus 20, and then sets and sends the column address, and the memory 1 reads the row address. The data is read from the address designated by the column address and is output to the system bus 20, and the control unit 19 ′ fetches this data and stores it in the FIFO memory 30.

Next, the control unit 19 'sets the next column address of the memory 1 in the MAC 11 and sends it via the system bus 20, and the memory 1 sends the data from the column address sent without changing the ROM address. The data is read out and output to the system bus 20.
The FIFO memory 3 receives this data from the bus 20.
The data is stored in 0 and a series of read operation is repeated in the same manner.

Then, when a certain amount of data is stored in the FIFO memory 30, the control unit 19 'determines that the DAC 12
The row address of the data write destination of the memory 2 is set to and is sent to the memory 2 via the system bus 20, then the column address is set and sent, and the FI is synchronized with it.
The data stored in the FO memory 30 is output to the system bus 20 from the previously stored data, and the memory 2 outputs the data to the system bus.
Data is fetched from the bus 20 and written to the address designated by the supplied row address and column address.

Next, the control unit 19 'sets the next column address of the memory 2 in the DAC 12 and sends it via the system bus 20, and in synchronization with it, the FIFO memory 30.
When the next data is output to the system bus 20 from the memory 2, the memory 2 fetches the data from the system bus 20,
The row address is written as it is, the data is written to the address specified by the column address, and a series of write operations is similarly repeated to write all the data stored in the FIFO memory 30 to the memory 2. The read operation and the write operation are repeated.

Next, the operation of the control section 19 'in the DMAC 10' of the memory-to-memory data transfer apparatus of this embodiment will be described with reference to FIGS. FIG. 3 is a flowchart showing the flow of the operation of the control unit 19 'of this embodiment. As shown in FIG. 3, the control unit 19 'of this embodiment first sets T
Clear C (1) 17 and TC (2) 18 (200), then add 1 to TC (1) 17 (210), set the address of read-only memory 1 in MAC 11 (212), and set M
The value of AC11 is output to the system bus 20 (21
4) Input data from the system bus 20 (21
6), store the data in the FIFO memory 30 (21
8). Then, it is judged whether the specified amount to be stored in the FIFO memory 30 has been reached (220), and if not reached, the process returns to the process 210.

When the specified amount to be stored in the FIFO memory 30 is reached, 1 is added to TC (2) 18 (230), the address of the memory 2 is set in the DAC 12 (232), and DA is set.
The value of C12 is output to the system bus 20 (234),
The data is output from the FIFO memory 30 to the system bus 20 (236), and it is judged whether the transfer of the data stored in the FIFO memory 30 is completed (240). If not completed, the process returns to the process 230.

When the transfer of the data stored in the FIFO memory 30 is completed, it is judged whether or not the transfer of all the data is completed (250). If the transfer has been completed, the process ends.

According to the inter-memory data transfer apparatus and the data transfer method thereof of this embodiment, the DMAC 10 'is provided with the FIFO memory 30 capable of storing a certain amount of data, and the read operation from the memory 1 is performed by the capacity of the FIFO memory 30. Since a fixed amount is continuously performed within the range of, and then the write operation to the memory 2 is continuously performed for the data stored in the FIFO memory 30, the high-speed page mode access of the D-RAM is performed. The address setting for each memory access can be reduced to about 1/2 in each process of data read and data write, and high-speed page mode access can realize high-speed data transfer between D-RAM memories. effective.

Next, another embodiment (second embodiment) of the present invention will be described with reference to the drawings. FIG. 4 is a configuration block diagram of an inter-memory data transfer device according to the second embodiment. It should be noted that portions having the same configuration as in FIG.

As shown in FIG. 4, the memory-to-memory data transfer device of the second embodiment controls access to the two memories 1 and 2 as a part similar to the conventional memory-to-memory data transfer device. There is a DMAC 40. Further, as a characteristic part of the present embodiment, two address buses 21 and 22 connecting the DMAC 40 and the memories 1 and 2, a data bus 25 connecting the memories, and the memories 1 and 2. And a control circuit 50 for controlling the DMAC 40.
In the inside of the, the data read destination address counter (MAC) 11, the data write destination address counter (DAC) 12, and the transfer counter (T
C) 16 and a control unit 49 for controlling each memory access address by operating each counter.

Next, the function of each part will be specifically described. The memory 1 is a memory for reading data in memory-to-memory data transfer, and the memory 2 is a memory for writing data, as in the conventional case.

And, which is a characteristic part of the second embodiment,
Address bus (1) 21 is from DMAC 40 to memory 1
Address bus (2)
22 is a bus for transferring addresses from the DMAC 40 to the memory 2, and the data bus 25 is a bus for transferring data between the memories 1, 2 and 2.

The DMAC 40 of the second embodiment is
It is a memory controller that can output multiple access addresses at the same time. It sends the access address from the MAC 11 to the memory 1 via the address bus (1) 21.
At the same time, the access address is sent from the DAC 12 to the memory 2 via the address bus (2) 22.

The counter inside the DMAC 40 is the same as the conventional one, the MAC 11 is a counter for setting the read address of the memory 1, the DAC 12 is a counter for setting the write address of the memory 2, and the TC 16 is for counting the number of transfer data. It is a counter that does.

Then, the control section 49 counts the number of transfer data in TC16, sets the address of memory 1 in MAC11 according to the value of TC16, sets the address of memory 2 in DAC12, and sets these two access addresses. Are simultaneously output to the respective address buses 21 and 22.

The control circuit 50 is a circuit for controlling the memory 1 and the memory 2. When each memory receives an access address, it supplies a data read operation signal to the memory 1 and a data write operation signal to the memory 2. It has become. Specifically, when the data read operation signal is output to the memory 1, the data of the data read destination address (access address) given to the memory 1 is transferred to the data.
When data is output (read) to the bus 25 and a data write operation signal is output to the memory 2, the data existing in the data bus 25 is written to the data write destination address (access address) given to the memory 2. .

Next, a data transfer method in the inter-memory data transfer device of the second embodiment will be described with reference to FIG. FIG. 5 is a schematic explanatory view showing a data transfer method in the inter-memory data transfer device of the second embodiment.

In the data transfer method of the inter-memory data transfer device of the second embodiment, as shown in FIG. 5, when transferring data from the memory 1 to the memory 2, the controller 49 of the DMAC 40 counts TC16. Up and MAC the read address (N) of the memory 1 according to the value of TC16
11, the write address (M) of the memory 2 is set in the DAC 12, and at the same time, each access address is output from the MAC 11 to the address bus (1) 21 and from the DAC 12 to the address bus (2) 22.

When the memory 1 receives the access address (N), a data read operation signal is given to the memory 1 from the control circuit 50, and the memory 1 reads the data from the supplied address (N) and the data bus. Two
Output to 5. On the other hand, when the memory 2 receives the access address (M), a data write operation signal is given to the memory 2 from the control circuit 50, the memory 2 takes in the data from the data bus 25, and the data is supplied to the supplied address (M). Write.

Next, TC16 is counted up, and TC
The read address of the memory 1 corresponding to the value of 16 is (N +
1), and the write address of the memory 2 is (M
+1), data transfer is performed by the same operation, and thereafter, a series of operations are similarly repeated.

Here, a case where the data transfer method of the second embodiment is used to transfer data between the D-RAMs which can operate in the high speed page mode will be described with reference to FIG. FIG. 6 shows the D using the data transfer method of the second embodiment.
FIG. 9 is a schematic explanatory diagram illustrating a method of transferring data between RAMs.
Incidentally, FIG. 6 shows an example of data transfer of a data portion in which the row address of the D-RAM is constant and the column address is changing.

When data transfer between D-RAMs capable of operating in the high speed page mode is performed by using the data transfer apparatus and the data transfer method thereof according to the second embodiment, first, a row which is a read address of the memory 1 is read. The address 1 and the row address 1'which is the write address of the memory 2 are simultaneously sent to the memories 1 and 2 via the address buses 21 and 22, and then the column address 1 which is the read address of the memory 1 and the memory 2 are read. When the column address 1'which is a write address is sent to the memories 1 and 2 at the same time, the control circuit 5
0 to the memories 1 and 2 by the data read operation signal and the data write operation signal.
Data transfer is performed directly to.

When the column address 2 which is the read address of the memory 1 and the column address 2 ′ which is the write address of the memory 2 are sent to the memories 1 and 2 at the same time, the memory 1 receives the data read operation signal and the data write operation signal. Then, the next data is transferred to the memory 2, and the same operation is repeated thereafter.

According to the inter-memory data transfer apparatus and the data transfer method thereof of the second embodiment, the read address of the memory 1 and the write address of the memory 2 are simultaneously supplied from the DMAC 40 via the address buses 21 and 22. However, under the control of the control circuit 50, the data is directly transferred from the memory 1 to the memory 2 via the data bus 25, so that the labor of temporarily storing the transfer data in the DMAC 40 is saved, and Since high-speed page mode access of the D-RAM can also be utilized, there is an effect that high-speed data transfer between memories can be realized.

A case of performing data transfer between three memories in another embodiment (third embodiment) will be described with reference to the drawings. FIG. 7 is a configuration block diagram of an inter-memory data transfer device according to the third embodiment. It should be noted that portions having the same configuration as in FIG.

As shown in FIG. 7, the inter-memory data transfer device of the third embodiment has a plurality of memories 1, 2 and 3 as a conventional part, a DMAC 60 for controlling access to the memories, and a DMAC 60. Each memory 1, 2,
3 and a system bus 20 for connecting them, and as a characteristic part of the third embodiment, an address converter (Memory Management Unit, hereinafter referred to as MM) provided for each memory.
71, 72, 73 and memories 1, 2, 3
In the DMAC 60, a control circuit 80 for controlling the supply address counter, an address counter (hereinafter referred to as AC) 61, a transfer counter (TC) 16 similar to the conventional one, and an access address by operating the counter. And a control unit 69 for controlling the above.

Next, the function of each part will be specifically described. In the third embodiment, the data transfer from the memory 1 to the memory 2 and the data transfer from the memory 2 to the memory 3 are simultaneously performed, and the system bus 20 is D
It is a bus that connects the MAC 60 and each memory and transfers addresses and data.

The DMAC 60 outputs a single access address to control access to the memories 1, 2 and 3. The internal TC 16 is a counter for counting the number of transfer data as in the conventional case. Yes,
AC 61 is a counter that sets an access address from the value of TC 16.

Then, the control unit 69 counts the TC 16 by the number of transfer data, sets the access address according to the value of the TC 16 in the AC 61, and outputs it to the system bus 20.

The MMUs 71, 72, 73 are the DMAC 60.
The single access address supplied from the above is converted by a preset conversion method and supplied to the memories 1, 2 and 3 so as to correspond to each memory.

The control circuit 80 is a circuit for controlling the memory 1, the memory 2 and the memory 3. When each memory receives the respective access addresses, it gives a data read operation signal to the memory 1 and a data read to the memory 2. An operation signal and a data write operation signal are given, and a data write operation signal is given to the memory 3.

Next, a data transfer method in the inter-memory data transfer device of the third embodiment will be described with reference to FIG. FIG. 8 is a schematic explanatory view showing a data transfer method in the inter-memory data transfer device of the third embodiment.

In the data transfer method of the inter-memory data transfer device of the third embodiment, as shown in FIG. 8, data is transferred from the memory 2 to the memory 3, and further the memory 1 to the memory 2 are transferred.
Control unit 69 of the DMAC 60 when transferring data to the
Counts up TC16, sets the access address (L) corresponding to the value of TC16 in AC61, and outputs it to the system bus 20.

Then, each MMU 71, 72, 73 fetches an access address from the system bus 20, converts the address by a predetermined conversion method, and
An address (M) is supplied from U71 to the memory 1 and M
The address (N) is supplied from the MU 72 to the memory 2,
An address (O) is supplied from the MMU 73 to the memory 3.

When the memory 2 receives the access address (N), the control circuit 80 gives a data read operation signal to the memory 2, and the memory 2 reads the data from the supplied address (N) and the system bus. 20 while the memory 3 accesses the access address (O).
When the control circuit 80 receives a data write operation signal from the control circuit 80, the memory 3 sends the data write operation signal to the system bus 2
The data is taken in from 0, and the data is written in the supplied address (O).

Next, the memory 1 accesses the access address (M).
When the control circuit 80 receives a data read operation signal from the control circuit 80, the memory 1 reads the data from the supplied address (M) and outputs the data to the system bus 20, while the control circuit 80 outputs the data to the memory 2. When the data write operation signal is given, the memory 2 is transferred to the system bus 20.
The data is taken in from and the data is written to the address (N) supplied to the memory 2.

Next, the address set in AC61 is 1
The number increases to (L + 1), and accordingly, each MMU 71,
The addresses converted by 72 and 73 are (M +
1), (N + 1), (O + 1), data transfer is performed by the same operation, and a series of operations is repeated.

Here, a case of performing data transfer between D-RAMs capable of operating in the high speed page mode by using the data transfer method of the third embodiment will be described with reference to FIG. FIG. 9 shows the D using the data transfer method of the third embodiment.
FIG. 9 is a schematic explanatory diagram illustrating a method of transferring data between RAMs.
Note that FIG. 9 shows an example of data transfer of a data portion in which the row address of the D-RAM is constant and the column address is changing.

When performing data transfer between D-RAMs capable of operating in the high speed page mode using the data transfer apparatus and the data transfer method thereof according to the third embodiment, first, the row address (a ' 1) is set to AC61 and output to the system bus 20, each MMU7
1, 72, 73, and the row address (b'1) and the row address (c 'are stored in the memories 1, 2 and 3, respectively.
1) and row address (d'1) are supplied. Next, when the column address (a1) of the access address is set in AC61 and output to the system bus 20, each MMU7
1, 72, 73, and the memory addresses 1, 2 and 3 are respectively converted into a column address (b1) and a column address (c
1) and column address (d1) are supplied.

As a result, first, data is read from the row address (c'1) and column address (c1) of the memory 2, and the data is read from the row address (d'1) of the memory 3.
), The column address (d1), and then the row address (b'1) and column address (b) of the memory 1
Data is read from 1) and the data is written to the row address (c'1) and column address (c1) of the memory 2.

Next, in the same manner, the column address (a2) of the access address is set in the AC 61 and output to the system bus 20, converted by the MMUs 71, 72, 73 and stored in the memories 1, 2, 3. Are respectively supplied with a column address (b2), a column address (c2), and a column address (d2). As a result, the row address of each memory remains unchanged, and the row address (c'1) and the column address of the memory 2 are first stored. Data is read from (c2) and written to the row address (d'1) and column address (d2) of the memory 3, and then from the row address (b'1) and column address (b2) of the memory 1. The data is read and written to the row address (c'1) and the column address (c2) of the memory 2, and a series of operations are similarly repeated.

According to the inter-memory data transfer device and the data transfer method thereof of the third embodiment, a single access address is supplied from the DMAC 60 and the address conversion is performed by the MMUs 71, 72, 73 provided for each memory. Access addresses are supplied to the memories 1, 2, 3 and each memory is read or written under the control of the control circuit 80 to directly transfer data between the memories. Saves you the trouble of temporarily storing
Since high-speed page mode access of RAM can also be utilized, there is an effect that high-speed data transfer between memories can be realized.

Further, according to the inter-memory data transfer device and the data transfer method thereof of the third embodiment, particularly high-speed data transfer between a plurality of memories can be realized. Therefore, background data saving in screen memory data control, There is an effect that can be effectively applied to the overdrawing of cursor figures.

In the inter-memory data transfer device of the third embodiment, the memory 3 and the MMU 73 are removed and the present invention can be applied to data transfer between two memories. In this case, the second
It is not necessary to provide an address bus for each memory as compared with the inter-memory data transfer device of the embodiment of
Since it is not necessary to provide the bus and data bus separately,
The counter and the bus part can be simplified.

[0082]

According to the first and second aspects of the present invention, a FIFO memory for storing a fixed amount of data is provided in the memory access controller, and a data read address is output to the first memory to output the first memory. The data read operation is repeatedly performed from the memory to store a certain amount of data in the FIFO memory, and then the write operation to the second memory is performed to the FIFO memory in synchronization with the timing of outputting the data write address to the second memory. Since the inter-memory data transfer device and the data transfer method for repeatedly performing the data transfer for the stored data are used, the
When RAM is used, high-speed page mode access can be utilized and data transfer between memories can be speeded up.

According to the third and fourth aspects of the present invention, the data read address to the first memory and the data write address to the second memory are set to the first address bus and the second address bus. To the data bus from the data read address portion of the first memory according to the data read operation instruction output from the control circuit and output to the data bus. Since the inter-memory data transfer device and the data transfer method for writing the data output to the data bus to the data write address portion of the memory and the data transfer method are used, it is possible to save the trouble of temporarily storing the transfer data in the memory access controller. Omit, and when using D-RAM as memory, utilize high-speed page mode access. It can be an effect that can transfer data between the memory at high speed.

According to the fifth and sixth aspects of the present invention, a single access address is output from the memory access controller, converted into an address for each memory by each address converter and output to each memory. The memory that receives the data read operation instruction reads the data at the converted address location and outputs it to the system bus, and the memory that receives the data write operation instruction from the control circuit outputs the converted address location to the system bus. Since an inter-memory data transfer device and a data transfer method for writing the written data to transfer the data are used, it is possible to save the trouble of temporarily storing the transfer data in the memory access controller, and to use the high-speed page when using the D-RAM as the memory. Mode access can be used to speed up data transfer between multiple memories. There is a result.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an inter-memory data transfer device according to an embodiment of the present invention.

FIG. 2 is a block diagram of D in the memory-to-memory data transfer device of this embodiment
FIG. 9 is a schematic explanatory diagram illustrating a method of transferring data between RAMs.

FIG. 3 is a flowchart showing a flow of operation of a control unit 19 ′ of this embodiment.

FIG. 4 is a configuration block diagram of an inter-memory data transfer device according to a second embodiment.

FIG. 5 is a schematic explanatory diagram showing a data transfer method in the inter-memory data transfer device of the second embodiment.

FIG. 6 is a DR using the data transfer method of the second embodiment.
It is a schematic explanatory drawing which shows the data transfer method between AMs.

FIG. 7 is a configuration block diagram of an inter-memory data transfer device according to a third embodiment.

FIG. 8 is a schematic explanatory view showing a data transfer method in the inter-memory data transfer device of the third embodiment.

FIG. 9 is a DR using the data transfer method of the third embodiment.
It is a schematic explanatory drawing which shows the data transfer method between AM.

FIG. 10 is a configuration block diagram of a conventional inter-memory data transfer device.

FIG. 11 shows a D- in a conventional memory-to-memory data transfer device.
It is a schematic explanatory drawing which shows the data transfer method between RAMs.

FIG. 12 is a flowchart showing a flow of operations of a conventional control section 19.

[Explanation of symbols]

1, 2, 3 ... Memory, 10, 10 ', 40, 60 ... D
MAC, 11 ... MAC, 12 ... DAC, 15 ... Data buffer, 16, 17, 18 ... TC, 19, 1
9 ', 49, 69 ... Control unit, 20 ... System bus,
21, 22 ... Address bus, 25 ... Data bus, 30 ... FIFO memory, 50, 80 ... Control circuit, 61 ... AC, 71, 72, 73 ... MMU

Claims (6)

[Claims] 1. A first memory storing data to be transferred, a second memory to which the data is transferred, and a data read address are output to the first memory, and the first memory outputs the data read address. A memory access controller for reading data in a data read address portion, outputting a data write address to the second memory, and writing the read data in the data write address portion of the second memory; System for connecting to the first and second memories
In a memory-to-memory data transfer device having a bus, a FIFO memory for storing a fixed amount of data is provided in the memory access controller, and the memory access controller outputs a data read address and reads data from the first memory. Repeat the above and the FIF
A memory, which is a controller for storing data in the O memory and writing the data stored in the FIFO memory in the second memory in synchronization with the timing of outputting the data write address to the second memory. Data transfer device. 2. A memory access controller outputs a data read address to a first memory, stores data read from the first memory in a FIFO memory, and outputs the data read address and the FIFO.
The data storage in the memory is repeated, the data write address is output to the second memory, and the data stored in the FIFO memory is synchronized with the output of the data write address to the data write address of the second memory. 2. The data transfer method for a memory-to-memory data transfer device according to claim 1, wherein data transfer is performed by repeating writing, outputting the data write address, and writing data to the second memory. 3. A first memory for storing data to be transferred, a second memory to which the data is transferred, a data read address is output to the first memory, and data is transferred to the second memory. A memory access controller for outputting a write address; a first address bus for transmitting the data read address output from the memory access controller to the first memory; and a data write output for the memory access controller A second address bus for transmitting an address to the second memory; a data bus for transmitting data from the first memory to the second memory; and for reading data at the data read address location. The data read operation instruction is output to the first memory, and the data write address To write data to the second
And a control circuit that outputs a data write operation instruction to the memory of FIG. 4. The memory access controller outputs a data read address to the first memory via the first address bus and a data write address to the second memory via the second address bus, The control circuit outputs a data read operation instruction to the first memory, the first memory reads the data at the data read address location according to the data read operation instruction, and outputs the data to the data bus, and the control circuit Outputting a data write operation instruction to the second memory, and causing the second memory to write the data output to the data bus to the data write address location according to the data write operation instruction to perform data transfer. Claim 3 characterized by
A data transfer method of a data transfer device between memories described. 5. Inter-memory data having a plurality of memories, a memory access controller for outputting a single access address to all of the plurality of memories, and a system bus connecting the memory access controller and each of the memories In the transfer device, an address converter that converts the access address into an address corresponding to each memory is provided between the system bus and each memory, and a data read operation instruction and a data write operation are performed in the plurality of memories. An inter-memory data transfer device comprising a control circuit for outputting an instruction. 6. A memory access controller outputs a single access address to a system bus, each address converter converts the access address into an address for each memory, and outputs the address to each memory. The memory to which the read operation instruction is given reads the data at the converted address portion and outputs the data to the system bus, and the memory to which the data write operation instruction is given from the control circuit is provided to the converted address portion. 6. The data transfer method for a memory-to-memory data transfer device according to claim 5, wherein the data output to the data bus is written to transfer the data.