JPH07111975B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit including a transistor that can satisfy all of Icmax and withstand voltage h _FE .

(B) Conventional technology Since the basic technical idea is to use each diffusion region in common in a semiconductor integrated circuit to simplify the process, each circuit element is configured with a common diffusion region, and the same chip is used. All of the above elements (NPN transistors) had the same characteristics.

However, in consumer ICs, especially audio ICs, etc., power system transistors in the output stage are often incorporated at the same time as various signal processing circuits, and due to circuit requirements, small signal transistors for signal processing and output stage transistors are used. There is a demand for differentiating the current amplification factor h _FE of the large-signal transistors. In other words, when the 100 to 200 the h _FE of the small signal transistor,
The requirement is to reduce the h _{FE of} large signal transistors to around 50 to increase the maximum collector current Icmax.

As means for changing h _FE in this way, for example, Japanese Patent Laid-Open No.
As described in 0-70756, there is a means for separately forming the base region.

That is, as shown in FIG. 3, each island (3) obtained by separating the epitaxial layer (1) by the separation region (2) has a base region (5) for the small signal transistor ( 4 ) and a large signal transistor ( 6 ). And the base region (7) of the above are individually formed. At this time, two methods can be considered for the base region (7) of the large signal transistor ( 6 ).

One is a method to reduce the h _FE by setting the impurity concentration high (Fig. 4, Fig. 1), and the other is a method to deepen the diffusion depth (widen the base width) and reduce the h _FE (4th method). Fig. 2).

(C) Problems to be Solved by the Invention However, the above-mentioned method has a drawback in that it cannot be increased so much due to the saturation limit of boron with respect to silicon crystals, and thus there is a limit in reducing h _FE . . Moreover, since there is concern about the breakdown voltage deterioration due to Zener breakdown,
When the base region (7) is formed by ion implantation, the processing time becomes long due to the increase in dose amount, which complicates the process.
On the other hand, although the latter method meets the purpose of lowering h _FE , there is a close relationship between the impurity concentration and the diffusion depth, and the impurity concentration of the base deteriorates, causing conductivity modulation.
There was a drawback that max did not increase. From this, h
_{If the FE} is the same, the higher the concentration of the base, the larger the Icmax can be. Even if both the impurity concentration and the base width are controlled, it is still difficult to satisfy both h _FE and Icmax.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and has a lower impurity concentration than the base region (21) at the bottom of the base region (21) having a relatively high impurity concentration. By forming a low-concentration base region (23), it has an appropriate h _FE and Icm
Provided is a semiconductor integrated circuit including a power transistor having a large ax.

According to (e) the invention for work, since the base width of the large signal transistor by superimposed low concentration base region (23) (20) widens, from the h _FE h _FE of the small-signal transistor (16) It can be controlled to a small and appropriate value.
Since the base region (21) forming a part of the base has a relatively high impurity concentration, the maximum collector current Icmax can be increased.

(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor integrated circuit according to the present invention. In the figure, (11) is a P-type silicon single crystal substrate,
(12) is an N ⁻ type epitaxial layer formed by epitaxial growth on the surface of the substrate (11), (13) is an N ⁺ type buried layer, and (14) surrounds the buried layer (13) and penetrates the epitaxial layer (12). The P ⁺ -type isolation region (15) is an island individually isolated by the isolation region (14).

One of the islands (15) has a small signal transistor ( 16 )
To form the P type base region (17) and the N ⁺ type emitter region (18), the island (15) is used as a collector to form a vertical NPN transistor. (19) is an N ⁺ type collector contact region.

Large signal transistor ( 20 ) on the other island (15)
In order to form the P type base region (21) and the N ⁺ type emitter region (22), a P ⁻ type low concentration base region (23) is formed so as to overlap with the base region (21). (24) is N ⁺ type collector contact region, (25) is silicon oxide film, (26)
Is each electrode. Base region (21) and emitter region (2
2) was formed in the same process.

In the low-concentration base region (23), the base region (21) is formed with a surface concentration of 10 ¹⁸ atomscm ^-2 and a diffusion depth of 1.0 to 1.5 µ, whereas the surface concentration of 10 ¹⁶ to 10 ¹⁷ atomscm ^{-2 is} diffused. Depth 2.0 ~
3.0 μ, which is deeper with a lower impurity concentration than the base region (22). When the impurity concentration is lowered as described above, an increase in leak current due to surface depletion of impurities is feared, so the low-concentration base region (23) is formed so as not to protrude from the base region (21).

As a result of double formation of the base region (21) and the low-concentration base region (23) below the emitter region (22), the concentration profile has the distribution shown in FIG. That is, the relatively steep slope formed by the base region (21) having a relatively high impurity concentration and the low concentration base region (23) having a relatively low impurity concentration.
Has a two-step inclination, which is a gentle inclination formed by. Then, the base width W _B of the large signal transistor ( 20 ) is determined by the diffusion depth of the low concentration base region (23) as shown in the figure, so that the small signal transistor ( 16 ) of only the base region (17) is formed.
The base width can be increased, and the current amplification factor h _FE can be reduced. Since it is a low impurity concentration region, h _FE will not drop too much. At the same time, since the base of the large signal transistor ( 20 ) is overlaid with the base region (21) of relatively high impurity concentration due to the base diffusion, the influence of the conductivity modulation of the base is small, and therefore it can be obtained by lowering h _FE. It is possible to maximize the increase in Icmax that can be obtained.

2A to 2D show a method of manufacturing the integrated circuit of the present application.

First, as shown in FIG. 2A, an epitaxial layer (12) is formed on a substrate (11) on which a buried layer (13) and a lower isolation region (14) are formed to correspond to a low concentration base region (23). Poron (B) is selectively ion-implanted into a portion at a required dose, and heat treatment is applied to the entire substrate (11) as shown in FIG. 2B so that the surface of the epitaxial layer (12) is doped with boron (B). Is driven in to a desired depth to form an upper isolation region (14) as shown in FIG. 2C, and then boron (B) is selectively ion-implanted and driven in again to drive the small signal transistor ( By simultaneously forming the base region (17) of 16 ) and the base region (21) of the large signal transistor ( 20 ), and forming the emitter regions (18) and (22) by emitter diffusion as shown in FIG. 2D. small-signal transistor (16) Forming a large-signal transistor (20).

According to the configuration of the present application, the small signal transistor ( 16 ) and the large signal transistor ( 20 ) are formed by subjecting the diffused low-concentration base region (23) to the base diffusion in which the diffusion depth does not easily change even if some heat treatment is applied. Therefore, the base diffusion can be controlled and diffused for the small signal transistor ( 16 ). Therefore, it is very easy to control the characteristics of both the small signal transistor ( 16 ) and the large signal transistor ( 20 ).

(G) Effect of the Invention As described above, according to the present invention, by superimposing the low-concentration base region (23) on the large-signal transistor ( 20 ), the small-signal transistor ( 16 ) and _hFE having a high h _{FE can be obtained.} It has the advantage that it can easily coexist with a large signal transistor ( 20 ) having a small size. In addition, since the base of the large signal transistor ( 20 ) is overlapped with the base region (21) having a relatively high impurity concentration, the decrease in Icmax due to conductivity modulation is small, and therefore the advantage that Icmax can be maximized is obtained. Have.
Furthermore, there is an advantage that ASO can be increased by lowering the h _FE of the large signal transistor ( 20 ) and that the transistor can be manufactured to have appropriate characteristics as an output stage transistor. And further,
The use of the low-concentration base region (23) also has an advantage that characteristics of both large signals and small signals can be easily controlled.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining the present invention, and FIGS. 2A to 2D.
Is a cross-sectional view for explaining the manufacturing method thereof, FIG. 3 is a cross-sectional view for explaining a conventional example, FIG. 4 is a view showing a conventional impurity concentration distribution, and FIG. 5 is a impurity concentration distribution of the present application. It is a figure.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (7)

[Claims] 1. A semiconductor integrated circuit comprising a vertical transistor in which a base region and an emitter region are overlapped with each other on one surface of an electrically isolated island, wherein an impurity profile of a base region below the emitter region is: A semiconductor integrated device characterized by having a second-stage gradient of a first gradient having a steep gradient and a second gradient having a gentler gradient than the first gradient over the entire surface of the emitter region. circuit. 2. A semiconductor integrated circuit comprising a vertical transistor in which a base region and an emitter region are overlapped with each other on one surface of an electrically isolated island, wherein the entire surface of the emitter region is below the base region. A semiconductor integrated circuit having a low concentration base region having a lower impurity concentration than the base region in a corresponding portion. 3. A reverse conductivity type epitaxial layer formed on a semiconductor substrate of one conductivity type, a plurality of islands formed by separating the epitaxial layer, and a first transistor for forming the first transistor. A base region of one conductivity type formed on one surface of the island, and an emitter region of opposite conductivity type formed on the surface of the base region, and another surface of the island to form a second transistor. A base region of one conductivity type and an emitter region of opposite conductivity type; and a low-concentration base region deeper than the base region and lower in impurity concentration than the base region formed to overlap with the base region of the second transistor. A semiconductor integrated circuit comprising: 4. The semiconductor integrated circuit according to claim 3, wherein the base region of the first transistor and the base region of the second transistor are formed at the same time. 5. The semiconductor integrated circuit according to claim 3, wherein the second transistor is configured as an output transistor. 6. The semiconductor integrated circuit according to claim 1, wherein the base region of the second transistor is overlapped so as to completely cover the low concentration base region. 7. A process of forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type, wherein impurities of one conductivity type are ion-implanted into the surface of the epitaxial layer and diffused to a desired depth to form a large signal transistor. Forming a low-concentration base region for the semiconductor layer, selectively diffusing one conductivity type impurity in the surface of the epitaxial layer, and superimposing it on the base region for the small-signal transistor and the low-concentration base region for the large-signal transistor. Forming a base region having a higher impurity concentration than the low-concentration base region and shallower than the low-concentration base region; forming an emitter region of a reverse conductivity type on the surface of the base region of the small signal transistor. The desired h _FE is obtained, and the emitter region of the large signal transistor is also formed in the portion where the low concentration base region and the base region are overlapped with each other to form the small signal. A step of obtaining h _FE smaller than the h _{FE of the} transistor, and a method of manufacturing a semiconductor integrated circuit.