JPH07111836B2 - Semiconductor non-volatile memory device and operating method thereof - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a rewritable semiconductor nonvolatile memory device.

[Outline of Invention]

According to the present invention, a semiconductor non-volatile memory device is configured to have means for temporarily storing a memory cell for a certain period of time, means for non-volatile storage, and means for connecting the two means. By this, the temporary storage means is written in a short time, and then all bits are simultaneously stored in the non-volatile storage means from the temporary storage means through the connection means, so that the multi-bit non-volatile It was designed to allow sexual memory in a short time.

[Conventional technology]

Rewritable semiconductor non-volatile memory devices have the function of retaining their stored data even when the power supply is cut off. It has been known that rewritable EEPROM, NVRAM (NOVRAM), which corresponds to SRAM and EEPROM bit by bit. In addition,
FIG. 2 is a block diagram showing a memory cell of a conventional semiconductor nonvolatile memory device, wherein 1 is a memory cell and 4 is a nonvolatile memory means.

[Problems to be Solved by the Invention] In a system using a semiconductor nonvolatile memory device, there is often a demand to write a large amount of data in a nonvolatile manner in a short time. For such a request, for example, 64
Considering a k-bit EEPROM, assuming that the configuration is 8 bits × 8196 bytes, and if it takes 10 milliseconds to rewrite 1 byte, it will take 81.92 seconds or more to rewrite all the bits. Also, even if there is a page mode rewriting function that is installed in some recent models, it will take about 2.56 seconds or more if the 64k bit EEPROM has 256 pages. As described above, the conventional semiconductor nonvolatile memory device has a drawback that it takes a very long time to rewrite a large amount of data.

Moreover, in the case of the conventional NVRAM, one nonvolatile memory cell corresponds to one SRAM cell, and the rewriting time is short, but the cell area becomes very large. There were drawbacks that the system became large and the cost was disadvantageous. The present invention has been made in order to solve the above drawbacks of the related art, and an object thereof is to obtain a semiconductor nonvolatile memory device which has a short rewriting time for all bits and is advantageous in terms of cost. .

[Means for Solving the Problems]

In order to solve the above problems, the present invention provides a means for temporarily storing (holding) write data at least for a certain period of time so as to correspond to each cell that performs nonvolatile storage By connecting via the means, the nonvolatile memory can be stored in a short time while minimizing the increase in the area of the memory cell.

[Action]

When writing is performed in the memory cell configured as described above, the means for temporarily storing (holding) the write data is tens of thousands to 100,000 times as long as the nonvolatile storage is performed. Writing is performed in a fraction of the time (per 1 byte). After the temporary writing to all bits is completed, all bits are simultaneously stored in the nonvolatile storage from the temporary storage unit to the nonvolatile storage unit via the connection unit.

〔Example〕

FIG. 1 is a block diagram showing the principle of the present invention, in which 1 is a storage cell, 2 is a temporary storage means, 3 is a connection means (writing auxiliary means), and 4 is a non-volatile storage means.

FIG. 3 shows a first embodiment of the present invention, in which a capacitor 21 as a temporary storage means is a MIS transistor 31 which constitutes a connecting means.
Is connected to the gate. The control gate of the floating gate MIS transistor 41 as the non-volatile memory means is the MIS transistor 31 constituting the connecting means.
Connected to the drain of. The drain of the MIS transistor 31 is connected to the capacitor 32. First, the capacitor 21 is charged or discharged to cause temporary storage. Next, when a high voltage is applied to one end A of the capacitance 32 which is not connected to the drain of the MIS transistor 31, the connection point B between the drain of the MIS transistor 31 and the capacitance 32 is charged with the capacitance 21. When the capacitance 21 is discharged, the potential is close to the source of the MIS transistor 31, and when the capacitance 21 is discharged, the potential is close to the high voltage applied to the one end A of the capacitance 32. Connection point B
Is connected to the control gate of the floating gate MIS transistor 41, and the potential of the connection point B is transmitted to the control gate.

FIG. 4 is a timing chart of the first embodiment, which shows a curve a.
Indicates the electric potential of A, and the curve b indicates the electric potential of C. TI is A
This is the period when 21 of the electric potential of is high voltage, and T2 is A
A period in which both the potential of C and the potential of C are high voltage is shown. When a voltage is applied at the timing of FIG. 4 and the connection point B has the same potential as the source of the MIS transistor 31, the information X is written in the period of T2, and the connection point B has the capacitance. When the potential is almost the same as the one end A of 32,
Information opposite to the information X is written during the period T1.

When rewriting is performed by the above procedure, for example 64
Considering a semiconductor non-volatile memory device according to the present invention having a storage cell of k bits (8 bits × 8192 bytes), it takes 250 + 1 seconds per byte for temporary storage, but 250 + 1 for all bits. It takes seconds × 8192 = 2.05 milliseconds, and then all bits are simultaneously written from the temporary storage means to the non-volatile storage means.

Since this operation takes about 10 milliseconds, which is the same time as one non-volatile write, rewriting of all 64k bits is completed in about 12 milliseconds in total.

Further, FIG. 5 shows a second embodiment of the present invention, in which the write terminal of the floating gate MIS transistor 41 is connected to the connection point A in the first embodiment,
The control gate of the floating gate MIS transistor 41 is connected to the terminal D, and the same potential as that of the writing terminal C in the first embodiment is applied to the terminal D, whereby the same operation as in the first embodiment is performed. Is to do.

FIG. 6 shows a third embodiment of the present invention, which is the floating gate MIS transistor 41 of the first embodiment.
Of the floating gate MIS transistor 4 is connected to the drain of the capacitor 21 via the MIS transistor 51.
The function for returning the information stored in 1 to the capacity 21 is added.

〔The invention's effect〕

As described above, the present invention has the effect that all bits can be rewritten in a short time without requiring a large memory cell area even in a large capacity semiconductor nonvolatile memory device. The effect is that the floating gate type MI is added to the nonvolatile memory means as described in this embodiment.
The same effect can be obtained not only by using the S-transistor but also by using other principles in the nonvolatile storage method, and also in the connection means, the one-way from the temporary storage means to the nonvolatile storage means. It goes without saying that the same effect can be obtained by using a bidirectional connection means that can connect not only the non-volatile storage means but also the temporary storage means. (See Figure 5)

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor nonvolatile memory device according to the present invention, FIG. 2 is a block diagram of a conventional semiconductor nonvolatile memory device, and FIG. 3 is a circuit diagram showing a first embodiment according to the present invention. FIG. 4 is a voltage timing chart of the first embodiment according to the invention, FIG. 5 is a circuit diagram showing a second embodiment of the invention, and FIG. 6 is a third embodiment of the invention. It is a circuit diagram showing. 1 ... Storage cell 2 ... Temporary storage means 3 ... Connection means 4 ... Non-volatile storage means 21 ... Capacitance 31 ... MIS transistor 32 ... Capacitance 41 ... Floating gate MIS transistor

Claims (3)

[Claims] 1. Storage comprising temporary storage means for temporarily storing data for a certain period of time, write assisting means connected to the temporary storage means, and non-volatile storage means connected to the write assisting means. In a semiconductor nonvolatile memory device having a plurality of cells, the write assisting means has a capacitor and an MIS transistor, a gate electrode of the MIS transistor is electrically connected to the temporary memory means, and one terminal of the capacitor has a predetermined value. A semiconductor nonvolatile memory device, characterized in that a voltage is input and the other terminal is electrically connected to the drain electrode of the MIS transistor and the nonvolatile memory means. 2. The semiconductor nonvolatile memory device according to claim 1, wherein said nonvolatile memory means is an electrically rewritable nonvolatile memory cell. 3. Storage comprising temporary storage means for temporarily storing data for a certain period of time, write assisting means connected to the temporary storage means, and non-volatile storage means connected to the write assisting means. In a method of operating a semiconductor non-volatile memory device having a plurality of cells, wherein the write assisting means is configured to directly connect a capacitor and a MIS transistor, a temporary write is performed to the temporary storing means of each memory cell. A semiconductor comprising: a temporary write step; and a step of simultaneously performing non-volatile storage in the non-volatile storage means of each memory cell via the write assisting means of each memory cell after the end of the temporary write step. Non-volatile memory device operating method.