JPH0256758B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to electrically erasable and rewritable read-only memories (E ² PROMs), and more particularly to page mode programming systems.

[Technical background of the invention]

In recent years, with the increase in the capacity of E ² PROM,
As a way to solve the problem of the long data writing time of E ² PROM, page mode programming has been proposed to rewrite data in a short time. The specifications of this page mode programming are as shown in Figure 2. In the byte load cycle in page programming mode, all n bytes of write data (for one page) are captured and latched internally, and then rewritten in the next erase cycle. All data stored in the target memory cell is erased, and the latched data is programmed (written) in the next program cycle to return to the normal read mode. In this case, the erase/program time is constant regardless of the number of bytes of written data (e.g.
5ms), so the larger the number of bytes in a page, the shorter the program time equivalently becomes.

Although the specific circuit format for realizing the above page mode programming specifications has not yet been determined, a simple configuration is a method that rewrites all n bytes of page data, no matter how many bytes there are to be rewritten. is possible. That is,
As shown in FIG. 3, the moment the page mode program operation starts, all the byte data belonging to the selected column of the main body memory 1 is transferred to the data latch unit 3.
Transfer to. Then, in the byte load cycle, only the data latch section 3 is accessed and changed to write data. All the data in the selected column 2 of the main body memory 1 is erased in the next erase cycle, and all the data in the data latch section 3 is transferred to the selected column 2 in the main body memory 1 in the next program cycle.

According to such a method, the system is simple, a selector for byte data for each column of the main body memory 1 is not required, and the degree of memory integration can be increased.

[Problems with background technology] By the way, E ² PROM is different from normal RAM.
Unless written data and read data are compared by a mechanism such as a flag, an erase/program cycle must be performed even if the stored data and written data are the same. However, this erase/program cycle requires the application of a high voltage, and there is a high probability that memory cell failure will occur when a high voltage is applied. Therefore,
In order to suppress the occurrence of such cell defects,
When the stored data and written data are the same as described above, it is desirable to avoid rewriting the same data.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
Electrically erasable/rewritable read-only memory that enables page mode programming that avoids rewriting the same byte data and rewrites only the byte data that requires rewriting, and reduces the probability of memory cell failure. It provides:

[Summary of the invention]

That is, the present invention provides, in an E ² PROM that satisfies page mode programming specifications, a byte data buffer that temporarily stores byte data that requires data rewriting among page data to be written in a byte load cycle; Similarly, in a byte load cycle, a flag means outputs a rewrite flag corresponding to the byte data that requires data rewriting, and in an erase cycle, a group of memory cells that require data rewriting is selected by referring to the flag output of the flag means. An erasing means selects and erases the stored data, and selects a memory cell group whose data needs to be rewritten from among the memory cells page-selected in the program cycle by referring to the flag output of the flag means, and erases the memory data. The present invention is characterized by comprising a write means for writing data corresponding to the data stored in the byte data buffer into the cell group.

Therefore, it is possible to perform page mode programming in which only byte data that requires rewriting is rewritten while avoiding rewriting the same byte data, thereby making it possible to suppress the probability of memory cell failure.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 shows a part of the E ² PROM, and to simplify the explanation, the cell data readout system is omitted, and two bytes of page data (for example, 16-byte data) in page mode programming are shown. Circuits corresponding to data A and B are representatively extracted and shown. 11 is a first cell group including eight electrically erasable and re-writable memory cells corresponding to byte data A, and 12 is a second cell group including eight memory cells corresponding to byte data B.
This is a group of cells. 13 is for the transfer gate of each memory cell in the first cell group 11;
A bit line group consisting of eight bit lines each connected to one end (drain) of the MOS transistor Q _T , 14 is the gate of the MOS transistor Q _F for the floating gate of each memory cell in the first cell group 11. MOS for transfer gate
This is the first gate control line connected via the transistor 15, and belongs to the first column together with the bit line group 13. Similarly, 16 is the second
A bit line group consisting of eight bit lines each connected to one end of each transfer gate MOS transistor _QT of each memory cell in the cell group 12, 17 represents the flow of each memory cell in the second cell group 12. A second gate control line that is connected to the gate of the transfer gate MOS transistor _QF via the transfer gate MOS transistor 18, and is connected to the second gate control line along with the bit line group 16.
Belongs to a column. Reference numeral 19 denotes each transfer gate transistor Q _T of the first and second cell groups 11 and 12 and the MOS transistor 1.
This is a word line commonly connected to gates 5 and 18.

On the other hand, 20 is a write enable line, 21 is an address bus, and 22 is a first byte address for selecting byte A for decoding the address signal of this address bus 21 and selecting a column of the first cell group 11. 23 is a MOS transistor whose gate is controlled by the decoded output of the first byte address decoder 22; 24 is a MOS transistor whose gate is controlled by the signal of the write enable line 20; 25 is a flag means for setting a rewrite flag. For example, a first flip-flop (FF) circuit whose input terminal is grounded through the two transistors 23 and 24 in series; 1 column transfer gate drive circuit. 27 is a data bus, and this data bus 27 and the first cell group 1
A transfer gate transistor group 28 for storing byte data whose gate is controlled by the output of the first byte address decoder 22 and a transfer gate transistor group 28 for temporarily storing rewritten byte data are connected to the first bit line group 13. 1 byte data storage circuit group (byte data buffer) 29, a page selection transfer gate transistor group 31 whose gate is controlled by the signal of the page decoder output line 30, and the output of the first column transfer gate drive circuit 26. A column transfer gate transistor group 32 whose gate is controlled by is inserted in series. Further, 33 is a program line, and a column transfer gate transistor 34 whose gate is controlled by the output of the first column transfer gate drive circuit is inserted between the program line 14 and the first gate control line 14.

Similar to the program system corresponding to the first cell group 11, the program system corresponding to the second cell group 12 includes a second byte address decoder 35, MOS transistors 36, 37, a second
FF circuit 38, second column transfer gate drive circuit 39, byte data storage transfer gate transistor group 40, second data storage circuit group (byte data buffer) 41, page selection transfer gate transistor group 4
2. A column transfer gate transistor group 43 and a column transfer gate transistor 44 are provided.

Next, among the page mode programming operations in the ^E.sup.2 PROM, operations corresponding to byte data A and B will be described as a representative example to simplify the explanation.

Now, a case will be described in which the user selects to rewrite byte data A and not to rewrite byte data B. First, in a byte load cycle, the write enable line 20 becomes a significant level (eg, "1" level) and waits for data to be stored. Next, address signals corresponding to the selected bytes appear on the address bus 21 in sequence, and the address signals corresponding to the first cell group 11 appearing on the address bus 21 cause the first byte address decoder 2 to
The output of the second byte address decoder 35 corresponding to the non-selected byte is at the "0" level. Also, rewritten data appears sequentially on the data bus 27 in response to changes in the address signal on the address bus 21, and the first cell group 1 appearing on the data bus 27
The rewritten data corresponding to 1 passes through the transfer gate transistor group 28 and is stored in the first data storage circuit group 29.

On the other hand, the significant level “1” of the write enable line 20 and the first byte address decoder 22
When the AND with the decoded output “1” is established,
The MOS transistors 23 and 24 are each turned on, and the output of the first FF circuit 25 is inverted from the normal state of "0" level to "1" level (rewrite flag), but the second FF circuit corresponding to the non-selected byte is
FF circuit 38 is in normal state (input end is open)
The output remains at the "0" level (normal state). In this way, byte loading of the rewritten data of the page data is performed,
A rewrite flag is set corresponding to the selected byte. Note that during this byte load cycle, the first and second data storage circuit groups 29, 41 and the first,
Bit line groups 13 and 16 of second cell groups 11 and 12
The page selection transfer gate transistor groups 31 and 33 inserted between the bit line group 1 and the bit line group 1 are in an off state, regardless of the state of the column transfer gate transistor groups 32 and 43
3 and 16 and data storage circuit groups 29 and 41 are electrically separated.

After the above operation (that is, after a certain period of time has elapsed since the write enable line 20 became "1" level), an erase cycle begins. At this time, all bit lines of the bit line groups 13 and 16 are set to the ground potential by a circuit not shown, and the selected word line 19 and program line 33 are set to a high potential (for example, 20V). Then, the column transfer gate transistor 3 is controlled by the first column transfer gate drive circuit 26 controlled by the flag "1" output from the first FF circuit 25.
The gate potential of each transistor in the 4 and column transfer gate transistor group 32 is set to a high potential, and the second cam transfer gate drive circuit 39 is controlled by the flag "0" output from the second FF circuit 38. The column transfer gate transistor 44 and the column transfer gate transistor group 43 are turned off. Therefore, each floating gate transistor Q _F in the first cell group 11 has a transfer gate transistor 34 at its gate,
15, a high voltage is applied from the program line 33 to perform an erase operation, and the erase state (data "1") is established.
However, since no high voltage is applied to the gate of each floating gate transistor Q _F in the second cell group 12, no erase operation is performed.

Next, when entering the program cycle, all bit lines of the bit line groups 13 and 16 are disconnected from the ground potential, the page decoder output line 30 goes to the "1" level, and the program line 33 is set to the ground potential. . As a result, the page selection transfer gate transistor groups 31 and 42 are turned on, and the data in the first data storage circuit group 29 is turned on by the output of the transistor group 31 and the first column transfer gate drive circuit 26. The first cell group 11 passes through the column transfer gate transistor group 32 which is driven by
A high voltage is applied to the memory cell to which "0" is written, and a ground potential is applied to the memory cell to which "1" is written. In this case, a ground potential is applied to the gate of the floating gate transistor Q _F from the program line 33 via the transfer gate transistors 34 and 15, and a high voltage is applied from the bit line corresponding to the drain of the transfer gate transistor Q _T. Data "0" is written to the memory cells that have been stored, and the data contents of the other memory cells do not change. Therefore,
A column transfer gate transistor group 42 between the memory cells of the first cell group 11 to which a ground potential is applied from the first data register circuit group 29 and the bit line group 16 and the second data storage circuit group 41 No change occurs in the data of each memory cell of the second cell group 12 which is in the off state.

In page mode programming as described above, only the first cell group 11 corresponding to rewritten byte A is rewritten, and the second cell group 1 corresponding to byte B, which does not require rewriting, is rewritten.
No high voltage is applied to data 2 for erasing or writing data "0". Therefore, when the number of bytes to be rewritten during page mode programming is small, rewriting of the same data can be avoided for the remaining bytes, reducing the probability of memory cell failure and achieving highly reliable rewriting. .

Another advantage of page mode programming as described above is that it is not necessary to read and latch the data in the memory cells the moment the page mode is entered.

〔Effect of the invention〕

As described above, according to the electrically erasable and rewritable read-only memory of the present invention, page mode programming is possible in which only the data that needs to be rewritten is rewritten, avoiding rewriting the same data, and memory cells are The probability of occurrence of defects can be suppressed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a part of an embodiment of E ² PROM according to the present invention, and Fig. 2 is a circuit diagram showing a part of an embodiment of the E 2 PROM according to the present invention.
FIG. 3 is a diagram showing each cycle of page mode programming of the E ² PROM. FIG. 3 is a diagram showing a conventionally considered circuit system for page mode programming. Q _T ...Transfer gate, Q _F ...Floating gate transistor, 11, 12...Cell group, 1
3, 16... Bit line group, 14, 17... Gate control line, 15, 18, 34, 44... Transfer gate, 19... Word line, 20... Write enable line, 21... Address bus, 22, 35... Byte address decoder , 23, 24, 36, 37...
MOS transistor, 25, 38...FF circuit, 2
6, 39...Column transfer gate drive circuit,
27... Data bus, 29, 41... Data storage circuit group (byte data buffer), 30... Page decoder output line, 31, 42... Page selection transfer gate group, 32, 43... Column selection transfer gate group, 33... Program line.

Claims (1)

[Scope of Claims] A group of electrically erasable and re-writable memory cells for storing 1-byte data, and a memory cell provided corresponding to each byte-based column of the memory cell group,
A byte data buffer that temporarily stores the byte data that requires data rewriting among the page data to be written in the byte load cycle, and a byte data buffer that also corresponds to the byte data that requires data rewriting in the byte load cycle. a flag means for outputting a rewrite flag; an erase means for selecting a group of memory cells requiring data rewriting by referring to the flag output of the flag means in an erase cycle and erasing the stored data; and a page selector in a program cycle. selecting a memory cell group that requires data rewriting from among the memory cell groups that have been updated, with reference to the flag output of the flag means;
The electrical erasing method is characterized by comprising a write means for writing data corresponding to the data stored in the byte data buffer into the memory cell group.
Rewritable read-only memory. 2. An address bus to which a byte address of a memory cell group corresponding to byte data requiring data rewriting among the page data is provided, and an address bus provided corresponding to each byte data buffer,
a byte address decoder that decodes the byte address on the address bus; a data bus to which byte data of the page data that requires data rewriting is provided; and a byte address decoder provided between the data bus and the byte data buffer. a group of transfer gates for storing byte data whose conductivity is controlled by the decode output of the byte address decoder, and the flag means is provided for each byte address decoder, and the flag means is configured to communicate between the decode output of the byte address decoder and a write enable signal. is a flip-flop circuit that inverts from the normal state and outputs the rewrite flag when both exist, and conduction is controlled by the rewrite flag output of this flip-flop circuit, and the bit line of the memory cell group corresponding to the byte data buffer and and between a column transfer gate group provided between the gate of the floating gate transistor of the memory cell group and the program line, and a bit line group of the memory cell group corresponding to the byte data buffer. The electrically erasable and rewritable device according to claim 1, further comprising a group of page selection transfer gates, all of which correspond to page data to be written, are commonly controlled to be conductive. Read-only memory.