JPH07111687B2 - Data creation method for logic simulation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A logic simulation data creation method for creating expected values of instructions and data required when debugging a vector operation unit at a gate level, and a method for creating a logic simulation data For the purpose of creating data for logical simulation of arithmetic units to improve processing efficiency and reduce work, a software simulator that completely realizes the target architecture in software and a built-in software simulator, And a data output means for collecting data relating to a specified target instruction when the simulator executes the specified target instruction. The software simulator executes a system-wide test program and outputs the output data to a gate level logic of a unit arithmetic unit. To enter the simulator Configure.

[Industrial application field]

The present invention relates to a logic simulation data creation method for creating expected values of instructions and data required when debugging a vector operation unit at a gate level, and in particular,
The present invention relates to a data generation method suitable for a unit calculator which is a part of a system.

[Conventional technology]

In order to debug the vector operation unit by itself and at the gate level by logic simulation, it is necessary to supply the necessary instructions and data expectation values as inputs to the logic simulator. These are generally a collection of data according to a particular format. In the past, in order to create these data, the arithmetic unit originally coded the source image, and then converted it by compiling it into a format usable by a logic simulator using a dedicated conversion program.

[Problems to be Solved by the Invention]

The arithmetic unit in this case is actually a unit that constitutes the system, and a test program for the entire system is also present. Nevertheless, in the conventional method, it is necessary to create a dedicated program in addition to the general test program, and the complicated work of coding the test data dedicated to each arithmetic unit and the interface of each logic simulator. It requires a complicated conversion that corresponds to the above, and has a heavy burden on the development cost.

The present invention was created in view of such problems,
By detecting the target instruction from a general test program and outputting the data related to that instruction in a format that can be used in a logic simulator, the logic simulation data of each arithmetic unit is created to improve the efficiency of processing and work. It is an object of the present invention to provide a data creation method for logic simulation that aims to reduce the load.

[Means for Solving the Problems]

Means for solving the above-mentioned problems in the present invention is, as shown in the basic configuration of FIG. 1, in a data creation method for creating logic simulation data of a unit arithmetic unit as a part of a system, A software simulator 1 that completely realizes the target architecture in terms of software, and a built-in software simulator 1.
Data output means 1a for collecting data relating to a specified target instruction when the simulator 1 executes the instruction.
According to the data creation method, the software simulator 1 executes the overall test program 2 of the system, and the output data 3 is input to the gate level logic simulator 4 of the unit arithmetic unit.

[Action]

If the target arithmetic unit is a part of the system, a test program for the entire system always exists, and the test program contains instructions, control data, and arithmetic data applicable to the target arithmetic unit. There is.

The present invention intends to modify and use these instructions and data in a format corresponding to each interface. First, a software simulator that completely realizes the target architecture in terms of software is developed. This is so that the movement of each instruction and function can be simulated to be exactly the same in the logical specifications, and the test program of the entire system can be executed. Next, a means for designating a target instruction for data output and outputting data relating to the instruction when the instruction is executed is incorporated into this software simulator. The test program of the whole system is executed by this software simulator, and the output data is sampled as the gate level logic simulator input of the vector operation unit.

That is, the present invention is based on a method of executing a general test program with a software simulator to create data for a single logic simulation at the gate level of an arithmetic unit. This is due to the method of outputting in the input format of.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a data creating apparatus embodying the present invention. In FIG. 1, reference numeral 1 is a software simulator, which includes an interface unit 11 for performing a target process, an execution unit 12 for realizing an architecture, a resource unit 13 for expressing hardware resources, and data for a target instruction. The collecting unit 14 and the stack unit 15 in which the collected data is written and temporarily held are
The output unit 16 outputs the data from 15 to the outside.

The interface unit 11 knows the contents of each format, and when the target instruction of data output is designated, outputs the corresponding one. When the execution unit 12 detects these target instructions during the execution of the test program, the execution unit 12 collects them.
14 is called and data is accumulated in the stack unit 15. If the stack section 15 overflows, the output section 16
The content of is edited and output to the external data set 3.

The software simulator 1 described above completely implements the target architecture in a software manner, and it is possible to simulate the movement of each instruction and function so as to be exactly the same in the logical specifications and execute the general test program. it can.

Each function is incorporated in the software simulator 1 so that a data output target instruction is designated and when the instruction is executed, data related to the instruction is output.

A general test program is executed by this software simulator 1, and its output data is used as the external data set 3
To the input of the gate level logic simulator 4 of the vector operation unit.

FIG. 3 is a flowchart showing an example of the operation of the above-described data creation device. As shown in the figure, first, after the software simulator 1 is started, the target instruction is specified, the test program is loaded, and the simulation is started. When the stack unit 15 becomes full, the output unit 16 edits the content into a format corresponding to the target logic simulator 4 and outputs it.

FIG. 4 is a flow chart showing the simulation part of the flow of FIG. 3 in more detail, mainly showing the processing contents of the execution part 12 and the collection part 14. As shown in the figure, the execution unit 12 reads an instruction from the test program, analyzes the instruction, and calls an instruction execution routine to execute the instruction.

The instruction code and control data of various masks (PSW, CR, etc.), the contents of the operands used as operation data in those instructions, and the correct answer value of the operation result are conventionally calculated by the assembler
These are a set of data that can be used only as an input of the logic simulation control program and are dedicated programs because they are coded by the instruction and created in the program. However, the method of the present invention can be operated in an actual machine. It is intended to dynamically extract the above equivalent data from a test program, that is, TSS (Time Sharin
g System) The software simulator 1 which is the same as the real machine in terms of logical specifications operating under the control of the system is provided, and the test program can be operated by the simulator 1. Thus, the conventional one is a plurality of data sets, whereas the current one is a process.

Next, in the software simulator 1, when a specific instruction is executed, an instruction code, the contents of various control registers, and the contents of each operand used in the instruction are saved.
Incorporate 14.

Which instruction in the test program is extracted as the target of the logic simulation is performed by designating the target instruction. This is designated by the instruction code in the operation screen of the software simulator 1.

If the instruction is a target instruction, the collecting unit 14 stacks instruction codes and registers, and further stacks operands. The part surrounded by the dotted line in this figure is an important part of the present invention.

By executing a test program in the software simulator 1, virtual main memory, various registers, etc. are set in the simulator 1, and required hardware is selected from among them and collected as a hardware resource. This is stored in the stack unit 15 inside the simulator 1, and finally converted into the target format and output to the external data set 3. The data arrangement is specified in the interface with the logic simulation control program, and is the same as the conventional dedicated program created and complied after observing this specification.

The collecting unit 14 does not directly collect data from the text of the test program, but executes and collects the instruction because there is data generated during execution and the expected value cannot be known without execution. .

As described above, according to the present invention, by executing a general test program with a software simulator, it is possible to extract and edit unit simulation data of a computer even in a format that is an input to a logic simulator, and create a dedicated program. No need.

〔The invention's effect〕

As described above, according to the present invention, a test program for the entire system is executed by a software simulator, and when a target instruction is detected, the data related to the instruction is output in a format usable by the logic simulator, so that each operation is performed. It is possible to provide a logic simulation data creation method in which data for logic simulation of a container is created to improve processing efficiency and reduce work.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIGS. 3 and 4 are flowcharts of processing of an embodiment of the present invention. 1; Software simulator, 2; General test program, 3; External data set, 4; Logic simulator, 11; Interface section, 12; Execution section, 13; Resource section, 14; Collection section, 15; Stack section, 16; Output section.

Claims (1)

[Claims] 1. A data simulator for creating logic simulation data of a unit arithmetic unit as a part of a system, wherein a software simulator for completely realizing a target architecture in software, and a built-in software simulator, A data output means for collecting data relating to the specified target instruction when the simulator executes the specified target instruction, executing a system-wide test program by the software simulator, and operating the output data of the data output means as a unit operation Input to the gate-level logic simulator of the instrument. A data creation method for logic simulation characterized by the following.