JP2000222245A - Program execution time evaluating device, source program execution time evaluating device, program execution time evaluating method, and source program execution time evaluating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the detection precision of a stall caused by a program and to accurately measure the execution time of the program by bringing stall occurrence accompanying cache memory access into consideration for static stall detection based upon the program. SOLUTION: A stage state grasping part (1) has a function of grasping respective stage states when an instruction cache and a data cache are not missed, a state state grasping part (2) when the instruction cache is missed, a stage state grasping part (3) when the data cache is missed, and a stage state grasping part (4) when the instruction cache and data cache are missed. Four multipliers 16a to 16d multiply pieces 1 to 4 of stall information ST, corresponding to the respective stage state grasping parts (1) to (4), detected by a stall detection part 13 by parameters based upon an instruction cache miss rate X and a data cache miss rate Y.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program execution time evaluation apparatus and a program execution time evaluation method for evaluating a program execution time, and a source program execution method for estimating the execution time of a source program described for a microprocessor, for example. The present invention relates to a time evaluation device and a source program execution time evaluation method.

[0002]

2. Description of the Related Art A developer of a program for an embedded microprocessor must always grasp the state of the execution time of the program being developed for the microprocessor. That is, the execution time is the shortest in the optimum state, but it is necessary to grasp whether the execution time satisfies the specification even under the worst conditions.
It is also necessary to grasp the average execution time in a typical state in designing the overall system.

[0003] Modern microprocessors have become more integrated and faster due to improvements in semiconductor technology, have an internal instruction pipeline structure, and have a VLIW (Very Lon).
gInstruction Word) and super scalar technology are adopted, and a large-capacity cache memory is mounted, which is further complicated. Further, a peripheral circuit specialized for an application is being mounted on the same silicon.

Conventionally, as an environment in which the execution time can be measured, there is an environment in which a real microprocessor such as an emulator or an evaluation board is mounted. However, development of an actual microprocessor takes a long time due to the above situation, and it is not expected that an emulator or an evaluation board environment is always provided from an early stage of program development due to development time and cost problems.

On the other hand, the speedup and cost reduction of a general computer environment has made it possible to construct an environment for simulating the operation of a microprocessor by software. However, from the viewpoint of accurately measuring the execution time, even a simple processor can be executed in terms of time and cost, but the above-mentioned complicated processor can perform instruction-level logical execution. Few simulators can accurately measure execution time even if they are obtained. Further, even if the execution time can be accurately measured, the simulation execution speed is low, so that it takes a long time to obtain a result, and the program development efficiency is low.

As a countermeasure against such a problem, there is a technique proposed in Japanese Patent Application No. 9-231331. In order to optimally program a complicated microprocessor program, an environment for developing a program while detecting a stall is proposed.

FIG. 8 is a block diagram showing a configuration of a stall detection display device disclosed in Japanese Patent Application No. 9-231331.

In this stall detection and display device, a file of a source program is read by a file control unit 103 in a GUI unit 101 for controlling a user interface, and a check range obtaining unit 104 obtains a stall detection range.

Then, the text interpreting section 109 of the internal processing section 102 interprets each command line of the text character string in the source program, and the stage information creating section 110 creates stage information based on the interpretation result. Further, the stall information creating unit 110 detects stalls that have occurred and creates stall information, and at the same time, the image information creating unit 112 creates pipeline image information in the pipeline processing.

After performing such a series of processing for all instruction lines in the stall detection range, the coloring information creating unit 105 creates stall coloring information, and the image display unit 106 displays pipeline image information. The stall information coloring unit 107 colors the stall information.

According to the stall detection display device, the trace result of the instruction level simulator is inputted, the instruction arrangement of the program is interpreted, the stall generated in the microprocessor is detected, and the optimality of the program and the time required for execution are reduced. Can be requested.

FIG. 9 shows a development flow using the stall detection display device.

In FIG. 1, a high-paid-language source program (201) such as the C language, for example, has a compiler (20).
Compiled by 2) and converted into machine language (203). Further, the object loader (204) receives the machine language and stores the object program in the memory unit (20).
5), and the program from the memory unit (205) is passed to the instruction execution unit (206).

On the other hand, a correspondence table (208) between a machine language and a source program is created based on the load information of the object loader (204), and debug control (208) is performed based on the table, and the result is stored in the instruction execution unit. (20
6) and the user interface (209).

Then, the instruction trace result (210) obtained by the instruction execution unit (206) is input to a stall detection unit (the stall detection display device of FIG. 8) to obtain a stall detection result (213). The execution time is determined and a stall is displayed (214).

The optimization of the program is performed by coding the program source so as to reduce the stall as much as possible from the stall detection result. The execution time T
Is determined using the following relational expression.

[0017]

(Equation 1) CPIi = (1 + Si / Ni) (1) where Ni: the number of instructions in the range in which stall detection is performed CPIi: the average number of clocks required for one instruction in the above range C: the operating cycle of the processor (period per clock) ) Si: the number of stall cycles in the above range Note that the CPI when there is no stall is set to 1.

In the end, the expression (1) indicates that a program is optimized for its processor by focusing on a certain program range and minimizing the number of stalls and the number of instructions in this range. In other words, the total execution time can be determined by the number of executed instructions and how much stall is occurring.

[0019]

However, the execution time obtained by the conventional apparatus shown in FIG. 8 corresponds to the case of a limited condition in an actual processor. This is because the actual number of stall cycles Si is given by the following equation.

Si = (Sstatic + Smemory) where Sstatic: instruction placement stall number Smemory: memory stall In the above conventional device, only the Sstatic value is detected.
No Smemory value was detected. This means that in microprocessors with cache memory,
The cache memory miss rate always corresponds to 0 (a situation that always hits). In practice, the Smemory value cannot be 0 depending on the program flow. For this reason, there is a problem that the execution time is always smaller than the execution time in the actual processor.

As is apparent from FIG. 9, in order to obtain the entire execution time, an execution environment such as a simulator for obtaining all execution traces is assumed. Further, since stall detection must be performed for all execution traces, it may take a long time to detect a stall when the trace result is huge. Focusing on a small source program portion, it is redundant to perform stall detection on all execution traces, even though a stall cycle with the same pattern occurs repeatedly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to improve the detection accuracy of a stall generated in a program and accurately measure the execution time of the program. It is an object of the present invention to provide a program execution time evaluation device and a program execution time evaluation method capable of performing the above. Another object of the present invention is to improve the accuracy of detecting a stall generated in a source program to accurately measure the execution time of the source program, and to quickly measure the execution time of the source program by efficiently executing the stall detection. An object of the present invention is to provide a source program execution time evaluation device and a source program execution time evaluation method.

[0023]

In order to achieve the above object, a program execution time evaluation apparatus according to the present invention is characterized by an interpreting means for interpreting a program, and a program executed by the interpreting means. Regarding the interpretation result,
Each stage state when the instruction cache and data cache did not miss, each stage state when the instruction cache missed, each stage state when the data cache missed, and when the instruction cache and the data cache missed Stage state grasping means for grasping each stage state in the case of doing, stall detection means for detecting a stall occurring in pipeline processing of a program obtained by the stage state grasping means, and outputting the detected stall information, An instruction cache miss ratio designating unit for designating an instruction cache miss ratio; a data cache miss ratio designating unit for designating a data cache miss ratio; stall information output from the stall detecting unit; Life Cache miss rate, and on the basis of the data cache miss rate obtained from the data cache miss rate designating means is to have a run time calculation means for calculating the execution time of the program.

A feature of the source program execution time evaluation apparatus according to the second aspect of the present invention is that a flow of a source program is analyzed, a divided program is generated based on a result of the flow analysis, and a source program in each divided program is generated. Source program dividing means for outputting the position information of each of the divided programs and the number of times of execution of each of the divided programs; a designated value of an instruction cache miss ratio, a data cache miss, together with the position information and the number of executions outputted from the source program dividing means; 2. A divided program execution information storage unit for storing a designated value of a rate and a divided program execution time corresponding to each of the divided programs, a program execution time evaluation device according to the invention of claim 1, and the divided program execution information storage. From the location information on the source program stored in the means. The source program portion to be executed is input to the program execution time evaluation device together with the instruction cache miss rate and the data cache miss rate, and the obtained execution time of the divided program is stored in the divided program execution information storage means. A program execution time measuring means for outputting the program execution time to the storage area, and a total program execution time calculation for calculating the program execution time by summing up the number of executions and the execution time of the divided program recorded in the program execution information storage means Means.

According to a third aspect of the present invention, in the source program execution time evaluating apparatus according to the second aspect of the present invention, the source program execution time estimating apparatus includes: A data access information detecting means for detecting data access information, a data access information storing means for storing the data access information in the divided program execution information storing means, and a program for storing the divided program stored in the divided program execution information storing means. A cache miss rate setting unit that sets the instruction cache miss rate based on the number of executions and sets the data cache miss rate based on the data access information and the number of times the divided program is executed.

A feature of the program execution time evaluation method according to the fourth aspect of the present invention is that an interpreting process for interpreting a program,
Regarding the interpretation result of the program obtained by the interpretation processing, each stage state when the instruction cache and data cache did not miss, each stage state when the instruction cache missed, and each stage state when the data cache missed Detecting a stage state, a stage state grasping process for grasping each stage state when the instruction cache and the data cache miss, and a stall occurring in a pipeline process of a program obtained by the stage state grasping process, Stall detection processing for outputting the detected stall information, and calculating the execution time of the program based on the stall information output from the stall detection processing, a predetermined instruction cache miss rate, and a predetermined data cache miss rate. Execution time calculation It is to execute the process.

A feature of the source program execution time evaluation method according to the fifth aspect of the present invention is that a flow of a source program is analyzed, a divided program is generated based on a result of the flow analysis, and a source program in each divided program is generated. Using the instruction cache miss rate and the data cache miss rate for a source program division process for obtaining position information of the source program and the number of times of execution of each of the divided programs, and for a source program portion obtained from position information on the source program. And executing the program execution time evaluation method according to the invention of claim 4 to determine the execution time of the divided program; executing the divided program obtained in the execution time measurement process; Aggregate the number of executions of the divided program obtained in the process and It is to run the total program execution time calculating process for calculating a program execution time.

According to a sixth aspect of the present invention, in the method of evaluating a source program execution time according to the fifth aspect of the present invention, the division of the source program is performed based on a flow analysis result of the source program dividing process. A data access information detection process for detecting data access information in a program, and the instruction cache miss rate is set based on the number of executions of the divided program obtained in the source program division process, and the data access information and the And a cache miss ratio setting process for setting the data cache miss ratio based on the number of executions of the divided program.

[0029]

Embodiments of the present invention will be described below.

(First Embodiment) FIG. 1 is a block diagram showing a functional configuration of a program execution time evaluation device according to a first embodiment of the present invention.

The program execution time evaluation device 10 comprises:
It has a source program reader 11 for reading a microprocessor source program, and a source program interpreter 12 for interpreting the read source program. Further, on the output side of the source program interpreting section 12, a stage state grasping section (1), a stage state grasping section (2), a stage state grasping section (3), and a stage state grasping section (4) are sequentially provided. Is connected.

The stage state grasping unit (1) determines that the instruction cache and the data cache do not miss the interpretation result of the source program obtained by the source program interpretation unit 12 (Imiss = 0%, Dmiss
= 0%), and the stage state grasping unit (2) has a function of grasping each stage state when the instruction cache misses (Imiss = 100%, Dmiss = 0%). Having. Further, the stage state grasping section (3) has a function of grasping each stage state when the data cache misses (Imiss = 0%, Dmiss = 100%). When the cache and the data cache miss (Imiss = 100%, Dmiss = 100
%) Has a function of grasping the state of each stage.

A stall detecting unit 13 is connected to the output side of each of the stage state grasping units (1) to (4). The stall detection unit 13 detects a stall occurring in the pipeline processing of the source program, obtained by each of the stage state grasping units (1) to (4), and detects the detected stall information ST1.
To ST4.

An instruction cache miss ratio designating unit 14 for designating an instruction cache miss ratio and a data cache miss ratio designating unit 15 for designating a data cache miss ratio are provided. The output sides of the rate specifying unit 15 and the stall detecting unit 13 are connected to the execution time calculating unit 16.

The execution time calculation unit 16 includes the stall detection unit 1
3, execution of the source program from stall information ST1 to ST4 output from instruction cache error rate X obtained from instruction cache miss rate specifying section 14, and data cache miss rate Y obtained from data cache miss rate specifying section 15. It has a function to calculate time. In particular,
The execution time calculation unit 16 has four multipliers 16a to 16d and one adder 16e. Four multipliers 16a
16 to 16d are stall information ST1 to ST4 corresponding to the respective stage state grasping units (1) to (4) detected by the stall detecting unit 13, and parameters based on the instruction cache miss rate X and the data cache miss rate Y. Respectively. Then, the multiplication results of the multipliers 16a to 16d are added by the adder 16e to calculate the execution time of the source program.

Here, the multipliers 16a, 16b, 16c,
16d are (1
-X) (1-Y), X (1-Y), (1-X) Y, XY
Are represented by the following equations.

In this embodiment, a linear programming method is used for calculating the execution time based on the instruction cache miss rate and the data cache miss rate. For extremely short programs, it is necessary to confirm that such a calculation method can provide sufficient accuracy.
Hereinafter, description will be given with reference to FIGS. 2, 3, and 4. FIG. FIG. 2 is a diagram showing a program example of the present embodiment, and FIGS. 3A to 3D are diagrams showing a program pipeline operation of the present embodiment. In addition, FIG.
(E) is a diagram showing a pipeline operation that is close to actual.

As an example, consider the case of reading from an array described in the C language and assigning it to a variable. FIG. 2 shows the compilation results (instructions I1 to I4).

In the configuration shown in FIG. 1, the pipeline states when the instruction cache miss rate is 0% and 100% and the data cache miss rate is 0% and 100% are shown in FIGS. It is shown in d). Specifically, FIG.
3A shows the state of the pipeline when both the instruction cache miss rate and the data cache miss rate are set to 0%, and FIG. 3B shows the pipeline when the instruction cache miss rate is 100% and the data cache miss rate is 0%. %, And FIG. 3C shows the pipeline when the instruction cache miss ratio is 0% and the data cache miss ratio is 100%, and FIG. Means that both the instruction cache miss rate and the data cache miss rate are 1
The state of the pipeline when it is set to 00% is shown.

A case where both the instruction cache miss rate and the data cache miss rate are 0% (FIG. 3 (a))
In this case, the pipeline stall does not occur from the instruction I1 to the instruction I4, and the execution cycles F, D, E, M, and W are shifted by one cycle, and are executed in eight cycles in total.

The case where the instruction cache miss rate is 100% and the data cache miss rate is 0% (FIG. 3)
In (b)), three cycles of pipeline stall occur in each execution cycle F from instruction I1 to instruction I4, and as a result, the whole is executed in 20 cycles, and +
A 12-cycle stall has occurred.

The case where the instruction cache miss rate is 0% and the data cache miss rate is 100% (FIG. 3)
In (c)), a three-cycle pipeline stall occurs in the execution cycle M of the instruction I3 and a three-cycle pipeline stall occurs in the execution cycle E of the instruction I4. +3
A cycle stall has occurred.

In the case where both the instruction cache miss rate and the data cache miss rate are 100% (FIG. 3
(D)) In each execution cycle F of the instructions I1, I2, and I3, a pipeline stall of three cycles occurs,
Further, a pipeline stall of three cycles occurs in the execution cycle M of the instruction I3, and a pipeline stall of six cycles occurs in the execution cycle F of the instruction I4. As a result, the whole is executed in 23 cycles and a stall of +15 cycles occurs. are doing.

However, in the case of an actual microprocessor, the situations shown in FIGS. 3B and 3D are unlikely to occur. This is because, due to the principle of instruction locality, the miss rate of the instruction cache will be at most about 20%. If so, the instruction cache miss occurs once in every five instructions, so that no instruction cache miss occurs for the four instructions (I1 to I4) shown in FIG. May cause a cache miss.

FIGS. 4 (a) to 4 (e) show a pipeline operation close to the actual operation taking this into consideration.

The case where the instruction cache miss rate is 20% and the data cache miss rate is 0% (FIG. 4)
In (a)), three cycles of pipeline stall occur in the execution cycle F of the instruction I1, and as a result,
Execution is performed in one cycle, and a +3 cycle stall has occurred.

A case where the instruction cache miss rate is 20% and the data cache miss rate is 0% (FIG. 4)
In (a)), three cycles of pipeline stall occur in the execution cycle F of the instruction I1, and as a result,
Execution is performed in one cycle, and a +3 cycle stall has occurred.

In the first case (FIG. 4B) where the instruction cache miss rate is 20% and the data cache miss rate is 100%, three cycles of pipeline stall occur in the execution cycle F of the instruction I1. And the instruction I
As a result of the execution of the pipeline stall of 3 cycles in the execution cycle M of 3 and the execution cycle E of the instruction I4, the entire execution is performed in 14 cycles and a stall of +6 cycles occurs.

In the second case (FIG. 4C) where the instruction cache miss rate is 20% and the data cache miss rate is 100%, three cycles of pipeline stall occur in the execution cycle F of the instruction I2. And the instruction I
As a result of the execution of the pipeline stall of 3 cycles in the execution cycle M of 3 and the execution cycle E of the instruction I4, the entire execution is performed in 14 cycles and a stall of +6 cycles occurs.

In the third case (FIG. 4D) where the instruction cache miss rate is 20% and the data cache miss rate is 100%, three cycles of pipeline stall occur in the execution cycle F of the instruction I3. And the instruction I
As a result of the execution of the pipeline stall of 3 cycles in the execution cycle M of 3 and the execution cycle E of the instruction I4, the entire execution is performed in 14 cycles and a stall of +6 cycles occurs.

In the fourth case (FIG. 4 (e)) where the instruction cache miss rate is 20% and the data cache miss rate is 100%, five cycles of pipeline stall occur in the execution cycle M of the instruction I3. And the instruction I
As a result of the 7-cycle pipeline stall occurring in the execution cycle F of 4, the entire execution is performed in 15 cycles, and a stall of +7 cycles occurs.

As described above, from the pipeline operations shown in FIGS. 3 and 4, assuming that an instruction cache miss occurs on average, a stall of +3 cycles occurs for four instructions and a further +3 cycle occurs if a data cache miss occurs. Therefore, a stall of approximately +6 cycles is generated by four instructions. When this situation is evaluated by the program execution time evaluation apparatus of the present embodiment shown in FIG.

## EQU2 ## = ST2 × X × (1-Y) + ST3 × (1-X) × Y + ST4 × X × Y = 12 × 0.2 × (1-1) + 3 × (1-0.2) × 1 + 15 × 0.2 × 1 = 5.4, which is a value that is not so far away but a value that is actually approximated.

Then, the execution time is calculated by substituting the number of stall cycles obtained by the above method into the above-mentioned conventional relational expression (1).

As described above, according to the present embodiment, the occurrence of stall due to cache memory access is taken into account. For example, when detecting the stall of an extremely short source program, the execution time can be calculated with high accuracy. Can be.

(Second Embodiment) FIG. 5 is a block diagram showing a functional configuration of a source program execution time evaluation device according to a second embodiment of the present invention.

This source program execution time evaluation device 2
0 includes a source program flow analysis unit 21, a divided program execution information storage unit 22, a divided program execution time measurement unit 23, and a total program execution time calculation unit 24.

The source program flow analysis unit 21 reads a microprocessor source program and analyzes the program flow, and converts the source program into a sequential unit 22X, a loop unit 22Y, and a subroutine unit (procedure call unit) 22Z. It has a function of outputting the position information (hereinafter simply referred to as source position information) of the divided program on the source program and outputting the number of times of execution of each divided program.

The divided program execution information storage section 22 stores a program flow analysis section 2 corresponding to each divided program.
Storage area 2 for storing source position information output from 1
2a, a storage area 22b for storing the specified value of the instruction cache miss rate, a storage area 22c for storing the specified value of the data cache miss rate, a storage area 22d for storing the execution time of the divided program, and the execution of the divided program. And a storage area 22e for storing the number of times.

The divided program execution time measuring section 23
Inputs the source program portion obtained from the source position information stored in the divided program execution information storage unit 22 to the evaluation device 10 of the first embodiment together with the instruction cache miss rate and the data cache miss rate, and It has a function of obtaining the execution time of the program and outputting it to the divided program execution time storage area 22d in the divided program execution information storage unit 22.

Further, the total program execution time calculation section 24
Has a function of calculating the execution time of the source program by counting the number of times of execution of the divided program and the execution time of the divided program recorded in the divided program execution information storage unit 22.

For example, when a program as shown in FIG. 6 is input, first, the source program flow analysis unit 21
Stores the source position and the number of times of execution in the divided program execution information storage unit 22 in FIG. 5 corresponding to each arrow in FIG.

Next, the average instruction cache miss rate and data cache miss rate are input according to the configuration of the program. For example, the function func () of the program in FIG.
Since it is in a for loop executed ten times, it can be seen that the miss rate of the instruction cache is 10%. In this way, the miss rate of the instruction cache and the miss rate of the data cache of each section are manually input.

When this input is completed, the execution time for each execution of each program portion is input to the evaluation device shown in the first embodiment and obtained. Finally, multiplication is performed by multiplying the execution time of each program part by the number of executions.

In short, in this embodiment, the input microprocessor source program is divided to create a divided source program. For each of the divided source programs, stall detection is performed by adding a condition that the access to the instruction cache memory is missed or not, and the access miss to the data cache memory is not missed. Then, each execution time obtained from the stall detection result corresponding to each condition is stored in correspondence with the divided source program.

On the other hand, the execution flow of the input source program is analyzed to obtain the number of executions of the divided source program. The number of executions is also stored for each divided source program. The user specifies an instruction cache miss rate and a data cache miss rate for each divided source program.

Then, from the stall detection result, the instruction cache miss rate and the data cache miss rate, the time required to execute each divided source program once is obtained. Finally, the execution time of the input source program is determined by multiplying the execution time per execution of the divided source program by the number of executions, and integrating the result.

With this method, the total execution time of the input microprocessor source program can be reduced by:
It can be obtained with a small amount of stall detection, and the efficiency of stall detection can be increased.

(Third Embodiment) FIG. 7 is a block diagram showing a functional configuration of a program execution time evaluation device according to a second embodiment of the present invention.

In the program execution time evaluation device 30, in the program execution time evaluation device of the second embodiment, the source program flow analysis unit 21 detects data access in the divided program from the flow analysis, and Is added, and this is newly designated as a source program flow analysis unit 21A.
Further, the sequential unit 2 of the divided program execution information storage unit 22
A storage area 22f for the data access information output from the source program flow analysis unit 21A is added to each area of the 2X, the loop unit 22Y, and the subroutine unit 22Z. A cache miss ratio setting means for setting an instruction cache miss ratio from the number of executions of the source program stored in the divided program execution information storage section 22A and setting a data cache miss ratio from the number of times of execution of the data access information and the source program 31 are provided.

According to this embodiment, the miss ratio of the instruction cache and the data cache set in the second embodiment is set for a portion which is found from the result of the flow analysis. For example, in the program shown in FIG. 6, the fact that access to the array [] occurs only once is stored as the data access information 22f of the divided program execution information. When it is time to set the cache miss rate, this information
Since it is known that the access to ay [] causes a 100% cache miss, this is automatically set as the data cache miss rate.

If the number of executions of the divided program portion is known from the program flow analysis and it is clear that the source program is sufficiently small, there is a portion where the miss rate of the instruction cache can be automatically set. If the instruction cache miss rate is obvious from the program flow,
For example, a program path that passes only once makes a 100% miss, and a code that loops twice locally makes a 50% miss, and so on.

As described above, in the present embodiment, when a trivial cache miss ratio is found, it is automatically set. Therefore, the setting of the cache miss ratio is labor-saving, and the measurement accuracy of the execution time is improved. be able to.

[0073]

As described above in detail, according to the program execution time evaluation apparatus according to the first aspect of the present invention and the program execution time evaluation method according to the fourth aspect of the present invention, a static stall based on a program is performed. Since the stall generation accompanying the cache memory access is added to the detection, the accuracy of the stall detection can be improved, and the execution time of the source program can be accurately obtained.

According to the source program execution time evaluation apparatus of the second aspect and the source program execution time evaluation method of the fifth aspect, static stall detection based on the source program accompanies cache memory access. Since stall occurrence is taken into account, the accuracy of stall detection can be improved, and the execution time of the source program can be accurately obtained. Furthermore, the execution time of the source program can be measured at high speed by the efficient execution of stall detection.

According to the source program execution time evaluation device of the third aspect and the source program execution time evaluation method of the sixth aspect of the present invention, in the source program execution time evaluation device of the second aspect, a self-evident cache is used. When the miss rate is found, it can be automatically set, so that the setting of the cache miss rate can be saved and the execution time measurement accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a functional configuration of a program execution time evaluation device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a program according to the first embodiment;

FIG. 3 is a diagram showing a program pipeline operation of the first embodiment.

FIG. 4 is a diagram showing a pipeline operation that is close to the actual operation.

FIG. 5 is a block diagram showing a functional configuration of a program execution time evaluation device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a program according to a second embodiment.

FIG. 7 is a block diagram showing a functional configuration of a program execution time evaluation device according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional stall detection display device.

9 is a diagram showing a development flow using the stall detection display device shown in FIG.

[Explanation of symbols]

 10, 20, 30 Program execution time evaluation device 11 Source program reading unit 12 Source program interpretation unit 13 Stall detection unit 14 Instruction cache miss ratio designation unit 15 Data cache miss ratio designation unit 16 Execution time calculation unit 21, 21A Source program flow analysis Unit 22, 22A divided program execution information storage unit 23 divided program execution time measurement unit 24 total program execution time calculation unit 31 cache miss rate setting means

Claims (4)

[Claims] An interpreting means for interpreting a program; and an interpretation result of the program obtained by the interpreting means, each stage state when an instruction cache and a data cache do not miss, A stage state grasping means for grasping each stage state, each stage state when the data cache misses, and each stage state when the instruction cache and the data cache miss, and a stage state grasping means. Stall detection means for detecting stalls occurring in pipeline processing of a program and outputting the detected stall information; instruction cache miss rate designating means for designating an instruction cache miss rate; and data cache for designating a data cache miss rate. Miss rate Based on the stall information output from the stall detecting means, the instruction cache miss rate obtained from the instruction cache miss rate specifying means, and the data cache miss rate obtained from the data cache miss rate specifying means. A program execution time evaluation device, comprising: execution time calculation means for calculating an execution time of a program. 2. Analyzing the flow of a source program, generating a divided program based on the flow analysis result, and outputting position information on the source program in each of the divided programs and the number of times of execution of each of the divided programs. A source program dividing unit, the designated value of the instruction cache miss ratio, the designated value of the data cache miss ratio, and the divided program execution time, together with the position information and the number of executions output from the source program dividing unit. A divided program execution information storage unit that stores the program in association with the program; a program execution time evaluation device according to claim 1; and a source program part obtained from position information on the source program stored in the divided program execution information storage unit The instruction cache miss rate and the data A divided program execution time measuring unit that inputs the program execution time evaluation device together with the cache miss rate and outputs the obtained divided program execution time to a divided program execution time storage area in the divided program execution information storage unit; A total program execution time calculating means for calculating the program execution time by totalizing the number of executions and the execution time of the divided programs recorded in the divided program execution information storage means. Evaluation device. 3. An interpreting process for interpreting a program, and, regarding an interpreted result of the program obtained by the interpreting process, each stage state when an instruction cache and a data cache do not miss, and when an instruction cache misses, A stage state grasping process for grasping each stage state, each stage state when the data cache misses, and a stage state when the instruction cache and the data cache miss, respectively, are obtained by the stage state grasping process. A stall detection process for detecting a stall occurring in a pipeline process of a program and outputting the detected stall information; stall information output from the stall detection process, a predetermined instruction cache miss rate, and a predetermined data cache miss Based on rate And an execution time calculation process for calculating an execution time of the program. 4. A source for analyzing a flow of a source program, generating a divided program based on a result of the flow analysis, and obtaining position information on the source program in each of the divided programs and the number of times of execution of each of the divided programs. And executing the program execution time evaluation method according to claim 4 using the instruction cache miss ratio and the data cache miss ratio for a source program portion obtained from position information on the source program. The execution time measurement processing for obtaining the execution time of the divided program, the execution time of the divided program obtained in the execution time measurement processing, and the number of times of execution of the divided program obtained in the source program division processing are totaled. Execute the total program execution time calculation processing to calculate the program execution time Source program execution time evaluation method characterized by.