JPH07111651A - Moving image compression coding device and compression moving image recording device - Google Patents

Abstract

PURPOSE:To make an encoding device which is immune to error and is suitable to a high speed reproduction when a coding is performed to moving picture data by using an inter-frame predictive coding. CONSTITUTION:The DC coefficient and the AC coefficient from a DCT conversion quantization circuit 4 are coded in a DC coefficient coding circuit 5 and an AC coefficient coding circuit 6, respectively, and are classified in slices based on the slice synchronizing signal S from a slice synchronizing signal generation circuit 16. At this time, when the frame from an input terminal 1 is set to an intra-frame by a picture mode setting circuit 17, the period of the slice synchronizing signal S at this time becomes 1/2 to 1/5 times as long as that of the slice synchronizing signal S when an input frame is made a non-intra-frame. Thus, the slice size of the intra-frame becomes 1/2 to 1/5 times as long as that of the slice size of the non-intra-frame and the slice sizes of the intra-frame and the non-intra-frame becomes almost equal after coding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture compression coding apparatus for compressing and coding moving picture data using inter-frame prediction, and a compressed moving picture recording for recording the compression coded moving picture data on a recording medium. The present invention relates to an apparatus, and more particularly, to an encoding apparatus and a recording apparatus capable of suppressing error occurrence when recording / reproducing is performed by a recording / reproducing apparatus such as a VTR and image quality deterioration due to high-speed reproduction.

[0002]

2. Description of the Related Art Regarding an encoding method for compressing a moving image,
Standardization of a method using interframe predictive coding is in progress. About this, Journal of Image Electronics Engineers, Vol. 20, No. 4
No. (1991) pp. 306-316. This standardization work started on storage media such as CD-ROMs, but applications to communications and broadcasting are also being considered. Coding element technologies are interframe prediction with motion compensation and DCT (discrete cosine transform).

The inter-frame prediction is to encode the difference from the prediction value obtained from the previous reproduced image, but in order to realize random access, the intra-frame coding is performed without taking the prediction difference. A frame is inserted every predetermined number of frames. Hereinafter, a frame for intra-frame coding will be referred to as an intra frame, and a frame for coding a prediction difference will be referred to as a non-intra frame.

When interframe predictive coding is performed, DCT (discrete cosine transform) of such a frame is performed.
This DCT is performed every 8 × 8 pixels. This 8 × 8 pixel block is referred to as a 1DCT block. Further, a 6DCT block including a 2 × 2 DCT block of a luminance signal and one DCT block of two color difference signals constitutes a macroblock as a minimum unit of an image, and encoding is performed in units of this macroblock. The number of DCT blocks forming the macroblock differs between the luminance signal and the color difference signal because the sampling of the luminance component and the color difference component is different.

In actual coding, the macroblock address indicating the position of each macroblock on the screen is coded. At this time, the difference from the address of the immediately preceding macroblock is coded. In addition, the motion vector information used for inter-frame prediction also encodes the difference from the previous macroblock. Further, among the DCT coefficients obtained by the DCT, the DC coefficient related to the DC component is the DCT immediately before the same signal such as the luminance signal.
Encode the difference from the block. These difference processing,
To protect against errors, it is reset at the beginning of a unit called a slice consisting of a plurality of consecutive macroblocks. The size of the slice can be changed depending on the error condition of the transmission path.

[0006]

However, although the above-mentioned conventional technique protects the slice from an error, it has the following problems.

That is, in general, the code amount of a coded intra frame is between 2 and 5 times the code amount of a coded non-intra frame. Therefore, when the intra-frame and the non-intra frame are encoded with the same slice size, the intra-frame slice data becomes larger than the non-intra-frame slice data. Here, large slice data means low tolerance to errors. For this reason, the intra frame serves as a reference for prediction of other frames, but the spread range of the error is wide, and the intra frame having a high degree of importance is less resistant to the error. In the above-mentioned conventional technique, the slice size can be arbitrarily selected, but the relation between the slice sizes of the intra frame and the non-intra frame is not considered.

When a moving image signal encoded by a recording / reproducing apparatus such as a VTR is recorded / reproduced on / from a recording medium, the encoded data is divided into fixed lengths to form a synchronization block, which is sequentially recorded. I am trying. Then, the error correction processing at the time of reproduction is performed in units of this synchronous block, and at the time of high-speed reproduction, the data is reproduced in units of synchronous blocks. Therefore, in order to efficiently use the reproduced data, it is desirable that one or two slices be included in the synchronization block, but this has not been taken into consideration either.

It is an object of the present invention to provide a moving picture compression coding apparatus and a compressed moving picture recording apparatus which solves such a problem, is resistant to errors and is suitable for high speed reproduction.

[0010]

In order to achieve the above object, a moving picture compression coding apparatus according to the present invention is configured so that a slice size of a non-intra frame before coding is equal to a slice size of an intra frame before coding. Means for reducing the size are provided. In particular, the slice size of an intra frame is 1 / the slice size of a non-intra frame.
2 to 1/5 times.

Further, the moving picture compression coding apparatus according to the present invention uses a means for detecting the data amount of the encoded slice and the detection output so that the data amount of the encoded slice becomes substantially constant. And a means for setting the slice size before encoding.

In order to achieve the above object, the compressed moving image recording apparatus according to the present invention converts a data stream so that the slice size of an intra frame becomes small when recording moving image data that has already been subjected to interframe predictive coding. The means to do is provided.

[0013]

When an intra frame and a non-intra frame having the same slice size are coded, the slice size of the intra frame becomes larger than the slice size of the non-intra frame, and becomes 2 to 5 times. According to the present invention, the slice size of an intra frame is smaller than the slice size of a non-intra frame by ½ before encoding.
~ 1/5 times, so these intra frames,
When the non-intra frames are coded, their slice sizes are approximately equal.

The slice size of each frame before encoding is variable, and each slice size is set so that the data amount of encoded slices is always constant.
The slice size of the intra-frame after encoding and the slice size of the non-intra frame are almost equal. In this case, before encoding, the slice size of the intra frame is smaller than the slice size of the non-intra frame.

When recording moving image data that has been interframe predictive coded, the slice size of the coded intra frame is reduced, so that the slice size of the intra frame and that of the non-intra frame are made substantially equal. Therefore, it is possible to include one or two slices in one recording synchronization block even for an intra frame.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a moving picture compression encoding apparatus according to the present invention, in which 1 is an input terminal, 2 is a motion compensation prediction difference processing circuit, 3 is a switch, 4 is a DCT transform quantization circuit, 5 is a DC coefficient coding circuit, 6 is an AC coefficient coding circuit, 7 is an inverse quantization inverse DCT conversion circuit, 8 is a multiplexing circuit, 9 is an additional information coding circuit, 10 is a buffer, 11 is an output terminal, and 12 is Rate control circuit, 13 is a small slice size setting circuit, 14 is a large slice size setting circuit, 15
Is a switch, 16 is a slice synchronization signal generating circuit, and 17 is a picture mode setting circuit.

In the figure, image data is sequentially input from the input terminal 1 for each frame. The picture mode setting circuit 17 sets the intra mode or the non-intra mode for each frame from the input terminal 1, and the motion compensation prediction difference processing circuit 2, the switches 3 and 15 and the additions are made according to the setting mode. The information coding circuit 9 and the like are controlled.

Now, assuming that the intra mode is set by the picture mode setting circuit 17, the switch 3,
15 is closed to the I side, and the frame input from the input terminal 1 at that time is directly supplied to the DCT transform quantization circuit 4 via the switch 3 as an intra frame. Further, if the non-intra mode is set by the picture mode setting circuit 17, the switches 3 and 15 are closed to the NI side, and the frame input from the input terminal 1 at that time is a non-intra frame, and the motion compensation prediction difference processing is performed. It is supplied to the circuit 2. This motion compensation prediction difference processing circuit 2
Then, the prediction difference from the reference frame from the inverse DCT transform inverse quantization circuit 7 is calculated, and the difference data thus obtained is supplied to the DCT transform quantization circuit 4 via the switch 3.

In the DCT transform quantization circuit 4, the input intra-frame or non-intra-frame data is DCT processed in DCT block units as described above,
Further, the DCT coefficient obtained by the DCT process is quantized based on the quantization width information Q from the rate control circuit 12. The DC coefficient of the quantized DCT coefficients is D
The C coefficient coding circuit 5 and the AC coefficient are coded by the AC coefficient coding circuit 6, respectively.

D output from the DCT transform quantization circuit 4
The CT coefficient is also supplied to the inverse quantization inverse DCT conversion circuit 7, is inversely quantized on the basis of the quantization width information Q from the rate control circuit 12, and is inverse DCT-transformed to be the original reference frame. The frame is played.

On the other hand, the small slice size setting circuit 13 and the large slice size setting circuit 14 respectively output information for determining the slice size, and the picture mode setting circuit 17
Is set to the intra mode, the information from the small slice size setting circuit 13 is set, and when the picture mode setting circuit 17 is set to the non-intra mode, the information from the large slice size setting circuit 14 is set. It is supplied to the slice synchronization signal generation circuit 16 via the switch 15. Here, the slice size according to the information from the small slice size setting circuit 13 is smaller than the slice size according to the information from the large slice size setting circuit 14.

The slice synchronizing signal generating circuit 16 generates the slice synchronizing signal S at a cycle corresponding to the information.
The cycle of the slice synchronization signal S generated by the information from the small slice size setting circuit 13 is shorter than the cycle of the slice synchronization signal S generated by the information from the large slice size setting circuit 14. However, these slice synchronization signals S are synchronized with the DC coefficient output from the DCT transform quantization circuit 4 and have a cycle that is an integral multiple of the cycle of the macroblock.

The DC coefficient coding circuit 5 codes the quantized DC coefficient in synchronization with the slice synchronization signal S. Here, the DC coefficient when the slice synchronization signal S is supplied is encoded as it is, but for the other DC coefficients, the difference from the previous DC coefficient is encoded.

Further, the additional information encoding circuit 9 has the motion vector information V generated by the motion compensation prediction difference processing circuit 2, the picture mode signal M from the picture mode setting circuit 17, and the quantization width information from the rate control circuit 12. Q, a slice synchronization signal S, etc. are supplied, and a frame synchronization code and encoded additional information are output for each head of a frame, and a slice synchronization code and additional information are output for each head of a slice.
Here, the additional information for each head of the frame is information indicating whether it is an intra frame or non-intra frame by the picture mode signal M, and the additional information for each head of the slice is a quantization width. The information Q is the motion vector information V used for the motion compensation of the prediction.

DCT coefficients coded by the DC coefficient coding circuit 5 and the AC coefficient coding circuit 6, and the additional information coding circuit 9
Is supplied to the multiplexing circuit 8 to be multiplexed, and a slice synchronization code and additional information are added to the head of each slice, and a frame synchronization code and additional information are added to the head of each frame. In this way, the inter-frame predictive-coded moving image data obtained from the multiplexing circuit 8 is temporarily stored in the buffer 10 and output from the output terminal 11 at a desired transmission rate.

The rate control circuit 12 monitors the data amount in the buffer 10, that is, the residual data amount which is the difference between the write data amount and the read data amount, and the quantization width information Q corresponding to this residual data amount is monitored. It is generated and supplied to the DCT transform quantization circuit 4. In the DCT transform quantization circuit 4, the quantization width according to the quantization width information Q is set, whereby the data amount of the moving image data supplied to the buffer 10 becomes a constant rate. The rate control circuit 12 monitors the amount of residual data in the buffer 10 by the slice synchronization signal S from the slice synchronization signal generation circuit 16 in units of slices. Therefore, in the DCT transform quantization circuit 4,
The quantization width is set for each slice.

As described above, in this embodiment, the slice size of the intra frame is smaller than the slice size of the non-intra frame by making the periods of the slice synchronization signals different between the intra frame and the non-intra frame. . Therefore, even if such an intra frame is encoded, the amount of data in the slice does not increase. Since the amount of data after encoding the intra frame is 2 to 5 times the amount of data after encoding the non-intra frame, in this embodiment, the slice size of the intra frame before encoding is set to the slice size of the non-intra frame. By setting ½ to ⅕ times, the slice size of the intra frame can be made approximately the same as the slice size of the non-intra frame after encoding.

FIG. 2 shows that the slice size of an intra-frame before encoding is 1 of the slice size of a non-intra frame.
FIG. 3 is a diagram showing division by slice of an intra frame and a non-intra frame when the number is / 3, and FIG.
Shows an intra-frame, and FIG. 7B shows a non-intra-frame.

In this case, the luminance signal is 72 pixels wide in each frame.
0 × vertical 480 pixels, the color difference signal is horizontal 360 × vertical 240 pixels, and the macroblock is 16 × 16 pixels (= 2 ×
2DCT blocks), one frame is horizontal 45
X Vertical 30 macroblocks. Therefore, in a non-intra frame, 45 macroblocks constitute one slice as shown in FIG. 2b). In an intraframe, 15 macroblocks constitute one slice as shown in FIG. 2a). become.

FIG. 3 is a diagram showing the structure of a data stream after the frame shown in FIG. 2 is encoded. In FIG. 3, a) shows an intraframe data stream, and FIG. 3b shows a non-intraframe data stream. Each stream is shown.

When a slice is set in each frame as shown in FIG. 2, 1 is set in each slice of the intra frame.
The data for 5 macroblocks is included, and the data for 45 macroblocks is included in each slice of the non-intra frame. Since the amount is 2 to 5 times the amount, the amount of data per slice of the intra frame and the non-intra frame after being encoded is substantially equal.

FIG. 4 is a side information encoding circuit 9 in FIG.
2 is a block diagram showing a specific example of a DC coefficient encoding circuit 5, in which 18 is a picture header generation circuit, 19 is a slice header generation circuit, 20 is a macroblock address generation circuit, 21 is an address difference circuit, and 22 is a switch. ,
23 is an address variable length coding circuit, 24 is a vector difference circuit, 25 is a switch, 26 is a vector variable length coding circuit, 27 is a DC coefficient difference circuit, 28 is a switch, and 29 is a DC coefficient variable length coding circuit. The same reference numerals are given to the portions corresponding to those in FIG. 1, and duplicate description will be omitted.

In the figure, the picture mode setting circuit 1
The picture mode signal M from 7 is supplied to the picture header generation circuit 18, and a picture header added to each frame such as a frame synchronization code indicating the beginning of the frame and picture mode information indicating whether the frame is an intra frame or a non-intra frame. Is generated. This picture header is supplied to the multiplexing circuit 8. In addition, the quantization width information Q from the rate control circuit 12 is the slice header generation circuit 1
9, a slice header added to each slice such as a slice synchronization code indicating the beginning of the slice and quantization width information Q is generated. This slice header is supplied to the multiplexing circuit 8.

On the other hand, the macroblock address generation circuit 2
From 0, a macroblock address indicating the position of the currently encoded macroblock on the screen is generated. When the slice synchronization signal S is supplied from the slice synchronization signal generation circuit 16 at the head of the slice, the switch 22 is closed in the direction shown in the figure, and the macroblock address output from the macroblock address generation circuit 20 is directly transmitted via the switch 22. It is supplied to the address variable length encoding circuit 23. At other times, the switch 22 is closed on the side opposite to that shown. As a result, the macro block address output from the macro block address generation circuit 20 is supplied to the address difference circuit 21, and the difference macro block address obtained by taking the difference from the previous macro block address is the switch 22. Is supplied to the address variable-length coding circuit 23 via. The address variable length coding circuit 23 performs variable length coding on the supplied macroblock address or differential macroblock address and supplies it to the multiplexing circuit 8.

On the other hand, the motion vector information V from the motion compensation prediction difference processing circuit 2 is directly supplied to the switch 25 on the one hand, and is supplied to the vector difference circuit 24 on the other hand to be the previous motion vector information V. Difference is taken. The difference motion vector information obtained by this is the switch 25.
Is supplied to. The switch 25 is closed in the direction shown in the drawing when the slice synchronization signal S is supplied from the slice synchronization signal generation circuit 16 at the beginning of the slice, and the motion vector information V from the motion compensation prediction difference processing circuit 2 is subjected to vector variable length coding. Supply to the circuit 26. Otherwise,
The switch 25 is closed in the opposite direction to that shown in the figure, and the differential motion vector information from the vector differential circuit 24 is supplied to the vector variable length coding circuit 26. The vector variable length coding circuit 26 variable length codes the supplied motion vector information V or differential motion vector information, and supplies it to the multiplexing circuit 8.

Further, D from the DCT transform quantization circuit 4
On the one hand, the C coefficient is directly supplied to the switch 28, and on the other hand, it is supplied to the DC coefficient difference circuit 27 so that the previous D coefficient is supplied.
The difference from the C coefficient is taken. Difference D obtained by this
The C coefficient is supplied to the switch 28. Switch 28
When the slice synchronization signal S is supplied from the slice synchronization signal generation circuit 16 at the head of the slice, the slice synchronization signal S is closed in the direction shown in the drawing, and the DC coefficient from the DCT transform quantization circuit 4 is set to DC.
The coefficient variable length encoding circuit 29 is supplied. At other times, the switch 28 is closed in the opposite direction to that shown, and the differential DC coefficient from the DC coefficient difference circuit 27 is supplied to the DC coefficient variable length encoding circuit 29. DC coefficient variable length coding circuit 2
9 is a variable length coded DC coefficient or differential DC coefficient,
It is supplied to the multiplexing circuit 8.

In this way, since the macroblock address, the motion vector information V, and the DC coefficient are also transmitted as the difference data, the data amount can be reduced, but
Further, the switches 22, 25, and 28, which are switch-controlled by the slice synchronization signal S, reset the difference processing in the macroblock at the head of the slice. Therefore, the propagation range of the error in the macroblock address, the motion vector information V, and the DC coefficient is also limited within the slice.

As described above, in this embodiment, by reducing the slice size in the intra frame,
The error propagation range in the intra frame is narrowed, and deterioration of the image quality of the intra frame, which is important for moving image reproduction, can be reduced.

When this embodiment is applied to a recording device such as a VTR, it is possible to form a sync block so as to include one or two slices, thus improving the utilization rate of the reproduction data during high speed reproduction. Therefore, the image quality can be improved.

FIG. 5 is a block diagram showing another embodiment of the moving picture compression coding apparatus according to the present invention, in which 49 is a slice code amount detection circuit and 50 is a slice size variable circuit, which corresponds to FIG. The same reference numerals are given to the parts, and the duplicated description will be omitted.

In this embodiment, the data amount of slices is made more constant.

In the figure, the slice size variable circuit 5
0 corresponds to a portion including the small slice size setting circuit 13, the large slice size setting circuit 14 and the switch 15 in FIG. 1, but the cycle of the slice synchronization signal S generated from the slice synchronization signal generation circuit 16 is continuously changed. Or, it can be changed in multiple stages. The slice code amount detection circuit 49 detects the data amount of each slice encoded from the output signal of the multiplexing circuit 8.
The slice size variable circuit 50 is controlled by this detection output.

In such a configuration, the slice code amount detection circuit 49 detects the data amount of each slice after being encoded, and controls the slice size variable circuit 50 so that this amount becomes a constant amount. Change the slice size of intraframes and non-intraframes. In this case, the slice size of the intra frame before encoding is naturally smaller than the slice size of the non-intra frame.

As described above, in this embodiment, since the data amount of the slice after encoding can be made substantially constant, when this is applied to the recording device such as the VTR, the reproduction data of the high speed reproduction is The utilization rate can be improved and the image quality can be improved.

FIG. 6 is a block diagram showing an embodiment of a compressed moving image recording apparatus according to the present invention, in which 30 is an antenna,
Reference numeral 31 is an RF demodulation circuit, 32 is a header addition difference data replacement circuit, 33 is a switch, 34 is a macroblock counter, 35 is a small size slice synchronization signal generation circuit, 36 is a picture mode detection circuit, 37 is a recording synchronization block formation circuit, 38 is a recording head.

In the figure, the inter-frame predictive coded digital television broadcast signal is received from the antenna 30 and RF demodulated by the RF demodulation circuit 31. In this digital television broadcast signal, the slice size of the intra-frame before encoding and the slice size of the non-intra-frame are equal. Therefore, the slice size of the intra frame in the received digital television broadcast signal is larger than the slice size of the non-intra frame. The demodulated moving image data is supplied to the picture mode detection circuit 36, the picture mode information is detected from the header of each frame, and it is judged whether the current frame is an intra frame or a non-intra frame and the judgment result is shown. The picture mode signal M is output.

When the current received frame is an intra frame, the switch 33 is closed to the I side terminal by the picture mode signal M, and the moving image data of the intra frame output from the RF demodulation circuit 31 is replaced with the header addition difference data. It is supplied to the recording synchronization block forming circuit 37 via the circuit 32 and the switch 33. If the current received frame is a non-intra frame, the switch 33 is closed to the NI side terminal by the picture mode signal M, and R
The non-intra-frame moving image data output from the F demodulation circuit 31 is supplied to the recording synchronization block forming circuit 37 via the switch 33.

The recording synchronization block forming circuit 37 converts the supplied moving image data into a data stream divided into recording synchronization blocks to which a synchronization code, an ID code, and an error correction parity code are added. This data stream is supplied to the head 38 and recorded on a recording medium (not shown).

On the other hand, the output signal of the RF demodulation circuit 31 is also supplied to the macroblock counter 34, and the macroblock is counted. In response to this count value, the small-size slice synchronization signal generation circuit 35 generates a slice synchronization signal S having a cycle similar to the slice synchronization signal of the non-intra frame, and in synchronization with this slice synchronization signal S, header addition differential data replacement The circuit 32 adds a new header to the intra frame from the RF demodulation circuit 31, and further, in the data stream of the supplied intra frame, the difference of the macroblock address and the DC coefficient at the head of the new slice by the slice synchronization signal S. Convert to a data stream that resets the process. As a result, the slice sizes of the intra frame and the non-intra frame become substantially equal.

FIG. 7 is a block diagram showing a specific example of the header addition difference data replacement circuit 32 in FIG. 6, 39 is a data replacement circuit, 40 is a quantization width information extraction circuit, and 41 is a slice header generation circuit. , 42 is an address variable length decoding circuit, 43 is an address inverse difference circuit, 44 is an address variable length encoding circuit, 45 is a DC coefficient variable length decoding circuit, 46
Is a DC coefficient inverse difference circuit, and 47 is a DC coefficient variable length encoding circuit. The same reference numerals are given to the portions corresponding to those in FIG.

In the figure, each frame output from the RF demodulation circuit 31 is supplied to the quantization width information extraction circuit 40, and the quantization width information Q is extracted from each slice. This quantization width information Q is supplied to the slice header generation circuit,
A new slice header is created.

Further, the address variable length decoding circuit 42 uses R
The variable length coded macroblock address information added to each macroblock of each frame output from the F demodulation circuit 31 is decoded. Since this macroblock address information has been subjected to the difference processing, it is returned to the information of the original value by the address reverse difference circuit 43, and variable-length coded by the address variable-length coding circuit 44.

As for the DC coefficient of each frame output from the RF demodulation circuit 31, the variable length coded DC of the first DCT block in the new slice determined by the slice synchronization signal S of the luminance signal or the color difference signal is also used. Coefficient is DC
The coefficient variable length decoding circuit 45 decodes it, and the DC coefficient inverse difference circuit 46 converts it into the DC coefficient of the original value.
The variable-length coding circuit 47 performs variable-length coding to obtain a variable-length code that does not take a difference.

The slice header output from the slice header generation circuit 41, the Marok block address information that does not take the difference output from the address variable length encoding circuit 44, and the difference output from the DC coefficient variable length encoding circuit 47 The DC coefficient that is not taken is supplied to the data replacement circuit 39 together with the intraframe data stream from the RF demodulation circuit 31. In this data replacement circuit 39, this slice header is added to this data stream in synchronization with the slice synchronization signal S from the small size slice synchronization signal generation circuit 35, and the differential block of the difference in this data stream is blocked. The address information and the DC coefficient are replaced with the new Maroc block address information and the DC coefficient which do not take the difference.

FIG. 8 is a diagram showing the structure of a synchronization block formed by the recording synchronization block forming circuit 37 in FIG.

In the figure, the central area of the figure is a data stream, and an outer correction code is added to a vertical data series and an inner correction code is added to a horizontal data series. One row of data forms one synchronization block, and a synchronization code and an ID code are added to this to be recorded in order.

In this embodiment, the slice size of the intra frame is set to 1 of the slice size of the non-intra frame.
Since the data amount of the slices can be made substantially equal by converting to / 2 to ⅕ times, as shown in the figure, most of the synchronization blocks can be configured to include one to two slices.

By the way, in general, when the data recorded in this way is reproduced at high speed, reproduced data can be obtained discretely in sync block units. Therefore, if the sync block includes one or two slices, at least one slice can be decoded from most of the played sync blocks, so that the playback data at the time of high-speed playback can be efficiently used. You can

According to this embodiment, even when a data stream encoded in advance with a large slice size is recorded, the data of an intra frame is converted into data of a small slice size and recorded, so that the image quality is deteriorated due to an error. Can be made smaller. Further, since the synchronous block for recording can include one or two slice data, it is possible to efficiently use the reproduction data at the time of high-speed reproduction and improve the high-speed reproduction image quality.

[0060]

As described above, according to the moving picture compression coding apparatus of the present invention, it is possible to reduce the image quality deterioration due to the error by reducing the slice size of the intra frame. Further, particularly, by setting the slice size of the intra frame to be 1/2 to 1/5 times the slice size of the non-intra frame, the utilization rate of the reproduction data at the time of high speed reproduction is improved and the high speed reproduction image quality is improved. Can be improved. Alternatively, the same effect can be obtained by controlling the slice size so that the data amount of the slice after encoding is almost constant.

Further, according to the compressed moving image recording apparatus of the present invention, even when the already encoded data is recorded,
The same effect can be obtained by converting the data stream so that the slice size of the intra frame becomes smaller.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a moving image compression encoding apparatus according to the present invention.

FIG. 2 is a diagram showing a comparison between slices of an intra-frame coded frame and an inter-frame predictive coded frame in the embodiment shown in FIG.

FIG. 3 is a diagram showing a structure of a data stream of an intra-frame coded frame and an inter-frame predictive coded frame in the embodiment shown in FIG.

4 is a block diagram showing a specific example of an additional information encoding circuit and a DC coefficient encoding circuit in FIG.

FIG. 5 is a block diagram showing another embodiment of the moving picture compression encoding apparatus according to the present invention.

FIG. 6 is a block diagram showing an embodiment of a compressed moving image recording apparatus according to the present invention.

7 is a block diagram showing a specific example of a header addition difference data replacement circuit in FIG.

8 is a diagram showing the structure of a recording synchronization block in the embodiment shown in FIG.

[Explanation of symbols]

 1 Image Data Input Terminal 2 Motion Compensation Prediction Difference Processing Circuit 3 Switch 4 DCT Transform Quantization Circuit 5 DC Coefficient Coding Circuit 6 AC Coefficient Coding Circuit 7 Inverse Quantization Inverse DCT Conversion Circuit 8 Multiplexing Circuit 9 Additional Information Coding Circuit Reference Signs List 10 buffer 11 output terminal for encoded data 12 rate control circuit 13 small slice size setting circuit 14 large slice size setting circuit 15 switch 16 slice synchronization signal generating circuit 17 picture mode setting circuit 18 picture header generating circuit 19 slice header generating circuit 30 antenna 31 RF demodulation circuit 32 Header addition difference data replacement circuit 33 Switch 34 Macro block counter 35 Small size slice sync signal generation circuit 36 Picture mode detection circuit 37 Recording sync block forming circuit 38 Head 48 Recording sync block 49 Slice code amount detection circuit 50 Slice size variable circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 7/137 Z (72) Inventor Nobuyoshi Tsukiji 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock ceremony Inside Hitachi Media Media Research Laboratories

Claims (4)

[Claims] 1. When compressing the moving image data by performing predictive coding between frames or intraframe coding of successive frames of input moving image data, each frame is divided into a plurality of partial images. However, in the moving picture compression coding apparatus that independently codes each partial image, a unit that makes the size of the partial image different between the frame for intra-frame coding and the frame for inter-frame predictive coding is provided. A moving picture compression coding apparatus, wherein the size of the partial image of the frame to be intra-coded is smaller than the size of the partial image of the frame to be inter-frame predictive coded. 2. The size according to claim 1, wherein the size of the partial image of the frame to be intra-coded is set to 1/2 to 1/5 of the size of the partial image of the frame to be inter-frame predictive coded. Video compression encoding device. 3. When compressing and encoding the moving image data by performing interframe predictive coding or intraframe coding on successive frames of input moving image data, each frame is divided into a plurality of partial images. Then, in a moving image compression coding apparatus for independently coding each partial image, a partial image code amount detecting means for detecting a data amount for each encoded partial image, and a detection of the partial image code amount detecting means And a partial image size control means for setting the size of each partial image before being encoded so that the partial data amount of each encoded partial image partial data is substantially constant. A featured moving image compression encoding device. 4. Sequential frames are interframe predictive coded or intraframe coded, and such coding is performed by dividing the frame into a plurality of partial images and independently for each partial image. Thus, in the compressed moving image recording apparatus for recording the compressed and encoded moving image data on the recording medium, the compression-encoded moving image is compressed so that the size of the partial image of the intra-frame encoded frame becomes small. A compressed moving image recording apparatus comprising means for converting image data into moving image data for recording.