JPH07111587A - Image reader - Google Patents

Abstract

PURPOSE:To simplify the constitution of a device by performing image processing using correlation between plural continuous lines such as linear density conversion processing by analog processing. CONSTITUTION:Image data of one line read in by a line image sensor is preserved in buffer memory in unit of picture element. The image data accumulated in the buffer memory is converted to an analog image signal by a digital/analog converter 30. The analog image signal is added on an analog reading image signal outputted from the line image sensor at an addition circuit 31. An added analog reading image signal is converted to a digital signal by an analog/digital converter 29, then, it is outputted to the device at the next stage. Since the linear density conversion processing is performed in a state of analog data in such manner, a circuit scale can be compressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus for reading and inputting an image line by line using a line image sensor.

[0002]

2. Description of the Related Art For example, in a group 3 facsimile apparatus, an image reading apparatus (scanner) for reading and inputting an original image is read so as to be compatible with a plurality of read linear densities (eg, standard linear density and fine linear density). It is equipped with a function to perform line density conversion processing on an image line by line basis.

The linear density conversion processing is such that the image signal of two lines is converted into an image signal of one line after the original image is read and input at a fine linear density. Usually, the image signal obtained by reading is converted into digital data.

[0004]

However, when the linear density conversion processing is performed in the state of digital data in this way, there is a problem that the circuit content becomes large although the processing content is simple. Further, if this processing is executed by software, the burden on the control unit that executes the processing of the entire apparatus increases, and a situation occurs in which the required performance cannot be obtained.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an image reading apparatus which can realize image processing such as linear density conversion processing with a simple configuration.

[0006]

SUMMARY OF THE INVENTION The present invention relates to an image reading apparatus for reading and inputting an image on a line-by-line basis using a line image sensor, and a buffer memory for storing image data for one line on a pixel-by-pixel basis. A digital / analog converter that converts the image data read from the memory into a corresponding analog image signal, an analog image signal output from this digital / analog converter, and an analog read image signal output from the line image sensor, An adder circuit that adds for the same pixel position,
An analog / digital converter for converting the added analog image signal output from the adding circuit into a corresponding digital signal, and a storage unit for storing the digital signal output from the analog / digital converter in the buffer memory, The digital signal output from the analog / digital converter is output to the next-stage device as a read image signal.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an analog image signal output from the digital / analog converter, and an analog read image signal output from the line image sensor are added for the same pixel position. An addition circuit, a selection circuit that selects either the addition analog image signal output from this addition circuit or the analog read image signal output from the line image sensor, and the signal output from this selection circuit. Analog to convert to the corresponding digital signal /
The addition circuit includes a digital converter, and the addition circuit executes the addition operation in the first half of one pixel cycle, and the selection circuit selects the output signal of the addition circuit in the first half of the one pixel cycle and the second half of the one pixel cycle. To select the analog read image signal, output the digital signal output from the analog / digital converter as a read image signal to the next-stage device, and output from the analog / digital converter in the latter half of one pixel cycle. The digital signal is stored in the buffer memory.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units corresponds to image data read out from the buffer memory. A digital / analog converter for converting into an analog image signal, an analog image signal output from the digital / analog converter, and an analog read image signal output from the line image sensor are added for the same pixel position. An addition circuit, a selection circuit that selects either the addition analog image signal output from this addition circuit or the analog read image signal output from the line image sensor, and the signal output from this selection circuit. Analog to convert to the corresponding digital signal /
A digital converter is provided, and the addition circuit executes the addition operation in the first half of one pixel cycle, and the selection circuit selects the analog read image signal in the first half of the one pixel cycle and in the second half of the one pixel cycle. The output signal of the adder circuit is selected, the digital signal output from the analog / digital converter is output to the next-stage device as a read image signal, and output from the analog / digital converter in the first half of one pixel cycle. The digital signal is stored in the buffer memory.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. An adder circuit that adds the analog read image signals that are output for the same pixel position, an analog / digital converter that converts the added analog image signal that is output from the adder circuit to a corresponding digital signal, and the analog / digital converter The digital signal output from the digital converter is stored in the above buffer memory. It exists comprising a storage unit, an image reading apparatus and outputting to the next stage device as a read image signal to a digital signal output from the analog / digital converter.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. Either an adder circuit for adding the output analog read image signals for the same pixel position, the added analog image signal output from this adder circuit, or the analog read image signal output from the line image sensor. The selection circuit that selects one and the signal output from this selection circuit are paired. An analog / digital converter for converting the digital signal, the adding circuit performs the addition operation in the first half of one pixel period, the selection circuit,
The output signal of the adder circuit is selected in the first half of one pixel cycle, the analog read image signal is selected in the second half of the one pixel cycle, and the digital signal output from the analog / digital converter is used as the read image signal in the next stage. The digital signal output to the device and output from the analog / digital converter in the latter half of one pixel period is stored in the buffer memory.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read from this buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. Either an adder circuit for adding the output analog read image signals for the same pixel position, the added analog image signal output from this adder circuit, or the analog read image signal output from the line image sensor. The selection circuit that selects one and the signal output from this selection circuit are paired. An analog / digital converter for converting the digital signal, the adding circuit performs the addition operation in the first half of one pixel period, the selection circuit,
The analog read image signal is selected in the first half of one pixel cycle and the output signal of the addition circuit is selected in the second half of the one pixel cycle, and the digital signal output from the analog / digital converter is used as the read image signal in the next stage. The digital signal output to the device and output from the analog / digital converter in the first half of one pixel period is stored in the buffer memory.

Further, in an image reading apparatus for reading and inputting an image on a line-by-line basis using a line image sensor, a buffer memory for storing image data of one line on a pixel-by-pixel basis and image data read from the buffer memory A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, and an analog image signal output from the variable gain amplifying means. , An adder circuit for adding the analog read image signal output from the line image sensor for the same pixel position, and an analog / digital converter for converting the added analog image signal output from the adder circuit to a corresponding digital signal And the digital signal output from this analog / digital converter A storage means for storing in the buffer memory is provided, and the gain of the variable gain amplifier is updated line by line, and the digital signal output from the analog / digital converter is output to the next stage device as a read image signal. It was done.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, an analog image signal output from the amplifying means, and a line An adder circuit that adds the analog read image signal output from the image sensor for the same pixel position,
A selection circuit for selecting either the addition analog image signal output from the addition circuit or the analog read image signal output from the line image sensor, and a digital signal corresponding to the signal output from the selection circuit. The gain of the variable gain amplifier is updated on a line-by-line basis, the adding circuit executes the adding operation in the first half of one pixel period, and the selecting circuit outputs one pixel. The output signal of the adding circuit is selected in the first half of the cycle, and the analog read image signal is selected in the second half of the one-pixel cycle, and the digital signal output from the analog / digital converter is used as the read image signal in the next stage device. The digital signal that is output and output from the analog / digital converter in the latter half of one pixel period is stored in the buffer memory. One in which the.

Further, in an image reading apparatus for reading and inputting an image in line units using a line image sensor, a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, and an analog image signal output from the variable gain amplifying means. An adder circuit for adding the analog read image signals output from the line image sensor for the same pixel position, and the added analog image signal output from the adder circuit or the analog read image output from the line image sensor. The selection circuit that selects either one of the image signals An analog / digital converter that converts an output signal into a corresponding digital signal is provided, the gain of the variable gain amplifier is updated in units of lines, and the adder circuit performs the addition operation in the first half of one pixel period. The selection circuit selects the analog read image signal in the first half of one pixel cycle and the output signal of the addition circuit in the second half of the one pixel cycle, and selects the digital signal output from the analog / digital converter. The read image signal is output to the next stage device, and the digital signal output from the analog / digital converter in the first half of one pixel period is stored in the buffer memory.

[0015]

Therefore, since the image processing utilizing the correlation between a plurality of continuous lines such as the linear density conversion processing is realized by the analog processing, the device configuration of this portion can be simplified.

[0016]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a group 3 facsimile apparatus according to an embodiment of the present invention.

In FIG. 1, the control unit 1 performs control processing of each unit of the facsimile apparatus and facsimile transmission control procedure processing, and the system memory 2 is
The control unit 1 stores a control processing program executed by the control unit 1 and various data necessary for executing the processing program, and constitutes a work area of the control unit 1. The parameter memory 3 is a group memory. It is for storing various information unique to the facsimile machine.

The scanner 4 is for reading an original image at a predetermined resolution, the plotter 5 is for recording and outputting an image at a predetermined resolution, and the operation display unit 6 is a facsimile device. For operation,
It consists of various operation keys and various indicators.

The encoding / decoding unit 7 is for encoding and compressing the image signal and for decoding the encoded and compressed image information into the original image signal. The image storage device 8 is
This is for storing a large amount of image information in a coded and compressed state.

The group 3 facsimile modem 9 is for realizing the modem function of the group 3 facsimile, and is a low speed modem function (V.21 modem) for exchanging a transmission procedure signal and mainly exchanging image information. High-speed modem function (V.33 modem, V.33
29 modem, V.29. 27ter modem etc.).

The network control device 10 is for connecting the facsimile device to a public telephone line network, and has an automatic transmission / reception function.

These control unit 1, system memory 2,
The parameter memory 3, scanner 4, plotter 5, operation display unit 6, encoding / decoding unit 7, image storage device 8, group 3 facsimile modem 9, and network control device 10
It is connected to the system bus 11, and data is exchanged between these elements mainly in the system bus 1.
It is done through 1.

Data is exchanged directly between the network controller 10 and the group 3 facsimile modem 9.

FIG. 2 shows an example of the image reading processing system of the scanner 4.

In the figure, the read controller 21 is a CCD.
This is for controlling the (Charge Coupled Device) 22 to control the reading operation of the document image, and when a start signal ST for designating the start of operation is added from a higher-order control section (not shown), the timing generation section Clock MCK output from H.23 (Fig. 3 (a)
(See FIG. 3), a line synchronization signal LS for designating the start of the reading operation of one line, and a pixel clock ECK for designating the pixel transfer timing (see FIG. 3).
(See (b)) is output.

The line sync signal LS and the pixel clock ECK are supplied to the CCD 22, the timing generator 23,
In addition to being added to the address counter 24, it is output to an external device as a timing signal indicating the reading operation state of the scanner 4. Further, in this case, the pixel clock ECK is formed by dividing the clock MCK by four.

The timing generator 23 synchronizes with the line synchronization signal LS and the pixel clock ECK, and the timing signal TMs (see FIG. 3D), the read / write control signal RW (see FIG. 3F), and the enable signal. Signal EN (Fig. 3
(G)), selection signal SL (see FIG. 3 (j)), timing signal TMa (see FIG. 3 (l)), timing signal TMo (see FIG. 3 (n)), and timing signal T.
Md (see FIG. 3D) is output at a predetermined timing.

Here, the timing signal TMs and the timing signal TMd are signals that rise to the logical H level during the half cycle of the clock MCK at the start of the pixel clock ECK.

The read / write control signal RW holds the logic H level for three cycles of the clock MCK from the start timing of the pixel clock ECK, and the clock MC thereafter.
It is a signal that holds the logic L level for one cycle of K.

The enable signal EN is the pixel clock EC.
From the start timing of K to the two cycles of the clock MCK,
The logic H level is held, the logic L level is held for one cycle of the clock MCK thereafter, and the subsequent clock M
It is a signal that holds the logic H level for one cycle of CK.

The selection signal SL has a logic H level during two cycles of the clock MCK from the start timing of the pixel clock ECK.
It is a signal that holds the level and holds the logic L level for two subsequent cycles of the clock MCK.

The timing signal TMa is the pixel clock E.
It is a signal that rises to the logical H level for every ½ cycle of the pixel clock ECK from the time when ½ cycle of the clock MCK has passed from the start timing of CK, for every ½ cycle of the pixel clock ECK.

The timing signal TMo is the pixel clock E.
This signal is a signal that rises to the logical H level for a half cycle of the clock MCK when one cycle of the clock MCK has passed from the start timing of CK.

The timing signal TMs is sent to the sample / hold circuit 25, the read / write control signal RW is sent to the RAM (random access memory) 26 and the input / output circuit 27, and the enable signal EN is sent to the input / output circuit 27.
The selection signal SL is supplied to the selection circuit 28 and the timing signal T
Ma is added to the analog / digital converter 29, the timing signal TMo is added to the next stage device, and the timing signal TMd is added to the digital / analog converter 30.

The CCD 22 is for reading the original image line by line, and outputs its output analog image signal AV.
(See FIG. 3C) is added to the sample / hold circuit 25. The sample / hold circuit 25 samples the input analog image signal AV at the timing when the timing signal TMs is added,
The sample output is the sample analog image signal AVs.
As shown in FIG. 3E, it is added to one input terminal of the adder 31 and one selection input terminal of the selection circuit 28.

The address counter 24 has a pixel clock E.
It is for counting the address representing the pixel position of the analog image signal AV read from the CCD 22 in synchronization with CK, and the count value is an initial value (for example, 0) every time the line synchronization signal LS is applied. Initialized to. The count value of the address counter 24 is added to the RAM 26 as address data ADD.

The RAM 26 has a read / write control signal R.
When W is at the logical H level, the image data for one pixel stored in the storage area of the address corresponding to the address data ADD is read and output to the input / output circuit 27, and the read / write control signal RW is output. Is a logical L
When the level is set, the image data for one pixel added from the input / output circuit 27 at that time is stored in the storage area of the address corresponding to the address data ADD.

The input / output circuit 27 is a RAM when the read / write control signal RW is at the logical H level while the enable signal EN is at the logical H level.
The image data output from 26 is output to the digital / analog converter 30 as read image data DTr (see FIG. 3 (h)), and when the read / write control signal RW is at the logical L level, analog/
The digital image data DT (see FIG. 3 (m)) output from the digital converter 29 is output to the RAM 26 as write image data DTr (see FIG. 3 (o)).

The digital / analog converter 30 samples the read image data DTr that has been added at the rising timing of the timing signal TMd and converts the sample value into a corresponding analog signal.
The output is applied to the variable gain circuit 32 as the read analog image signal AVr.

The variable gain circuit 32 amplifies the input read analog image signal AVr with a gain corresponding to the gain data GG output from the upper control section, and its output is an analog image signal AVr '. , Is added to the other input terminal of the adder 31.

The adder 31 adds the sample analog image signal AVs applied to one input end and the analog image signal AVr 'applied to the other input end, and the addition result is Addition analog image signal AVc
As shown in FIG. 3 (i), it is added to the other selection input terminal of the selection circuit 28.

The selection circuit 28, when the selection signal SL is at the logical L level, adds the analog image signal AVc.
When the selection signal SL is at the logical H level, the sample analog image signal AVs is selected, and the selected output is added to the analog / digital converter 29 as the selected analog image signal AS. Has been.

With the above configuration, when the start signal ST is applied, the read controller 21 starts outputting the line synchronizing signal LS and the pixel clock ECK based on the clock MCK output from the timing generator 23.

As a result, the timing generating section 23 has the timing signals TMs, TMd, TM in the above-described manner.
o, TMa, read / write control signal RW, enable signal EN, and selection signal SL are output respectively.

As a result, for example, when the CCD 22 outputs the analog image signal AV at the address n, the analog image signal AV is sampled by the sample / hold circuit 25 at the timing immediately after the output, and accordingly, from that timing. During one period of the pixel clock ECK, the sample analog image signal AVs corresponding to the value of the analog image signal AV at the address n is applied to one input terminal of the adder 31 and one selection input terminal of the selection circuit 28. To be

On the other hand, the image data stored at the address n is output from the RAM 26 for three cycles of the clock MCK from the start of the pixel clock ECK, whereby the image clock 2 is supplied from the start of the pixel clock ECK to the clock MCK.
During the cycle, the read image data DTr corresponding to the address n is output from the input / output circuit 27.

This read image data DTr is sampled by the digital / analog converter 30 at the timing of the sampling signal TMd, whereby the read image data D of the address n is read from the digital / analog converter 30.
The read analog image signal AVr corresponding to Tr is output,
The read analog image signal AVr is amplified by the variable gain circuit 32 with a predetermined gain, and then the analog image signal AVr is obtained.
It is added to the other input terminal of the adder 31 as r '.

As a result, for the address n, the adder 31 outputs the sample analog image signal AVs corresponding to the analog image signal AV read and input by the CCD 22,
The analog image signal AVr ′ corresponding to the read image data DTr read from the RAM 26 is added.

Here, the selection circuit 28 uses the pixel clock E
During the first half of CK, the added analog image signal AVc output from the adder 31 is selected and output as the selected analog image signal AS to the analog / digital converter 29.

Further, the analog / digital converter 29 is
At the timing delayed by one cycle of the clock MCK from the start of the pixel clock ECK, 1/2 of the pixel clock ECK
The conversion operation of the input signal is executed every cycle.

Therefore, in the first half of the pixel clock ECK, the analog / digital converter 29 outputs the digital image data DT corresponding to the value of the added analog image signal AVc and the timing signal TMo. Therefore, in the next-stage device, the added analog image signal A
Digital image data DT corresponding to the value of Vc is input as the read image data at that time.

Further, the selection circuit 28 uses the pixel clock EC
During the latter half period of K, the sample analog image signal AVs is selected and used as the selected analog image signal AS.
Output to the digital converter 29.

Therefore, in the latter half of the pixel clock ECK, the value of the sample analog image signal AVs from the analog / digital converter 29, that is, the analog image signal AV read and input by the CCD 22 at that time.
The digital image data DT corresponding to the value of is output, and in this state, the read / write control signal RW becomes the logical L level.

As a result, at this time, the image data corresponding to the image signal at the address n of the newly read and input line is stored in the storage area of the RAM 26 at the address n. That is, the RAM 26 stores the image data corresponding to the image signal one line before the line currently read and input.
It will be stored sequentially.

In this way, the RAM 26 stores the image data corresponding to the image signal of the newly read and input line, and the image data of the previous line stored in the RAM 26 is predetermined. The image data obtained by adding the value multiplied by the gain and the value of the line currently being read and input in pixel units is output to the next-stage device as digital image data DT obtained by reading at that time. It

Therefore, when the line density in the sub-scanning direction of the image read and input by the CCD 22 is set to a fine line density of 7.7 (lines / millimeter), 3.85 (lines / line) are obtained by the above-mentioned digital image data DT. An image signal having a standard linear density of (mm) can be directly obtained.

The image signal of fine linear density is sample /
A sample analog image signal AVs output from the hold circuit 25 converted into a digital signal can be used. The processing system will be omitted.

In this way, in this embodiment, when the sub-scanning read line density is a fine line density, an image signal of standard line density can be obtained. Further, in the present embodiment, this linear density conversion processing is executed in the state of the analog image signal, so that the device configuration can be simplified.

FIG. 4 shows another example of the signal processing system of the scanner 4. In the figure, the same parts as those in FIG. 2 and corresponding parts are designated by the same reference numerals.

In the figure, the read controller 21 is a CCD
22 to control the reading operation of the original image, and when a start signal ST for designating the start of operation is applied from a higher-order control unit (not shown), the timing generation unit 23 outputs the start signal. Clock MCK (Fig. 5
(See (a)), a line synchronization signal LS for designating the start of the reading operation of one line, and a pixel clock ECK for designating the pixel transfer timing.
(See FIG. 5B) is output.

Here, the line synchronization signal LS and the pixel clock ECK are supplied to the CCD 22, the timing generator 23,
In addition to being added to the address counter 24, it is output to an external device as a timing signal indicating the reading operation state of the scanner 4. Further, in this case, the pixel clock ECK is formed by dividing the clock MCK by four.

The timing generator 23 synchronizes with the line synchronization signal LS and the pixel clock ECK, and the timing signal TMs (see FIG. 5D), the read / write control signal RW (see FIG. 5F), and the enable signal. Signal EN (Fig. 5
(See (g)), the timing signal TMa (see FIG. 5 (j)), the timing signal TMo (see FIG. 3 (l)), and the timing signal TMd (see FIG. 5 (d)) at predetermined timings. It is what is output.

Here, the timing signal TMs and the timing signal TMd are signals that rise to the logical H level during the half cycle of the clock MCK at the start of the pixel clock ECK.

The read / write control signal RW holds the logic H level for three cycles of the clock MCK from the start timing of the pixel clock ECK, and the clock MC thereafter.
It is a signal that holds the logic L level for one cycle of K.

The enable signal EN is the pixel clock EC.
From the start timing of K to the two cycles of the clock MCK,
The logic H level is held, the logic L level is held for one cycle of the clock MCK thereafter, and the subsequent clock M
It is a signal that holds the logic H level for one cycle of CK.

The timing signal TMa is the pixel clock E.
When 1/2 cycle of the clock MCK has elapsed from the start timing of CK, during the 1/2 cycle of the clock MCK,
This signal rises to the logical H level.

The timing signal TMo is the pixel clock E.
This signal is a signal that rises to the logical H level for a half cycle of the clock MCK when one cycle of the clock MCK has passed from the start timing of CK.

The timing signal TMs is applied to the sample / hold circuit 25, the read / write control signal RW is applied to the RAM (random access memory) 26 and the input / output circuit 27, and the enable signal EN is applied to the input / output circuit 27.
Further, the timing signal TMa is added to the analog / digital converter 29, the timing signal TMo is added to the next stage device, and the timing signal TMd is added to the digital / analog converter 30.

The CCD 22 is for reading the original image line by line, and outputs its output analog image signal AV.
(See FIG. 5C) is added to the sample / hold circuit 25. The sample / hold circuit 25 samples the input analog image signal AV at the timing when the timing signal TMs is added,
The sample output is the sample analog image signal AVs.
As shown in FIG. 5E, it is added to one input end of the adder 31.

The address counter 24 has a pixel clock E.
It is for counting the address representing the pixel position of the analog image signal AV read from the CCD 22 in synchronization with CK, and the count value is an initial value (for example, 0) every time the line synchronization signal LS is applied. Initialized to. The count value of the address counter 24 is added to the RAM 26 as address data ADD.

The RAM 26 has a read / write control signal R.
When W is at the logical H level, the image data for one pixel stored in the storage area of the address corresponding to the address data ADD is read and output to the input / output circuit 27, and the read / write control signal RW is output. Is a logical L
When the level is set, the image data for one pixel added from the input / output circuit 27 at that time is stored in the storage area of the address corresponding to the address data ADD.

The input / output circuit 27 has a RAM when the read / write control signal RW is at the logic H level while the enable signal EN is at the logic H level.
The image data output from 26 is output to the digital / analog converter 30 as the read image data DTr (see FIG. 5 (h)), and when the read / write control signal RW is at the logical L level, analog/
The digital image data DT (see FIG. 5 (k)) output from the digital converter 29 is output to the RAM 26 as write image data DTr (see FIG. 5 (m)).

The digital / analog converter 30 samples the read image data DTr added at the rising timing of the timing signal TMd, and converts the sampled value into a corresponding analog signal.
The output is applied to the variable gain circuit 32 as the read analog image signal AVr.

The variable gain circuit 32 amplifies the input read analog image signal AVr with a gain corresponding to the gain data GG output from the host controller, and its output is an analog image signal AVr '. , Is added to the other input terminal of the adder 31.

The adder 31 adds the sample analog image signal AVs applied to one input end and the analog image signal AVr 'applied to the other input end, and the addition result is Addition analog image signal AVc
It is added to the analog / digital converter 29 (see FIG. 5 (i)).

With the above configuration, when the start signal ST is applied, the read control unit 21 starts the output of the line synchronization signal LS and the pixel clock ECK based on the clock MCK output from the timing generation unit 23.

As a result, the timing generating section 23 is provided with the timing signals TMs, TMd, TM in the above-mentioned manner.
o, TMa, read / write control signal RW, and enable signal EN are output.

As a result, for example, when the CCD 22 outputs the analog image signal AV at the address n, the analog image signal AV is sampled by the sample / hold circuit 25 at the timing immediately after the output, and therefore from that timing. During one period of the pixel clock ECK, the sample analog image signal AVs corresponding to the value of the analog image signal AV at the address n is applied to one input terminal of the adder 31.

On the other hand, the image data stored at the address n is output from the RAM 26 during the three cycles of the clock MCK from the start of the pixel clock ECK, whereby 2 times of the clock MCK from the start of the pixel clock ECK.
During the cycle, the read image data DTr corresponding to the address n is output from the input / output circuit 27.

The read image data DTr is sampled by the digital / analog converter 30 at the timing of the sampling signal TMd, whereby the read image data D at the address n is read from the digital / analog converter 30.
The read analog image signal AVr corresponding to Tr is output,
The read analog image signal AVr is amplified by the variable gain circuit 32 with a predetermined gain, and then the analog image signal AVr is obtained.
It is added to the other input terminal of the adder 31 as r '.

As a result, for the address n, the adder 31 outputs the sample analog image signal AVs corresponding to the analog image signal AV read and input by the CCD 22,
The analog image signal AVr ′ corresponding to the read image data DTr read from the RAM 26 is added.

Further, the analog / digital converter 29 is
The conversion operation of the input signal is executed for each cycle of the pixel clock ECK at a timing delayed by one cycle of the clock MCK from the start of the pixel clock ECK.

Therefore, the analog / digital converter 2
The digital image data DT corresponding to the value of the added analog image signal AVc and the timing signal TMo are output from 9. Therefore, in the next-stage device, the digital image corresponding to the value of the added analog image signal AVc is output. The data DT is input as the read image data at that time.

At the same time, in the latter half of the pixel clock ECK, since the read / write control signal RW is at the logical L level, the image signal at the address n of the newly read and input line is stored in the storage area of the RAM 26 at the address n. Image data corresponding to a value obtained by adding a value obtained by multiplying the image data stored in the RAM 26 up to immediately before by a predetermined gain is stored.

In this manner, the RAM 26 stores the image data corresponding to the image signal of the newly read and input line and the added value of the values obtained by multiplying the previously stored image data by a predetermined value. It Therefore, in the present embodiment, the image processing operation utilizing the correlation of a plurality of lines can be easily realized by the configuration of FIG.

By appropriately changing the value of the gain data GG given to the variable gain circuit 32, the ratio of the correlation of the read value for each line to the calculated value can be set appropriately.

[0088]

As described above, according to the present invention,
Since the image processing utilizing the correlation between a plurality of continuous lines such as the linear density conversion processing is realized by the analog processing, there is an effect that the device configuration of this portion can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a group 3 facsimile apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an image reading processing system of a scanner.

3 is an operation waveform diagram for explaining the operation of the apparatus of FIG.

FIG. 4 is a block diagram showing another example of the image reading processing system of the scanner.

5 is an operation waveform chart for explaining the operation of the apparatus of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Control part 4 Scanner 21 Read-out control part 22 CCD (Charge Coupled Dev)
ice) 23 timing generator 24 address counter 25 sample / hold circuit 26 RAM (random access memory) 27 input / output circuit 28 selection circuit 29 analog / digital converter 30 digital / analog converter 31 adder 32 variable gain circuit

Claims (9)

[Claims] 1. An image reading apparatus for reading and inputting an image in line units by using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an analog image signal output from the digital / analog converter, and an analog read image signal output from the line image sensor are added for the same pixel position. An adder circuit, an analog / digital converter that converts the added analog image signal output from the adder circuit into a corresponding digital signal, and a save that saves the digital signal output from the analog / digital converter in the buffer memory Means for outputting from the analog / digital converter. An image reading apparatus which outputs a received digital signal as a read image signal to a next-stage apparatus. 2. An image reading apparatus for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an analog image signal output from the digital / analog converter, and an analog read image signal output from the line image sensor are added for the same pixel position. An addition circuit, a selection circuit for selecting either the addition analog image signal output from the addition circuit or the analog read image signal output from the line image sensor, and a signal output from the selection circuit. Equipped with an analog / digital converter that converts to a corresponding digital signal The addition circuit executes the addition operation in the first half of one pixel cycle, and the selection circuit selects the output signal of the addition circuit in the first half of the one pixel cycle and the analog read image signal in the second half of the one pixel cycle. Is selected, the digital signal output from the analog / digital converter is output as a read image signal to the next stage device, and the digital signal output from the analog / digital converter in the latter half of one pixel period is stored in the buffer memory. An image reading device characterized by being stored in. 3. An image reading device for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an analog image signal output from the digital / analog converter, and an analog read image signal output from the line image sensor are added for the same pixel position. An addition circuit, a selection circuit for selecting either the addition analog image signal output from the addition circuit or the analog read image signal output from the line image sensor, and a signal output from the selection circuit. Equipped with an analog / digital converter that converts to a corresponding digital signal The addition circuit executes the addition operation in the first half of the one pixel cycle, and the selection circuit selects the analog read image signal in the first half of the one pixel cycle and outputs the output signal of the addition circuit in the second half of the one pixel cycle. Is selected, the digital signal output from the analog / digital converter is output to the next-stage device as a read image signal, and the digital signal output from the analog / digital converter in the first half of one pixel cycle is stored in the buffer memory. An image reading device characterized by being stored in. 4. An image reading apparatus for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from this buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. The analog read image signal output is
An adder circuit for adding the same pixel position, an analog / digital converter for converting the added analog image signal output from this adder circuit to a corresponding digital signal, and a digital signal output from this analog / digital converter Is stored in the buffer memory, and the digital signal output from the analog / digital converter is output to the next-stage device as a read image signal. 5. An image reading device for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. The analog read image signal output is
An adder circuit for adding the same pixel position; and a select circuit for selecting either the added analog image signal output from the adder circuit or the analog read image signal output from the line image sensor, An analog / digital converter that converts a signal output from the selection circuit into a corresponding digital signal is provided, and the addition circuit performs the addition operation in the first half of one pixel period, and the selection circuit has one pixel period. The output signal of the adder circuit is selected in the first half, the analog read image signal is selected in the second half of one pixel period, and the digital signal output from the analog / digital converter is output to the next stage device as the read image signal. Saving the digital signal output from the analog / digital converter in the latter half of one pixel period in the buffer memory Image reading apparatus according to claim. 6. An image reading apparatus for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, an amplifying means for amplifying an output signal of the digital / analog converter with a predetermined gain, an analog image signal output from the amplifying means, and a line image sensor. The analog read image signal output is
An adder circuit for adding the same pixel position; and a select circuit for selecting either the added analog image signal output from the adder circuit or the analog read image signal output from the line image sensor, An analog / digital converter that converts a signal output from the selection circuit into a corresponding digital signal is provided, and the addition circuit performs the addition operation in the first half of one pixel period, and the selection circuit has one pixel period. The analog read image signal is selected in the first half and the output signal of the adder circuit is selected in the latter half of one pixel period, and the digital signal output from the analog / digital converter is output to the next stage device as the read image signal. Saving the digital signal output from the analog / digital converter in the first half of one pixel period in the buffer memory Image reading apparatus according to claim. 7. An image reading apparatus for reading and inputting an image line by line using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read out from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, and an analog image signal output from the variable gain amplifying means. , An adder circuit for adding the analog read image signal output from the line image sensor for the same pixel position, and an analog / digital converter for converting the added analog image signal output from the adder circuit into a corresponding digital signal And the digital signal output from this analog / digital converter A storage means for storing in the buffer memory is provided, and the gain of the variable gain amplifier is updated line by line, and the digital signal output from the analog / digital converter is output to the next stage device as a read image signal. Characteristic image reading device. 8. An image reading apparatus for reading and inputting an image line by line using a line image sensor, a buffer memory for storing image data for one line in pixel units, and image data read out from the buffer memory. A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, an analog image signal output from the amplifying means, and a line The analog read image signal output from the image sensor
An adder circuit for adding the same pixel position; and a select circuit for selecting either the added analog image signal output from the adder circuit or the analog read image signal output from the line image sensor, An analog / digital converter for converting the signal output from the selection circuit into a corresponding digital signal is provided, and the gain of the variable gain amplifier is updated line by line, and the addition circuit adds the gain in the first half of one pixel period. The selecting circuit executes the operation, selects the output signal of the adding circuit in the first half of one pixel cycle, selects the analog read image signal in the second half of the one pixel cycle, and outputs the analog read image signal from the analog / digital converter. The digital signal is output as a read image signal to the next stage device, and is output from the analog / digital converter in the latter half of one pixel cycle. An image reading apparatus characterized in that a digital signal to be stored is stored in the buffer memory. 9. An image reading apparatus for reading and inputting an image in line units using a line image sensor, wherein a buffer memory for storing image data for one line in pixel units and image data read from the buffer memory correspond to each other. A digital / analog converter for converting into an analog image signal, a variable gain amplifying means for amplifying an output signal of the digital / analog converter with a designated gain, and an analog image signal output from the variable gain amplifying means. , An addition circuit for adding the analog read image signal output from the line image sensor for the same pixel position, and the added analog image signal output from this adder circuit or the analog read image output from the line image sensor From the selection circuit that selects either one of the image signals, An analog / digital converter for converting an output signal into a corresponding digital signal is provided, the gain of the variable gain amplifier is updated in units of lines, and the adder circuit performs the addition operation in the first half of one pixel period. The selection circuit selects the analog read image signal in the first half of one pixel cycle, selects the output signal of the addition circuit in the second half of the one pixel cycle, and selects the digital signal output from the analog / digital converter. An image reading apparatus which outputs a read image signal to a next-stage device and stores a digital signal output from the analog / digital converter in the first half of one pixel period in the buffer memory.