JP3233430B2 - Video printer control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention fetches an input video signal as image data into an image memory, then reads out the image data from the memory and outputs it to a monitor, and also outputs it to a printing means for printing. The present invention relates to a control circuit of a video printer.

[0002]

2. Description of the Related Art Conventionally, as a video printer, a "thermal printer" as disclosed in Japanese Patent Application Laid-Open No. 58-138667 has been known. Such a conventional document describes a configuration in which the content to be printed is temporarily recorded as image data in an image memory, and is read out and passed to a thermal head side as a printing means. There is no description of a configuration for monitoring the image data, or a configuration for reading out image data from the image memory at a high speed at the time of monitoring and printing at a high speed by the printing means. In addition to reading the image data recorded in the image memory to the printer,
In order to enable reading and processing to a personal computer or the like as an external device, no configuration or the like to read to an external device is described.

[0003]

As a printer, a video printer capable of performing halftone recording using a thermal head is used. Even when printing is performed by such a printer, the image content to be printed (input video signal) is also required. ) Is read out to the monitor side and there is a demand to print while confirming the contents.

In this case, when the input video signal is taken into the image memory as image data, the input video signal is taken in synchronization with a horizontal synchronization signal separated from the video signal, and thereafter,
The image data is read out from the memory and output to the monitor side, and is also output in parallel to the printing means side for printing. At this time, even if the printing speed is increased, the reading speed to the monitor side is reduced. Restricted
There was a problem that reading could not be performed faster.

That is, reading is performed from the image memory one frame at a time at a constant speed and is displayed on an image display means (monitor) such as a CRT. If the reading is performed too fast, the image cannot be displayed on the CRT side. Limited by performance.

On the other hand, on the video printer side, one frame of horizontal (horizontal) scan in the horizontal direction which is read out to the monitor side,
Since the image data for one line in the vertical (vertical) direction is fetched and printed, printing (printing) for one screen is completed by multiplying the number of dots in one line in the horizontal (horizontal) direction. Scanning of the number of frames is required.

Conventionally, there was such a relationship between the reading speed on the monitor side and the printing speed, so that it was not possible to increase only the printing speed.
An object of the present invention is to provide a video printer control circuit capable of solving the problems of the prior art and enabling a printer to perform high-speed printing without being limited by a reading speed to a monitor. .

[0008]

In order to achieve the above object, according to the present invention, when an input video signal is taken into an image memory as image data, the input video signal is taken in synchronization with a horizontal synchronization signal separated from the video signal. After that, in the control circuit of the video printer which reads out the image data from the memory and outputs it to the monitor side, and also outputs to the printing means side and prints, a blanking generation circuit, a flag circuit, and a write operation for the buffer memory. And a read control circuit.

[0009]

The blanking generation circuit detects a horizontal retrace period from a horizontal synchronizing signal separated from an input video signal to be printed, and outputs a signal representing the period as a blanking signal. The flag circuit waits for a blanking signal from the blanking generation circuit when a print enable signal is received from the printing means, and outputs a signal indicating a horizontal blanking period represented by the signal as a flag.

When a flag signal from the flag circuit is input to the write / read control circuit for the buffer memory, independently of reading image data to the monitor side,
The image data to be sent to the printing means for printing is read from the image memory at a high speed and written into the buffer memory, and then read from the buffer memory and transferred to the printing means.

As described above, by utilizing the horizontal retrace period of the video signal to be printed, during this period, the printer performs high-speed reading for printing independently of image memory reading for the monitor, thereby allowing the printer to operate. It is possible to print at high speed.

[0012]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a decoder circuit for extracting a video signal portion from an input video signal, 2 denotes an A / D converter for analog-to-digital conversion of the video signal extracted by the decoder circuit 1, and 3 denotes an AD-converted video signal. An image memory for recording one frame or one field of a signal.

Reference numeral 4 denotes a D / A converter which converts one frame or one field of image data read from the image memory 3 from digital to analog and reproduces it as a video signal before recording. A synchronization separation circuit that separates a signal and provides the timing signal to the memory control circuit 6, and a memory control circuit 6 that drives the image memory 3. In the memory control circuit 6, reference numeral 20 denotes a memory control unit (1), reference numeral 21 denotes a horizontal blanking generation circuit, and reference numeral 22 denotes an access flag circuit.

Reference numeral 7 denotes a clock generation circuit that generates and outputs a sampling clock to be supplied to the A / D converter 2 from a synchronizing signal, 8 denotes a line memory for storing data of one line to be printed, and 9 denotes a line memory. And a halftone control circuit that reads out the converted data into a signal for driving the thermal head 10.

Reference numeral 10 denotes a thermal head for converting a converted drive signal (a signal representing image data to be printed) into heat and transferring it to ink paper (not shown). Reference numeral 11 denotes a system control for controlling the operation of the entire printer. A microcomputer (hereinafter abbreviated as syscon), 12 is a mechanism for transporting recording paper and ink paper of the printer, and 13 is a memory control unit (2) for controlling writing and reading of the line memory 8.

Next, the circuit operation will be described with reference to FIG.
The input video signal is input to the decoder circuit 1 and the sync separation circuit 5. The decoder circuit 1 separates a video signal portion recorded in the video signal. If the video signal portion is a color image, a RGB (red, green, blue) color image signal is output. Take out.

On the other hand, the synchronization separation circuit 5 separates the synchronization signal recorded in the video signal, and
It is supplied to the clock generation circuit 7. The clock generation circuit 7 generates a sampling clock of the image signal by using the synchronization signal provided from the synchronization separation circuit 5 as a reset signal. The clock signal generated here is supplied to the A / D converter 2
Is supplied to the memory control circuit 6.

The image data converted into a digital signal by the A / D converter 2 is input to an image memory 3. The memory control circuit 6 determines the writing and reading operations of the image memory 3. The memory control circuit 6 includes a memory control unit (1) 20 for controlling the operation of the image memory 3, a horizontal blanking generation circuit 21, and an access flag circuit 2
As mentioned earlier, it is composed of 2.

The memory control unit (1) 20 controls the image memory 3 based on inputs from both the synchronization separation circuit 5 and the clock generation circuit 7. Specifically, when writing and storing the image data in the image memory 3, the writing terminal of the image memory 3 is set to the writing mode by a control signal from the memory control unit (1) 20, and the memory control unit (1) is set. 2) According to the address designation from 20, the A / D-converted data is written into the image memory 3 in accordance with the conversion speed of the A2 / D converter 2.

On the other hand, at the time of reproduction, the read terminal of the image memory 3 is set to the read mode by a control signal from the memory control unit (1) 20, and the internal (storage data) of the image memory 3 is stored in the same address order as that at the time of writing. That is, the same signal as that at the time of reading and recording is reproduced. Image memory 3
The digital signal read from the D / A converter 4
Then, the conversion reverse to that of the A / D converter 2 is performed, and is output as an analog signal.

On the other hand, the horizontal blanking generation circuit 21 and the access flag circuit 22 in the memory control circuit 6 control the operation of the line memory 8 via the memory control section (2) 13. In the image memory 3, reading control to the D / A converter 4 is normally performed. In the present embodiment, printing performed by the thermal head 10 via the halftone control circuit 9 is performed asynchronously with the image signal read from the image memory 3, so that the line memory 8 is accessed from the image memory 3. The timing does not coincide with the reading of the image signal.

Therefore, in this embodiment, the circuit operation performed by combining the access flag circuit 22 and the horizontal blanking generation circuit 21 causes the D / A converter to be transferred from the image memory 3 during the horizontal retrace period or the vertical retrace period. Independently of reading out the monitor image signal input to the monitor 4, the image data of one vertical line or n lines (n is plural) of the image to be printed is read and transferred to the line memory 8 for writing.

FIG. 2 shows this state at the timing of each part signal. In FIG. 2, reference numeral 30 denotes a head energizing pulse for controlling the energization of the thermal head 10, in a low section during one line printing period, energization (printing) of density gradation 0, energization of density gradation 1, and density gradation. 2 indicates that energization of density gradation 3 is performed. Numeral 31 denotes energization data for turning on / off each dot of the thermal head 10. Such energization data, that is, energization data corresponding to the density gradation 0 to energization data 3 is
This indicates that the transfer is performed at a timing prior to each of the 30 density gradation 0 sections to the density gradation 3 sections.

Reference numeral 32 denotes a head transfer clock for transferring the energization data to the thermal head. Numeral 33 indicates the horizontal synchronizing signal of the input video signal (and, consequently, the horizontal retrace interval) in the low section, which does not coincide with the energization cycle (the reason for the non-coincidence has already been described). Numeral 34 denotes a write signal to the line memory 8. The write signal 34 includes the first 33 low sections (horizontal blanking section) after the last high section in one line printing period of the head energizing pulse 30 starts. At the coincident timing, the memory control unit (2)
It can be seen that the data is output from C.13.

Reference numeral 35 denotes a read signal from the line memory 8, reference numeral 36 denotes a gradation counter for performing gradation control in the halftone control circuit 9, and reference numeral 37 denotes energization control for one line of image data to be printed. This is a read request signal requesting from the system controller 11 to end reading in the halftone control circuit 9 and to read image data of the next line.

When the energization control for one line of image data to be printed is completed, the halftone control circuit 9
1 is returned to the power-supply end signal. Upon receiving the power supply end signal from the halftone control circuit 9, the system controller 11 sends a read request signal 37 for the next line to the access flag circuit 22 in the memory control circuit 6.

Upon receiving this read request signal, the access flag circuit 22 sets that a read request has been made, and waits until a horizontal synchronization signal is detected from the synchronization separation circuit 5 and arrives. When the horizontal synchronizing signal arrives, first, in the memory control unit (1) 20, during the horizontal retrace period in which the monitor image is not read from the image memory 3,
The image data for printing to be transferred to the line memory 8 is read from the image memory 3.

At the same time, the horizontal blanking generation circuit 2
In step 1, a horizontal retrace period during which no monitor image is read from the image memory 3 is detected from the incoming horizontal synchronizing signal, and a signal indicating this is supplied to the access flag circuit 22. In the access flag circuit 22, during the first horizontal retrace period after receiving the read request signal from the system controller 11, the memory control unit (2) 13 reads the image data from the image memory 3 to the line memory 8. The transferred image data for one line to be printed is written into the line memory 8.

It will be apparent that the timing of this writing is indicated at 34 in FIG. Here, in one horizontal retrace period, one line of image data to be printed is read out from the image memory 3 and read out from the line memory 8.
However, when the required time is insufficient, the image data for one line to be printed is transferred to the image in two horizontal blanking periods or n horizontal blanking periods (n is more than 2). The data may be read from the memory 3 and transferred to the line memory 7.

The image data transferred from the image memory 3 to the halftone control circuit 9 via the line memory 8 in the halftone control circuit 9 is used as a drive signal for the thermal head 10 in the following manner. That is, the thermal head 10 is driven.

That is, when receiving a command to print one line of image data from the system controller 11, the halftone control circuit 9
The gradation counter therein is sequentially counted up from 0 to m. At this time, one line of image data is read from the line memory 8 each time, and the size of the image data is compared with the gradation counter. The image data compared here is transferred to the thermal head 10 as head energizing data 31 as a transfer clock 32.
Is transferred in synchronization with The thermal head 10 prints by applying power to the head 10 for each gradation based on the transferred image data to obtain a heat generation amount proportional to the power-on time.

When the energization is completed to m gradations (0 to 3 gradations in the figure), the halftone control circuit 9 outputs an energization end signal to the system controller 11 to complete the printing of one line. Let them know. The system controller 11 drives the mechanism 12 based on the print completion notification signal, feeds the recording paper for one line, reads the next line data from the image memory 3 and transfers the data to the line memory 8. Get ready.

FIG. 3 is a block diagram showing a modification of the memory control circuit 6 in FIG. In FIG. 3, FIG.
The same reference numerals are given to the same and corresponding parts as in FIG. In FIG. 3, 40 is a line memory built in the memory control circuit 6, 41 is a selector for selecting and outputting a write address and selecting a read address, 42 is a write counter for generating a write address, and 43 is a read for generating a read address. A counter 44, an access completion flag circuit indicating whether or not the access has been completed;
An access request flag circuit 45 stores an access request.

FIG. 4 is a timing chart showing the circuit operation of FIG. In FIG. 4, reference numeral 50 denotes a head energizing pulse for controlling energization of the thermal head, 51 denotes energizing data for turning on / off each dot of the thermal head, and 52 denotes a head transfer clock for transferring the energizing data.

Numeral 53 indicates the horizontal synchronizing signal of the video signal in the low section (and, consequently, the horizontal retrace period), which does not coincide with the energizing cycle. 54 is a write signal to the line memory 40, 55 is a read signal from the line memory 40, and 56 is an output of the access request flag circuit 45.

In the present embodiment shown in FIG.
By taking 0 into the memory control circuit 6, the circuit configuration is simplified. When a line memory write request from the system controller 11 is input to the access request flag circuit 45, the selector circuit 41 is first switched to select the write counter 42 that generates the write address.

When the synchronization separation signal from the synchronization separation circuit 5 is input to the access completion flag circuit 44, the access completion flag circuit 44 sends a clock to the write counter 42 to generate a write address, and The read data is written to the line memory 3. When the writing is completed, the access request flag circuit 45 receiving the notification from the access completion flag circuit 44 cancels the flag setting, switches the selector 41 to the read counter 43 side, and outputs the signal from the halftone control circuit 9. Prepare for reading.

Thus, in response to the access request from the access request flag circuit 45, the memory control circuit 6 uses the selector 41 to switch between the write address and the read address, and switches from the image memory 3 to the line memory 40. , And read from the line memory 40 to transfer image data to the halftone control circuit.

FIG. 5 is a block diagram showing another embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 3 and the corresponding components are denoted by the same reference numerals. In addition, reference numeral 60 denotes a buffer memory, which is used to buffer temporary data when writing image data from an external device (not shown) (for example, a personal computer) to the image memory 3 or when reading image data from the image memory 3 to the external device. It is.

Reference numeral 61 denotes an interface control circuit, which is a terminal for connection to the outside (for example, a printer control terminal of a personal computer, a parallel interface, or a digital interface such as RS232C). In the present embodiment, the case of the parallel interface has been described. Further, in this embodiment, the configuration in which the image data is read from the image memory 3 and output to the external terminal has been described.

There is a need to take out the contents of the image memory 3 to an external personal computer or the like, process it there, and then return it to the image memory 3 for printing. This embodiment is an embodiment for meeting such needs. It is.

In FIG. 5, an interface control circuit 61 transmits a strobe (STROBE) signal serving as a data transfer clock and data transfer in order to exchange data with an external device (not shown). A busy (BUSY) signal for controlling whether to perform or not is transmitted and received.

On the other hand, in response to an access request from an external device, the image memory 3 normally operates at a separate video timing. Therefore, what performs this timing adjustment is the buffer memory 60 and the interface control unit 61.
It is. When the control input BUSY signal from the external device goes low to request data transfer, the interface control unit 61 sets the flag of the access request flag circuit 45.

The access request flag circuit 45 exchanges the timing with the horizontal synchronization signal of the input video signal by exchanging with the access completion flag circuit 44 based on the request flag.
A part of the image memory is transferred from the image memory 3 to the buffer memory 60.

The data transferred to the buffer memory 60 in this manner is sequentially read from the buffer memory 60 by the interface control circuit 61 while synchronizing with the external device. By performing the reading operation in this manner, the interface control unit 61 can perform the interface with the external device asynchronously with the input video signal.

Writing from an external device can be performed in a similar manner. This means that data is transferred from the interface control unit 61 to the buffer memory 60, an access request flag is set in the circuit 45 after the transfer is completed, and the transfer direction of the memory is set in reverse (actually, the image memory 3 is switched to the write mode). , The buffer memory 60 is set to the read mode).

FIG. 6 is a block diagram showing still another embodiment of the present invention. In this figure, the same components as those in FIGS. 1, 3 and 5 are denoted by the same reference numerals. In addition, reference numeral 71 denotes a read / write control circuit for the line memory 72 provided inside the halftone control circuit 9, and 47 denotes a read / write control circuit for the buffer memory 60 via the selector 41.

In the present embodiment, an interface control circuit 61 for reading out data to the halftone control circuit 9 for printing and controlling an interface with an external device includes:
It shows an integrated configuration. That is, according to this embodiment, both the printing operation and the interface reading can be performed through the same circuit.

Specifically, in this embodiment, as shown in FIG. 6, the data line of the buffer memory 60 is divided into the line memory 72 in the halftone control circuit 9 and the data output line of the interface control circuit 61. And are directly connected to. Further, the interface control circuit 61
And the halftone control control circuit 9 are connected to the system controller 11 and are controlled so that the two circuits do not operate at the same time.

FIG. 7 is a timing chart showing the operation of the circuit of FIG. 7, reference numeral 81 denotes an energization control pulse for controlling energization of the thermal head, and 82 denotes a line memory 72.
Access request signal for making a read request to
Is a horizontal synchronizing signal, 84 is an EN (enable) signal indicating that writing to and reading from the image memory 3 is possible, 85
Indicates an image data transfer signal from the image memory 3 to the buffer memory 60.

Reference numeral 86 denotes a write clock to the line memory 72, 87 denotes a BUSY signal indicating that the line memory 72 is transferring, and 88 denotes an output signal from the interface control circuit 61.

Hereinafter, the circuit operation of FIG. 6 will be described with reference to FIG. When the energization of one line of data in the thermal head is completed, the halftone control circuit 9 outputs a one-line print end signal to the system controller 11. Syscon 1
When receiving the one-line print end signal, the 1 issues an access request to the access request flag circuit 45 of the memory control circuit 6 and simultaneously outputs an access prohibition signal to the interface control circuit 61.

As a result, no access is made from the interface control circuit 61 until the data of the next line is taken into the buffer memory 60 and further transferred to the line memory 72 in the halftone control circuit 9. . On the other hand, the interface control circuit 61 detects a period during which the halftone control control circuit 9 is not accessing based on the prohibition signal, and performs reading and writing to and from the external interface during this idle period.

FIG. 7 is a timing chart showing this state. The EN signal in FIG. 7 is an EN signal output by the system controller 11 in response to the read request signal (memory access request) 82. This signal is supplied to the halftone control circuit 9
Is a status signal indicating that the next line read may be performed. On the other hand, the interface control circuit 61 indicates that the halftone control circuit 9 is accessing the image memory 3 during this period.
Indicates that access is prohibited.

When the EN signal 84 becomes a high level signal, the interface control circuit 61 becomes accessible. The readout to the outside started at a1 (85 in FIG. 7) is temporarily interrupted by the EN signal 84 for the A1 period.
When the transfer is completed for the number of data requested by the external device, the interface control circuit 61 terminates the access to the image memory 3. On the other hand, as the print line advances to A1 and A2, the halftone control circuit 9
The line data is sequentially read from the image memory 3 and the thermal head is driven.

As described above, the two read circuits read the image data from the image memory 3 by dividing the time according to the control signal EN of the system controller 11. By doing so, data can be efficiently and quickly transferred from the image memory.

FIG. 8 is an explanatory diagram showing a print image according to another embodiment of the present invention. FIG. 9 is a circuit diagram showing a configuration example of the read / write control circuit of FIG. In FIG. 9, reference numeral 90 denotes an address counter for generating a read address; 91, an address decode circuit for decoding the address to detect whether or not the address has reached a predetermined address or more; and 92, an address based on the output of the address decode circuit 91. A gate circuit that gates the output of the counter 90;
93 is the output of the gate circuit and the original address counter 90
Is an addition circuit for performing the addition.

The operation of this circuit will be described below with reference to FIGS. As can be seen from the print example of FIG. 8, in this embodiment, a character image is superimposed on a print image and can be printed. To obtain such a print, a print image and a character image are stored at different addresses in the image memory 3 (in the embodiment, images are recorded from addresses n1 to n2 and character images are recorded from n3 to n4). Need to be recorded.

When stored, only the image data is displayed on the monitor at the time of reproduction, and the character data is displayed on the lower side of the monitor. Since a normal monitor is designed to display about 90% of the screen, character data is not displayed on the screen. On the other hand, it is easier to see the print image if the character image is superimposed immediately below the image. So the image memory 3
The character data is recorded outside the display range, and the character data is printed next to the image data during printing.

To realize this, the read address circuit of the image memory 3 may have an offset function. Actually, as shown in FIG. 9, a detection circuit 91 for determining whether or not the address exceeds the address n2 is provided.
Is detected, by giving an offset of (n3-n2) to the address, the offset address of the image memory 3 can be increased from n1 to n2, and then the address memory can jump from address n2 to address n3. This is achieved. As described above, it is also possible to realize the present invention by giving a read address from the system controller 11 each time without having an offset address.

FIGS. 10, 11 and 12 are diagrams for explaining still another embodiment of the present invention.
0 is an explanatory diagram showing an output image to a monitor, FIG. 11 is a block diagram showing its configuration, and FIG. 12 is a timing chart showing the circuit operation of FIG.

In FIG. 11, the same components as those in FIG. 6 and corresponding components are denoted by the same reference numerals. In addition, 100 is a timer that generates a signal indicating a certain position in a horizontal blanking period based on the input horizontal synchronization signal, 10
Reference numeral 1 denotes a memory control unit that performs memory access using the timer signal.

An address shift circuit 102 shifts the address generated by the memory control unit 101 and generates an address for skipping image data recorded in the image memory 3. Reference numeral 103 denotes a signal generated by the memory control unit 101, which inputs and outputs the image memory 3 from the AD converter 2,
A changeover switch for switching to the DA converter 4 side or the buffer memory 60 side.

Hereinafter, description will be made with reference to FIGS. 10, 11, and 12. FIG. In the present embodiment, an image recorded in the image memory 3 is reduced and displayed at the upper right of the screen during printing, the image display time is reduced, and the read time to the halftone control circuit is increased. This is to check what is being printed during printing, but since it is not necessary to display the full screen, the display screen is made smaller and the idle time is used for reading to the halftone control circuit for printing.

This embodiment will be described with reference to FIG.
The writing operation to the image memory 3 is performed in the same procedure as that described above. At the time of reading, the timer circuit 100 generates a start signal at a position corresponding to the right end of the screen (for example, at a position 35 μs from the fall of the horizontal synchronization signal, based on the input horizontal synchronization signal. The start signal is sent to the memory control unit 101.
Is input to

At the time of writing, the memory control unit 101
The address of the image memory 3 is generated in synchronization with the clock of the / D converter 2. At the time of reading, addresses are sequentially generated based on this start signal. The address signal generated in this manner is supplied to the address shift circuit 10
Shifted by two. The shifted address is as follows.

Address before shift 1, 2, 3, 4, 5, 6, 7, 8 Address after shift 2, 6, 10, 14, 18, 22

As a result, the image data read from the timer circuit 100 has a form in which the original image is reduced to １ ／ in the horizontal direction. Similarly, horizontal addresses are also accessed intermittently. The memory control unit 101 sets the output of the memory to the read mode during this read period, but prohibits the output of the image memory 3 during the other periods and directly outputs the output of the A / D converter 2 to the D / A converter 4. To be entered.

FIG. 12 shows an image memory switching signal showing this state. As a result, reading is performed to the D / A converter 4 while the image memory switching signal is low, and reading is performed to the buffer memory 60 while the image memory switching signal is high.

As a result, as compared with the conventional method of reading during the horizontal blanking period, a longer reading time to the buffer memory 60 can be taken, and more data can be read to the halftone control circuit earlier. If data can be read at such a high speed, the printing time can be shortened.

[0071]

As described above, according to the video printer control circuit of the present invention, the image data read out from the image memory is displayed on the monitor while being printed at a timing different from the image display. There is an advantage that image data can be read, and as a result, high-speed printing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing a circuit operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a modification of the memory control circuit in FIG. 1;

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3;

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a timing chart showing a circuit operation of the embodiment of FIG. 6;

FIG. 8 is an explanatory diagram showing an image generated by the embodiment of FIG. 9;

FIG. 9 is a block diagram showing a main part of still another embodiment of the present invention.

10 is an explanatory diagram showing a timing chart illustrating an operation of the embodiment of FIG. 11 and a generated image.

FIG. 11 is a block diagram showing still another embodiment of the present invention.

FIG. 12 is a timing chart showing a circuit operation of the embodiment of FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Decoder, 2 ... A / D converter, 3 ... Image memory, 4
... D / A converter, 5 ... sync separation circuit, 6 ... memory control circuit, 7 ... clock generation circuit, 8, 40, 72 ... line memory, 9 ... half tone control circuit, 10 ... thermal head, 11 ...
System control, 12 mechanism, 20 memory control unit (1), 21 horizontal blanking generation circuit, 22 access flag circuit, 41 selector, 42 write counter, 43 read counter, 44 access completion flag circuit, 45: access request flag circuit, 60: buffer memory, 61: interface control circuit, 47, 7
1: write / read control circuit 91: decoder circuit
93 ... addition circuit, 100 ... timer, 101 ... memory control unit, 102 ... address shift circuit, 103 ... selection switch

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuichi Takano 1410 Inada, Katsuta, Ibaraki Prefecture Inside the Tokai Plant of Hitachi, Ltd. (72) Inventor Akihiro Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Image Media Research Laboratories (56) References JP-A-59-228477 (JP, A) 62-88489 (JP, A) JP-A-1-116820 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/937

Claims (1)

(57) [Claims] When capturing an input video signal as image data into an image memory, the input video signal is captured in synchronization with a horizontal synchronizing signal separated from the video signal, and then the image data is read out from the memory and output to the monitor side. At the same time, a control circuit of the video printer for outputting to the printing means side for printing detects a horizontal retrace period from the horizontal synchronizing signal separated from the video signal, and outputs a signal representing the period as a blanking signal. A ranking generating circuit, and a flag circuit that waits for a blanking signal from the blanking generating circuit when there is a signal indicating that printing is possible from the printing unit, and outputs a signal indicating a horizontal retrace period represented by the signal as a flag, When the flag signal is input from the flag circuit, it is independent of reading image data to the monitor side. A read / write control circuit for a buffer memory, which reads image data to be sent to the printing means for printing from the image memory and writes it in the buffer memory, and then reads from the buffer memory and transfers it to the printing means. And read control for an external device for reading to an external device such as a personal computer, separately from the read control circuit for the buffer memory for reading the contents of the buffer memory toward a printing means. A video printer control circuit having a circuit, wherein the read control circuit for the external device is operated during a period in which the read control circuit for the buffer memory is not operating.