JPH0522694A - Video printer signal processing circuit - Google Patents

Abstract

PURPOSE:To independently and simultaneously drive plural printers by reading from a memory except the video period, adding an ID code and fetching data into a printing control circuit when the ID code is coincident. CONSTITUTION:A printer control circuit 16 receives a printing starting signal from each printing control circuit 12 and sends a reading signal to a memory control circuit 2 in the sequence. The memory control circuit 2 reads image data from an image memory 3 for a video period based on a counter output and outputs them to a DA converter 17. On the other hand, for the synchronizing period, an address equivalent to a printing line is prepared a reading signal from the printer control circuit 16, read by a random access action from the image memory 3, an ID code is added, and inputted to a thermal-sensing head driving circuit 10 of each printer. Each thermal-sensing head driving circuit 10, when the detected ID code is coincident with the ID code of each printing control circuit 12, fetches the image data read from the image memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit of a video printer for obtaining a print from a video signal, and more particularly to a memory reading system for reading image data written in a video memory to a plurality of thermal head driving circuits.

[0002]

2. Description of the Related Art In a conventional video printer, an input video image is temporarily recorded in an image memory as described in JP-A-58-138667 and then sequentially read from the memory in synchronization with the operation of a print mechanism. , A method of driving a thermal head has been described. The specific operation is directly in the case of a monochrome image, and once in the case of a color image, it is once decoded and converted into an RGB signal, and an analog signal is converted into a digital signal by an AD converter, respectively, and image data for one screen (NTSC signal) is converted. Then, it is once recorded in the image memory that stores 525 (vertical) and 640 (horizontal) data. The recorded image data is read for confirmation before printing and DA
The converter converts the digital signal into an analog signal and the encoder circuit converts it into an NTSC signal, which is displayed on the monitor.

On the other hand, in the printer control circuit, the image signal recorded in the image memory is read in units of vertical or horizontal lines and the thermal head is heated for a time proportional to the value of the image data to transfer the ink to the paper. Is. When the transfer of one line is completed, the printer control circuit moves the paper by one line, reads the data of the next one line from the image memory, and prepares to print the next line. When the paper is moved by one line, the printer control circuit transfers the data of the next one line to the paper by the same operation as described above.

In this way, a video image composed of 525 vertical lines and 640 horizontal lines is transferred to paper by repeating the transfer to the paper line by line. In the case of a color image, each color of RGB, for example, one side is printed with the R signal, and then the G signal is accurately aligned and printed on the paper transferred with the R signal. In this way, a color print is obtained by printing three colors in an overlapping manner.

[0005]

In the above prior art, since the image memory gives priority to reading to the monitor, the next image is stored at the time of printing, or a plurality of printers are driven. I couldn't do it. Further, since the reading is performed on the monitor, there is a problem that the reading speed to the thermal head is limited and the printing speed is limited.

An object of the present invention is to provide a printer control circuit capable of driving a plurality of thermal heads independently of reading from a monitor and without restriction of printing speed.

Another object of the present invention is to simultaneously drive a plurality of printers and manage the memory of these printers.

[0008]

In order to achieve the above-mentioned object, the storage means stores the image data after analog-digital conversion in the storage means, and the thermal head drive circuit corresponds to the operation of the printing mechanism and the print position. When the thermal head comes to, a read command is sent to the random access means. As a result, the random access circuit performs the reading and writing operations of the memory during the video period of the video signal, and the reading operation by the random access circuit during the other periods, and the image data is read from the storage means and printed.

Further, when a plurality of printers are simultaneously driven, the read control circuit adds an ID code to the read signal from the storage means to the image signal read during a period other than the video period, and each thermal head drive circuit adds this ID code. A plurality of thermal head drive circuits are driven at the same time by determining whether or not the image data sent by being identified is taken. Further, by providing the temporary buffer memory, the image data captured during the period other than the video period is transferred to the thermal head drive circuit in the handshake mode for efficient transfer.

[0010]

The storage means stores image data, and the address is determined and stored by the writing means on a frame-by-frame basis. The sync separation circuit separates the sync signal contained in the video signal from the video signal and detects and outputs each sync signal. The counter counts based on the synchronization signal and outputs a signal for distinguishing the video recording area from other areas.

The writing means is a circuit for generating an address and a control signal for writing the analog-digital converted image data in the storage means. Since the random access means reads out image data required for printing line by line from the storage means in the area determined by the counter, it generates an address and a control signal.

The thermal head drive circuit is a conversion circuit for converting line-by-line image data read by the random access means into a PWM signal for driving the thermal head.
The print control circuit receives the read signal of each printer, determines the access address of the random access circuit, the random access circuit reads the image data from the storage means, and supplies the image data to each thermal head drive circuit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment according to the present invention, and FIGS.
A timing chart showing the operation of the present invention is shown in FIG. Figure 1
1, an AD converter for converting a video signal into an analog signal, a memory control circuit 2 for writing the AD-converted video signal to an image memory, an image memory 3 for storing a plurality of frames of image data, and a thermal head driving device 4. When the first printer control circuit including the circuit conveys the thermal head drive circuit 10 and thermal head 11, the control circuit controlling the operation of the printer mechanism 13 and thermal head drive circuit 10 and the printing paper, and reaches the print position. The print head 13 is composed of a print mechanism 13 that presses the thermal head onto the printing paper and feeds the paper line by line.

A second printer control circuit 5 includes a line memory 15 for storing print line data, a thermal head drive circuit 10, a thermal head 11, and a print control circuit 1.
2. The printer mechanism 13. A printer control circuit 16 controls a plurality of print control circuits.
The read order is determined with respect to the read signals from the printer control circuits 4 and 5, the read signals are given to the memory control circuit 2, and the image data of each frame is read from the image memory line by line. Reference numeral 17 denotes a DA converter for converting the image data read out from the image memory by the memory control circuit into a digital analog signal and outputting it to the monitor.

In FIG. 1, the input video signal is A
The digital signal is converted by the D converter 1. The converted digital signal is written in the image memory 3 by generating an address on the basis of the sync signal separated from the video signal by the sync separation circuit (not shown) in the memory control circuit 2. The written video signal is the same as the memory control circuit 2
By this, addresses are generated in the same order as at the time of writing and read from the image memory 3, the digital signal is converted into an analog signal by the DA converter 17, and the image recorded on the monitor is checked.

The printing operation will be described below. Each printer control circuit 12 drives the mechanism 13 to convey the printing paper. When the conveyed printing paper reaches the printing position, the mechanism 13 notifies the print control circuit 12 that the printing paper has arrived at the printing start point. In response to this, the print control circuit 12 notifies the printer control circuit 16 of the print start signal.

The printer control circuit 16 receives the print start signal from each print control circuit 12 and sequentially sends a read signal to the memory control circuit 2. The memory control circuit 2 has a counter that separates the video period and the sync period from the sync signal. Based on the output of this counter, the image data is read from the image memory 3 during the video period and output to the DA converter 17.

On the other hand, during the synchronization period, an address corresponding to a print line is generated based on a read signal from the printer control circuit 16 and read from the image memory 3 by a random access operation. An ID code is added to the read address to detect the heat sensitivity of each printer. Input to the head drive circuit 10. Each thermal head drive circuit 10 detects the sent ID code and
When the D code matches the ID code of each print control circuit 12, the image data read from the image memory 3 is fetched.

FIG. 2 is a timing chart showing the operation of the image memory 3. The counter output generated based on the sync signal separated from the video signal generates a signal for distinguishing the video signal area and the sync signal area. From this counter output, the memory control circuit 2 reads the print data during the synchronization period, and the video signal area is D
The signal to the A converter 17 is being read.

FIG. 3 shows how the printer control circuit 16 distributes data to a plurality of print control circuits 12. The first print control circuit 12 is printed by the printer A, starts printing one line at point (a), and finishes printing one line at point (b). At point (b), the print control circuit 12 outputs a read request for the next print data. However, at this time, since the printer B is reading the data of the next line, the reading is not performed immediately.

When the reading of the printer B is completed (c), the memory control circuit 2 starts the reading of the printer A (d). When the reading is completed (e), the print control circuit 12 once returns the Busy signal to the "H" level, indicating that the next line data has been read. On the other hand, the printer B prints the section (f)-(g),
The data of the next line is read from the memory control circuit 2 in the period of (h)-(c). In this way, the image data stored in the image memory 2 is read by the memory control circuit 2 in a time division manner and input to the print control circuit 12.

FIG. 4 shows the configuration of the memory control circuit 2 in more detail. In FIG. 4, 20 is a sync separation circuit for separating the sync signal from the video signal, 21 is the address of the monitor data read from the image memory 3 to the DA converter 17 during the video period, and 21 is from the image memory 3 to the print control circuit 12 during the sync period. A selector for selecting an address of print data to be read, a transfer address circuit 22 for generating an address for monitor reading, a memory address circuit 23 for generating an address for reading print data, and 24: a video signal area and a sync signal from a sync signal. A transfer area generation counter that generates a signal that selects an area,
Reference numeral 25 is a memory write clock generation circuit for generating a clock for reading the image memory 3 in the synchronization signal area determined by the output of the transfer area generation counter 24, 26
Is a microcomputer that interfaces with the memory control circuit, the print control circuit 12, and the printer control circuit 16.

The operation of the memory control circuit 2 will be described below with reference to FIG. The input video signal is A in the AD converter 1.
After D conversion, it is output to the I / O line (not shown here) of the image memory 3. On the other hand, the signal separated in synchronization by the synchronization separation circuit 20 is input to the transfer area generation counter 24,
The counter output that distinguishes the sync signal area from the video signal area is obtained. At the time of writing, an address indicating the memory area of the image memory 3 determined by the microcomputer 26 is input to the transfer address generation circuit 22 as an initial value, and then sequentially written according to the synchronization signal. Similarly, at the time of reading, an address is similarly generated, read from the image memory 3 and output to the I / O line of the image memory 3, DA-converted, and output to the monitor.

On the other hand, the print data is accessed from the memory only in the synchronous signal area by the counter output, and the microcomputer 26 adds the ID code to the I / O line and inputs it to the thermal head drive circuit 10.

FIG. 5 shows a signal format with an ID code input to the thermal head drive circuit 12. The ID code consists of 2 bits and can specify four printers.

FIG. 6 shows a memory map of the image memory 3. The memory is composed of 640 bits in the horizontal direction and 512 bits × n in the vertical direction. Area A records the image of printer control circuit A, and area B sequentially records the image of printer control circuit B. As described above, the memory control circuit 2 can read a plurality of images recorded in the image memory 3 in a time division manner and supply image data to each thermal head drive circuit 10.

FIG. 7 shows an example of the construction of the thermal head drive circuit. 7, the same symbols as those in FIG. 1 have the same functions. Reference numeral 30 is a line memory for recording image data for one line, 31 is an address circuit for driving the line memory 30, 32 is data of the line memory 30 read by the address circuit 31, and a value of the gradation counter 33. And a comparator for generating a thermal head drive signal, 33
Is a gradation counter which indicates the gradation that is being energized, 34 is a gate circuit which gates the write clock input to the address circuit 31 by the output of the ID coincidence circuit 35, 35 is the input ID code and the DIP switch 36 in advance. This is a matching circuit that matches the set ID of each print control circuit.

The operation will be described below with reference to FIG. The print data read from the image memory 3 is added with an ID code by the microcomputer 26 as shown in FIG. 6, and is input to the thermal head drive circuit 10. The thermal head drive circuit 10 takes out the ID code from the sent signal, matches it with the ID code set in advance for each print control circuit 12, and if it matches, writes it in the line memory 30. The clock is input to the address circuit 31 through the gate 34 and written in the line memory 30. If no match is found, the write clock is not input by the gate 34 and nothing is written in the line memory 30.

The data written in the line memory 30 is sequentially compared with the value in the line memory 30 by the gradation counter 33, converted into ON and OFF signals, and written in the shift register 40 of the thermal head 11. In this way, the energization ON / OFF is determined and driven by comparing each gradation.

As described above, the thermal head drive circuit 10 has the coincidence circuit 35 therein, and it is possible to drive a plurality of print control circuits 12 at the same time by performing the write control by coincidence with the preset ID code. It is also possible to take continuous video images into the image memory 3 once, check the contents on the monitor before printing, and print only the desired image. In this, the microcomputer 26 gives an address to the memory address circuit 23, sequentially reads the recorded images, and reads them to the DA converter 7.

FIG. 8 shows another embodiment of the present invention. 8, the same symbols as those in FIG. 4 have the same functions. Reference numeral 40 is a write flag register composed of 4 bits, and each bit indicates the recording status of the image memory 3. Reference numeral 41 is a flag register input circuit for changing the contents of the flag register 40 by the input of the microcomputer 26. Microcomputer 2
6 first sets the entire contents of the flag register 40 to "L" to set a mode in which nothing is written. When the first frame is recorded, the microcomputer 26 sets the MSB bit of the flag register 40 to "H". Thereafter, a plurality of frames are sequentially written in the image memory 3.

At this time, the microcomputer 26 uses the flag register 4
The contents of 0 are updated bit by bit. Thereby, the microcomputer 26 can know whether each area of the image memory 3 is already recorded or is empty by referring to the content of the flag register 40, and the address to be sent to the memory address circuit 23 is determined based on this. It is a thing. When the flag register 40 is all "H", the recording is not possible, the microcomputer 26 does not generate the write address, and the writing is stopped. At the same time, the microcomputer 26 has an LED
(1) (not shown here) is driven to display that the contents of the image memory 3 are in use and cannot be stored.

When the printing operation is performed and the image data for one screen is read from the image memory 3, the microcomputer 26 sets the bit of the corresponding flag register 40 to "L" and the area of the image memory 3 is changed. Another LED (2) is used to indicate that the space is empty. As described above, in this embodiment, the recording state of the image memory 3 can be displayed, and the user can know the empty state of the memory.

FIG. 9 is a block diagram of another embodiment according to the present invention. 9, the same reference numerals as those in FIG. 8 have the same functions. FIG. 10 is a timing chart showing the operation of FIG.

In FIG. 9, reference numeral 50 is a buffer memory for temporarily recording the data read from the memory. An address circuit 51 controls the address of the buffer memory 50 and generates a write address and a read address. Reference numeral 52 denotes a memory reading circuit that generates a main memory address based on the address generated by the address circuit 51, and performs data reading from the main memory in synchronization with the address circuit 51. Reference numeral 53 is a memory reading circuit, which writes in the memory based on the sync signal separated from the video signal by the sync separation circuit 20. Reference numeral 54 is a selector for switching addresses of the memory reading circuit 52 and the memory writing circuit 53, which is switched by a timing circuit. A timing circuit 55 generates an operation switching signal for each circuit from the synchronization signal. 56 is a microcomputer.

The operation will be described below with reference to the drawings. The input video signal is AD-converted by the AD converter 1 and written in the image memory 3. This state is shown in FIG. Video data is written from the AD converter 1 to the image memory 3 in real time during the video signal area. The written data is written into the buffer memory 50 in block units by causing the address circuit 51 to generate an address designated by the microcomputer during the horizontal blanking period.

This is shown in the buffer memory write clock of FIG. 10 (in FIG. 10, three pieces of data are collectively read in one blanking period). The data once written in the buffer memory 50 is sent to the print control circuit 12 at a slower speed than the reading speed at the time of being read from the image memory 3 to the buffer memory 50 in the next horizontal video period according to a command from the microcomputer 56. Read out.

In the buffer memory reading of FIG. 10, three data are read from the buffer memory over one horizontal video period. At this time, a handshake operation is performed between the address control circuit 51, which controls the reading of the buffer memory 50, and the microcomputer 56.
The BUSY signal becomes “H” level when reading from the image memory 3 and when reading one by one.
The reading control is being performed. Further, the address circuit 51
The address of is read out to the memory reading circuit 52, and the reading of the buffer memory 50 and the reading of the image memory 3 are performed in conjunction with each other.

[0039]

According to the present invention, a plurality of print circuits can be driven by one memory control circuit, and a large number of different prints can be created at a high speed.

[Brief description of drawings]

FIG. 1 is an overall block diagram according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the blocks described in FIG.

FIG. 3 is a timing chart showing the operation of the blocks described in FIG.

FIG. 4 is a block diagram showing one configuration example of the memory control circuit described in FIG.

FIG. 5 is a data format 1 input to a thermal head drive circuit.
It is explanatory drawing which shows an example.

FIG. 6 is an explanatory diagram showing a memory map of an image memory.

FIG. 7 is a block diagram showing a configuration example of a thermal head drive circuit that prints image data to which an ID code is added.

FIG. 8 is an overall block according to another embodiment of the present invention.

FIG. 9 is an overall block diagram according to another embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of the embodiment shown in FIG.

[Explanation of symbols] 1 AD converter 2 Memory control circuit 3 image memory 4,5 print control 10 Thermal head drive circuit 11 Thermal head 12 Print control circuit 13 Mechanism 15 line memory 16 Printer control circuit 21 selector 22 Transfer address control circuit 23 Memory address circuit 24 Memory write clock generator 26 Microcomputer 30 line memory 32 comparator 33 gradation counter 35 Matching circuit 40 flag register

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H04N 5/76 E 7916-5C (72) Inventor Tatsuya Ishihii 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Incorporated company Hitachi Ltd.Video Media Research Institute (72) Inventor Koichi Tomatsu 1410 Inada, Katsuta City, Ibaraki Pref., Tokai Plant, Hitachi Ltd. (72) Inventor Junichi Shoji 1410 Inada, Katsuta City, Ibaraki Hitachi Ltd. Tokai factory

Claims (5)

[Claims] 1. A video signal is converted into a digital signal and stored in a storage means, which is sequentially read from a memory in a line unit at the time of printing and inputted to a thermal head driving means, and the thermal head driving means drives the thermal head to perform printing. In a video printer signal processing circuit, a sync separation circuit that separates a sync signal from a video signal, a counter that separates a video signal area and a sync signal area from the sync signal separation circuit, and a video signal period based on the counter output. Comprises a writing means for writing a video signal in the storage means, and a random access means for performing random access from the memory except during the video signal period, the output of the random access means is connected to the input of the thermal head drive circuit, It is stored in the storage means by the read command signal from the thermal head drive circuit. Video printer signal processing circuit image data reading was characterized by perform printing control of lines. 2. The video printer signal processing circuit according to claim 1, wherein the video printer signal processing circuit has a plurality of thermal head drive circuits and memories for a plurality of frames, and a read command signal from each thermal head drive circuit is sent to the print control circuit. Connected, the print control circuit reads the image signal of each frame by adding the ID code of each thermal head drive circuit from the memory in the order of the read command signal, and inputs it to each thermal head to print different frame images at the same time. Characterized video printer signal processing circuit. 3. The memory write means according to claim 1, wherein the memory write means determines a write area of the storage means at the time of writing to the memory from a flag circuit for storing the memory write completion, an output of the flag circuit and an input of the print control circuit. The address circuit clears the flag circuit of the area read out by printing after printing is completed, and outputs a write-disabled signal without writing in the memory when there is no empty area at the time of writing. Printer signal processing circuit. 4. The video printer signal processing circuit according to claim 1, wherein the memory writing circuit clears the image data of the printed area and the flag circuit after printing is completed. 5. The random access means according to claim 1, wherein the random access means controls a memory means, a temporary buffer memory connected to the memory means, a read circuit for reading the memory means, and a read / write operation for the temporary buffer memory. Image data read from the storage means by the reading circuit during a period other than the video period of the video signal is temporarily stored in a temporary buffer memory,
A video printer signal processing circuit characterized in that the read command of the thermal head drive circuit is input to the memory control circuit to read it from the temporary buffer memory to the thermal head drive circuit.