JPH05167808A - Thermal head driving circuit for video printer - Google Patents

Abstract

PURPOSE:To provide a thermal head driving circuit shared by a thermal head for print of NTSC signal of (64 dots X eight blocks) and a thermal head for print of PAL signal of (64 dots X 10 blocks). CONSTITUTION:In the thermal head driving circuit 8, data storage memory equivalent to one line comprises (64 words X 9) memory 49-57. When the thermal head for NTSC is driven, data is transferred by conforming eight memory from the end of the nine memory to eight blocks, and when the thermal head for PAL is driven, the data is transferred by conforming nine memory to the central parts of ten blocks (29-38). Thereby, it is possible to prevent a print image from being shifted to the terminal part of print paper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head driving circuit for a video printer, and more particularly, to a NTSC signal as a video signal to be printed.
Even when the thermal head for SC signal is attached to the printer, or when the video signal to be printed is a PAL signal and the thermal head for PAL signal is attached to the printer, the same thermal head drive circuit is used. The present invention relates to a thermal head drive circuit of a video printer which can be driven and can be commonly used for both NTSC signals and PAL signals.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing an overall configuration of a general video printer. In the figure, 1 is an analog signal processing circuit, 2 is an A / D converter, 3 is an image memory, 4 is a D / A converter, 5 is an analog signal processing circuit, 6
Is a monitor, 7 is an image memory control circuit, 8 is a head drive circuit, 9 is a thermal head, 10 is a system controller, 1
Reference numeral 1 is a printing paper moving means.

The circuit operation will be described with reference to FIG. A video signal (image input) to be printed is input to the analog signal processing circuit 1. Then, the analog signal processing circuit 1 performs analog processing such as color decoding and sends the processed image signal to the A / D converter 2. A / D converter 2
Converts an analog image signal into a digital image signal,
Transfer to the image memory 3.

The image memory control circuit 7 includes an A / D converter 2
The digital image data from is stored in the image memory 3. When the image data is stored in the image memory 3, the image memory control circuit 7 controls the image memory 3 to read the image data. The image memory 3 sends the read image data to the D / A converter 4.

The D / A converter 4 converts the digital image data into analog image data and transfers it to the analog signal processing circuit 5. The analog signal processing circuit 5 performs analog processing such as encoding on the image signal, transfers the image signal to the monitor 6, and enables monitoring.

On the other hand, the image memory control circuit 7 controls the image memory 3 to read out data for printing. The image memory 3 reads out image data for printing and sends it to the head drive circuit 8. The head drive circuit 8 converts the digital image data into data for printing by the thermal head and transfers it to the thermal head 9. The thermal head 9 uses the print data from the head drive circuit 8 to
The image is printed on a print sheet (not shown).

The system controller 10 receives signals from an image memory switch and a print start switch (not shown) and receives an image memory control circuit 7 and a head drive circuit 8.
Alternatively, a control signal is sent to the printing paper moving means 11 to control each. Under the control of the system controller 10, the printing paper moving means 11 drives a drum (not shown) to move the printing paper. In this way, the printing operation of the video signal is performed.

In the video printer as described above, a conventional thermal head drive circuit is disclosed in Japanese Patent Laid-Open No. 1-2262.
As described in Japanese Patent Laid-Open No. 93, it was a drive circuit when the video signal to be printed is an NTSC signal. Further, even if the current video printer is widely viewed, it is possible to print only when the video signal to be printed is the NTSC signal or the PAL signal.

[0009]

In the above prior art, the thermal head drive circuit is separately designed as a drive circuit for printing only NTSC signals or a drive circuit for printing only PAL signals. Was being manufactured.

This is a structure of a thermal head for printing NTSC signals having different numbers of scanning lines (64 dots × 8, 51
2 dots make up one scanning line length) and a PAL signal print thermal head configuration (64 dots × 10,
One scanning line length is composed of 640 dots). As described above, if the thermal head drive circuits are separately designed and manufactured for the NTSC signal and the PAL signal, mass production cannot be performed, resulting in higher cost.

In order to solve this, the print data storage memory in the thermal head drive circuit is provided with the number of pixels of an effective width of one scanning line length (64 × 9, 57 in the case of a PAL signal).
If it is increased to 6 dots), 512 for NTSC signals
Since one scanning line length is composed of dots, one thermal head drive circuit can form a drive circuit for both PAL and NTSC signals.

In the thermal head drive circuit for NTSC signals, one scanning line length is composed of 512 dots, and the effective width of one scanning line length is also composed of 512 dots.
In the thermal head drive circuit for L signal, one scanning line length is 640
The effective width of one scanning line length is 576 dots, and the difference of 64 dots is idle.

The print data storage memory in the thermal head drive circuit is simply increased to the number of pixels in the case of the PAL signal, and one thermal head drive circuit is used for PAL and NTSC.
When the drive circuit for both signals is configured, it becomes a drive circuit for both signals, but when driven by the PAL signal, a head prepared for one scanning line length (64 dots x 10) is provided. When the input image data is recorded on photographic paper,
Since the recording is unevenly recorded at the upper end or the lower end of the photographic printing paper, there is a problem that the appearance is not good.

In view of the current state of the video printer technology as described above, an object of the present invention is to drive a thermal head for NTSC signals, when the thermal head is mounted on the printer, drive the head.
When a thermal head for AL signal is attached to the printer, it can drive the head, NTSC, PA
It is to provide a thermal head drive circuit shared by L.

Still another object of the present invention is NTSC, P
Even if the thermal head drive circuit is shared by the ALs and is driven by the PAL signal, there is a problem in that the image data recorded on the photographic paper is biasedly recorded at the upper end or the lower end of the photographic paper. It is to provide a thermal head drive circuit for both NTSC and PAL.

[0016]

In order to achieve the above object, according to the present invention, a thermal head driving circuit for a video printer is provided with one memory in which ninety-four memories are arranged.
64 should be provided for the length of the scanning line and supplied to the heating element.
When a thermal head for an NTSC signal including eight shift registers for receiving dot data arranged as one scanning line length is attached to a video printer, the above-mentioned 9
Eight of the one scan line length memory is replaced by the eight 1
A thermal head for a PAL signal that includes, as one scanning line length, a row of ten shift registers that are driven corresponding to the scanning line length shift register and receive the data of 64 dots to be supplied to the heating element, When mounted on a video printer, the nine memories for one scanning line length are driven so as to correspond to the nine shift registers of the ten shift registers for one scanning line length. I chose

At this time, in the thermal head drive circuit of the video printer, nine memory for storing 64 words are arranged for one scanning line length, and the data read from the memory is transferred to the next stage. When the thermal head for NTSC signals is mounted on the video printer, the above 9 selectors and gates are provided.
By controlling the selector and the gate, eight from the end of the memory for the scanning line length are driven corresponding to the eight shift registers for one scanning line length, and the thermal head for the PAL signal is obtained. However, when mounted on a video printer, the nine memories for one scanning line length are controlled by controlling the selector and the gate so that both ends of the shift registers for the one scanning line length of ten ends. The drive is made to correspond to the shift registers for the central nine, excluding the 0.5 for each.

[0018]

According to the thermal head driving circuit of the video printer of the present invention, when the thermal head for NTSC signal is mounted on the printer, the head is driven and the thermal head for PAL signal is mounted on the printer. The head can be driven, and thus NTSC, P
It is possible to provide a thermal head drive circuit shared by ALs.

Further, in the thermal head drive circuit for both NTSC and PAL according to the present invention, the image data recorded on the printing paper is biased toward the upper end or the lower end of the printing paper even when driven by the PAL signal. There is no inconvenience of being recorded.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below, but before that, the respective circuit configurations and operations of the thermal head for NTSC signal printing and the thermal head for PAL signal printing will be described. The thermal head described here divides data for one scanning line into a plurality of data blocks of 64 dots in order to transfer image data to be printed at high speed and perform high-speed printing.
The respective data blocks are transferred in parallel and input to the thermal head.

FIG. 11 is a block diagram showing the structure of a thermal head for NTSC signal printing. In the figure,
Reference numeral 9 is a thermal head, and 13 to 20 are shift registers each having a 64-bit configuration (actually, a 64-bit data latch is connected after each shift register, but omitted here for simplicity of description. ), 21 to 2
Reference numeral 8 is a group of 64 heating elements.

In FIG. 11, the data for printing is
Data for one scanning line length is divided into blocks of data (1) to data (8) from a drive circuit (not shown) and sent to the thermal head 9. Each data block has 6
As mentioned above, it is composed of 4 dots.

The data blocks of data (1) to data (8) are input to the shift registers 13 to 20, respectively. 6 which was serial-parallel converted by the shift register 13
The 4-bit parallel output constitutes the heating element group 21.
The shift register 13 is connected in parallel to the four heating elements.
The data content input to is generated by the heating element group 21 (printing).

Similarly, the shift registers 14 to 20 will be described below.
The data contents respectively input to the heating elements 22 to 28 are caused to generate heat (print).

FIG. 12 is a block diagram showing the structure of a thermal head for PAL signal printing. In the figure, 1
2 is a thermal head for PAL signal printing, 29 to 38
Each is a 64-bit shift register (actually, a 64-bit data latch is connected after the shift register, but omitted here to avoid complication of description), and 40 to 47 are 64 heating elements respectively. Group, 3
Reference numerals 9 and 48 denote 48 heating element groups, respectively.

Here, (64 × 8 + 2 × 48 = 608)
In the thermal head 12 for PAL signal printing,
Note that 608 dots can be printed (however, the effective number of dots for one scanning line length is 576 or 575).

In FIG. 12, the data for printing is
It is divided into data blocks of data (1) to data (10) and sent to the thermal head 12 from a drive circuit (not shown). The data (1) to the data (10) are input to the shift registers 29 to 38, respectively. Each of the 64 bits forming the shift register 30 and the 64 heating elements of the heating element group 40 are connected in parallel, and the data content input to the shift register 30 is generated in the heating element group 40 ( Print).

Similarly, the shift registers 31 to 37 will be described below.
The data contents respectively input to the heating elements 41 to 47 are caused to generate heat (print).

The uppermost 48 heating elements 39 are connected to the lower 48 bits of the 64-bit shift register 29 and generate heat (print) representing the lower 48 bits of the shift register 29. Do. In addition, the lowest 48 heating elements 48 are the 64-bit shift register 3
8 is connected to the preceding 48 bits of the shift register 38, and heat generation (printing) representing the data contents of the preceding 48 bits of the shift register 38 is performed.

Thermal head 9 for NTSC shown in FIG.
And the PAL thermal head 12 shown in FIG. 12 is greatly different from the thermal head 12 in the dot direction (scanning line direction) at the upper and lower ends of the 64-dot shift register (29, 3).
8) presence or absence, and for PAL, the heating element groups at the upper end and the lower end are composed of 48 dots, and there is a portion where 16 dots cannot be printed.

FIG. 13 is a timing chart showing the print timing (print sequence) of the video printer described in this embodiment. In other words, it is a timing chart showing the print timing of the one-line print of the present embodiment. In the figure, 73 is a print start signal for one line, 74 is an energization strobe signal, and 75 is data to the thermal head.

Since the video printer described in this embodiment has a density resolution of 256 gradations, the energization strobe signal 74 is 256 for one line print.
Output twice. 25 head ON / OFF data
64 data are transferred to the thermal head for each 1-gradation printing of 6-gradation printing.

As described above with reference to FIGS. 11 and 12, the structure of the thermal head is as follows.
One line (scan line length) of data is divided into 10 blocks for input, and 64 data are serially transferred to each of 10 data input lines. The 64 pieces of data will be sent to the thermal head once for each gradation and 256 times by printing one line.

Next, FIG. 14 is a schematic diagram showing a PAL image print image. In the figure, 71 is an image image, 49 to 57 are memories in the head drive circuit, 12 is a thermal head for PAL signal printing, and 72 is a thermal head.
Is a print image on photographic paper.

As shown in FIG. 14, the image of the PAL signal has 576 dots in the vertical direction (the number of scanning lines excluding the blanking period in the vertical direction is 575). Image data of 576 dots per line, 6 for each
It is input to the memories 49 to 57 having a 4-bit structure. The data respectively input to the memories 49 to 57 are input to the central portion of 576 dots excluding 32 dots at the upper end and 32 dots at the lower end of the thermal head 12.

The data that has entered the thermal head 12 is printed on 576 dots in the center of the printing paper. The problem here is that the number of heating elements is 576, whereas the shift register of the thermal head 12 is made of 64 × 10. If the image data of the memories 49 to 57 made of the 64 × 9 structure is sent to the shift register of the thermal head 12 as it is, the image image to be printed is biased to the upper end of the printing paper.

In order to solve this problem, the memories 49 to 57 are not constituted by 64 × 9, but 64 × 10
It may be configured with. However, with this memory configuration, 6
Unnecessary memory for 4 words is required. Therefore, in the present invention, it is considered that the upper 32 bits and the lower 32 bits of each of the 64-word memories 49 to 50 are divided into two 64-bit shift registers of the thermal head 12 and transferred.

Based on the above, embodiments of the present invention will be described below. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 8 is a head drive circuit according to the present invention, 49 to 57 are 64-word memories respectively, 68 is a memory control circuit, 69 is a gate signal generation circuit, and 66 and 6 are provided.
Reference numeral 7 is a gate circuit, 58 to 65 are selectors, and 70 is a head control circuit. Reference numeral 12 is the thermal head for PAL described above with reference to FIG.

The circuit operation of the head drive circuit 8 will be described with reference to FIG. The memory control circuit 68 controls the memories 49 to 57 to store 576 image data of one line in the vertical direction. At this time, the uppermost 64 pixels are stored in the memory 49, and the first 50 pixels are stored in the memory 50 from the 65th pixel.
The 28th pixel is stored. Similarly, data of 576 pixels is stored in the memory 57.

The image data once stored in the memories 49 to 57 in this manner is read in parallel by the memory control circuit 68 for printing. The memory 49 has an upper end 6
The four pieces of image data are sent to the selector 58 and the gate 66.
At this time, the reading order of the image data from the memory 49 is such that the upper 32 data in the memory 49 is read first and sent to the selector 58 and the gate 66, and the lower 32 data is read thereafter and sent to the selector 58 and the gate 66. ..

Further, the read address is started from the end of the upper 32 data of the memory 49. Details of the read data order will be described later.

Simultaneously with the reading of the memory 49, the memory 5
For 0, the upper 32 data are read and sent to the selector 58 and the sector 59, and then the lower 32 data are read and sent to the selector 58 and the selector 59. Selector 58
Selects the data in the memory 50 (the data in the memory 49 is not selected) when the memory 49 and the memory 50 read the upper 32 data, and reads the data in the memory 49 when the lower 32 data is read. The data is selected (the data in the memory 50 is not selected) and the thermal head 1 is selected.
2 is transferred to the shift register 30.

Under the control of the gate signal generating circuit 69, the gate 66 gates the image data from the memory 49 and transfers it to the shift register 29 in the thermal head 12. The data to be gated at this time is the shift register 2
This is the portion corresponding to the upper 32 data of 9.

The selector 59 also operates similarly to the selector 58, first selecting the data in the memory 51 and sending it to the shift register 31, and then selecting the data in the memory 50 and sending it to the shift register 31. Similarly, memories 51 to 57
Reads the image data and sends it to the selectors 59 to 65, respectively.

The selectors 59 to 65 send the image data to the shift registers 31 to 37. The gate 67 gates the image data from the memory 64 under the control of the gate signal generating circuit 69 and transfers the image data to the shift register 38 in the thermal head 12. At this time, the data to be gated is the portion corresponding to the lower 32 data of the shift register 38.

The head control circuit 70 generates a clock, a latch signal and a strobe signal necessary for driving the thermal head and sends them to the thermal head 12. By the above operation, the memory 49
It is possible to transfer the image data of 576 pixels input to the to 57 to the central portion of the shift registers 29 to 38 in the thermal head 12.

FIG. 2 is a schematic diagram showing how data is transferred from the memory of the head drive circuit 8 to the shift register of the thermal head 12 in FIG. Referring to FIG.
The sequence of data transfer from the memory 49 shown in FIG. 1 to the shift register 29 and the shift register 30 will be described in detail.

In FIG. 2, the same symbols as those in FIG. 1 operate in the same manner as in FIG. In FIG. 2, a represents the upper half data 1 to 32 of the memory 49, b represents the lower half data 33 to 64 of the memory 49, and c represents the upper half data 6 of the memory 50.
5 to 96, and d is the data 97 in the lower half of the memory 50.
Represents ~ 128.

FIG. 2 illustrates the details of the data transfer operation of FIG. 1. In the memory 49, the first dot to the 64th dot of 64 pixels at the upper end of the image are input. The 65th to 128th dots of the next 64 pixels are input to the memory 50.

Regarding the memory 49, first, the data of the upper portion of 32 dots (a) is read out in the address order of 32, 31, ... (From the lower side) and sent to the shift register 29 and the selector 58. Next, regarding the memory 49, the data of the lower 32 dot (b) portion is 64, 63, ...
The address is read out in the order of address and sent to the shift register 29 and the selector 58.

As for the memory 50, first, 96, 9
32 pieces of data (c) are read out in the address order of 5, ... And sent to the selector 58, and then data (d) are read out in the order of address of 128, 127 ,. In the selector 58, the first 32 data selects the data in the memory 50, the next 32 data selects the data from the memory 49, and sends them to the shift register 30.

In the shift registers 29, 30, 31 ..., The direction of data to be shifted shifts from top to bottom as shown in FIG. As in the above operation, the shift registers 29, 30, 31, ... Are assigned to b, a, b, c, d.
Enter data in the order of …….

The upper 32 pieces of data of the shift register 29 are gated by the gate 66 of FIG. 1 and are actually white data. Therefore, one line of image data stored in the 64 × 9 memory is transferred to the central position of the 64 × 10 shift register.

The data transfer timing in FIG. 2 will be described with reference to FIG. FIG. 3 is a timing chart showing the timing of data transfer from the head drive circuit 8 to the thermal head 12.

In FIG. 3, 76 is the output from the memory 49, 77 is the output from the memory 50, 78 is the MSB of the read address, 79 is the input of the shift register 29, 80 is the input of the shift register 30, and 81 is the selector 58. 65 switching signal.

As shown in the explanation of the operation in FIG. 2, the outputs from the memory 49 are 32, 31, 30 ...
Outputs in the order of 4, 63, ..., 33 addresses. Similarly, the output from the memory 50 is 96, 95, 94 ..., 6
5, 128, 127, ..., 97 are output in the order of address.

The MSB of the read address is switched at the timing 82 in FIG. As a result, the data read area is switched every 32 data transfers. On the other hand, the switching signals from the selectors 58 to 65 are also switched at the timing indicated by 82 in FIG. This allows the shift register 2
9 has 32, 31, 30 ... 1, 64, 63, ...
..., data is transferred in the order of 33 addresses.

The shift register 30 has 96, 95, 9
Data is transferred in the order of addresses 4 ..., 65, 64, 63 ,. Data can be transferred from the thermal head drive circuit to the PAL head by switching the address and the selector at the above timing.

When data is transferred from the thermal head drive circuit 8 according to the present invention to the NTSC head 9, the eight memories 49 to 56 shown in FIG.
It will be understood that there is no problem as long as the data is transferred in correspondence with the eight shift registers 13 to 20 in FIG.

Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing the configuration of a head drive circuit as another embodiment of the present invention. In the present embodiment, in short, when writing one line of data to the memories 49 to 57, one line of image data is
Move downward by 32 dots, and fold back the bottom 32 unwritable portion of 32 dots to the top 3 of the memory 49.
Memory 4 at the top when writing and reading 2 dots
The data of No. 9 is sent to the uppermost shift register and the lowermost shift register of the thermal head, and the image for one line is transferred to the central portion of the thermal head.

In FIG. 4, reference numeral 83 is a head drive circuit according to the present invention, and 84 is a memory control circuit. Other,
In FIG. 4, the same symbols as those in FIG. 1 have the same functions.

The circuit operation of FIG. 4 will be described. When the image data for one line is stored in the memories 49 to 57, the memory control circuit 84 shifts the data downward by 32 dots and stores the data (starts writing from the lower 32 dots of the memory 49). If 32 dots are shifted downward and stored, the 32 dots of the bottom data will overflow. This bottom 32 dots of overflow data is stored in memory 4
The upper 32 dots of 9 are stored.

When reading to the thermal head 12 for printing, the memory 49 reads the data in order from the bottom of the memory 49 and sends it to the gate 66 and the gate 67. The memories 50 to 57 send data to the shift registers 30 to 37, respectively. The gates 66 and 67 send data to the shift registers 29 and 38, respectively.

By the above operation, the 576 pieces of data stored in the memories 49 to 57 are transferred to the central portions of the shift registers 29 to 38 in the thermal head 12.

Details of the memory control circuit 84 in FIG. 4 will be described below with reference to FIG. FIG. 5 is a block diagram showing details of the memory control circuit 84. In FIG. 5, reference numeral 85 is a decoder, 86 is a counter, 87 is a register, 88 is a memory write control circuit, and 89 is a memory read control circuit.

In FIG. 5, the register 87 stores counter load data from a system controller (not shown) and sends it to the counter 86. The counter 86 loads the data in the register 87 and starts counting by the data transfer start signal from the system controller.

The counter 86 is the image memory control circuit 7
The image data synchronizing clock from (FIG. 10) is counted as the clock of the counter, the count value is sent to the decoder 85, and the memory 49 is used as the address.
Send to ~ 57. When the count value of the counter 86 is 0 to 63, the decoder 85 outputs WE (write enable) 1
Is generated and sent to the memory 49, and when the count value of the counter 86 is 64 to 127, WE2 is generated and the memory 5
Send to 0. Similarly, WE3 to WE9 are generated,
Send to memory respectively.

When the count value of the counter 86 reaches 576, the decoder 85 outputs a decode signal and sends it to the counter 86 as a reset signal. The counter 86 is
Upon receiving the reset signal, the count value is set to 0, and counting is started again.

The same number of image data synchronization clocks as the number of image data are input. The counter 86 counts up to the number of image data synchronization clocks. Read control circuit 89
Reads the data input to the memories 49 to 57 sequentially from the bottom of each memory.

Also in the present embodiment in which the write operation as described above is performed, the data of one line can be stored in the memories 49 to 57 while being shifted by 32 dots.
Individual data can be printed on the center of photographic paper.

Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the present embodiment, a white frame generating circuit (which gates digital image data so that the data becomes white dots at the time of printing) is provided, and when a message is to be printed on a multi-screen or a print image,
The white frame is created on the print image. The present embodiment is characterized in that a white frame generating circuit is provided in front of a memory that stores data for one line.

FIG. 6 is a block diagram showing the configuration of still another embodiment of the present invention, as described above. In the figure, 90 is a head drive circuit according to the present invention, and 91 is a white frame generation circuit. In FIG. 6, the same symbols as those in FIG. 1 have the same functions.

The circuit operation of FIG. 6 will be described. Before starting printing, white frame area data is input to the white frame generating circuit 91 in advance. The white frame generation circuit 91 replaces the image data in the area indicated by the white frame area data with white data in synchronization with the image data synchronization clock, and sends the white data to the memories 49 to 50. The operation after the memory is the same as that of the embodiment shown in FIG.

A print image printed using the head drive circuit 90 shown in FIG. 6 is shown in FIGS. 7 and 8.
FIG. 7 is a schematic diagram showing a print image in the case of multi-screen printing, and FIG. 8 is a schematic diagram in which the place where the message is inserted is replaced with white data when a message or the like is included in the print image. ..

The portion within the range shown by the dotted line in FIG. 7 is the printable portion. A is an upper frame, B is an image area, and C is an intermediate frame (white frame).

Details of the white frame generation circuit 91 in FIG.
This will be described with reference to FIG. FIG. 9 is a block diagram showing details of the white frame generation circuit 91. In FIG. 9, 92 is a C register, 93 is a B register, 94 is an A register, 9
5 and 97 are counters, 96, 98 and 99 are matching circuits, 100 and 101 are SR latches, and 102 is a gate.

The circuit operation of FIG. 9 will be described. Register 9
White frame area data (corresponding to A, B, and C in FIG. 7) is previously input to 2, 93, and 94 from the system controller (not shown) (value of register C> value of register B). ..

The counter 95 is reset by the 1-line print start signal, counts the image data synchronizing clock, and sends the count value to the matching circuit 96.
The coincidence circuit 96 outputs a coincidence output to the counter 97 and the counter 97 when the value of the register 94 and the count value of the counter 95 match.
-Send to R latch 101. The SR latch 101 makes its output low by the 1-line print start signal.

The S-R latch 101 has a matching circuit 96.
Output from the match signal from the gate 102
Send to. The counter 97 receives the match signal from the match circuit 96, starts counting the image data synchronization clock, and sends the count value to the match circuits 98 and 99.

The match circuit 99 sends a match output to the SR latch 100 when the value in the register 93 and the count value from the counter 97 match. The matching circuit 98 outputs a matching output to the SR latch 100 and the counter 97 when the value of the register 92 and the count value from the counter 97 match.
Send to reset.

The SR latch 100 makes its output high by the coincidence signal from the coincidence circuit 99. Further, the SR latch 100 makes the output low by the match signal from the match circuit 98 and sends it to the gate 102. Gate 102
When the gate signal is high, the image data is passed, and when the gate signal is low, the image data is white data. By such an operation, the horizontal white frame of the print image can be added to the image data.

In FIG. 9, only the addition of the horizontal white frame is described. However, by replacing the 1-line print signal with the 1-color print start signal and the image data synchronizing clock with the 1-line print start signal, the vertical line can be easily displayed. A white frame can be added.

By adding the above-mentioned vertical and horizontal white frames, it is possible to add a white frame portion as shown in FIGS. 7 and 8 to the print image, so that the break of the multi-screen can be made clear, or characters and pictures can be handwritten. You can make a margin for it.

[0084]

As described above, according to the present invention,
In one thermal head drive circuit, both a thermal head for NTSC of 64 × 8 configuration including eight 64-bit registers and a thermal head for PAL of 64 × 10 configuration including ten 64-bit registers, Can be driven selectively,
As a result, when configuring a printer that can print both NTSC signals and PAL signals, there is an advantage that only one head drive circuit is required.

Further, regardless of whether the NTSC signal is printed or the PAL signal is printed, there is no inconvenience that the print image is recorded on the photographic printing paper at the upper end or the lower end thereof.

Furthermore, since a white area can be inserted in the print image, a margin can be created when forming a multi-screen, and a handwritten character can be inserted by forming a large white area. There are advantages.

[Brief description of drawings]

FIG. 1 is a block diagram showing a thermal head drive circuit as an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a generation order of print data read addresses in FIG. 1 and an operation mode of a selector.

3 is a chart showing data transfer timing as operation timing of the thermal head drive circuit in FIG.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a block diagram showing a specific example of a memory control circuit in FIG.

FIG. 6 is a block diagram showing still another embodiment of the present invention.

FIG. 7 is a schematic diagram showing an example of a print image when a white frame is inserted.

FIG. 8 is a schematic diagram showing another example of a print image when a white frame is inserted.

9 is a block diagram showing a specific example of a white frame generation circuit in FIG.

FIG. 10 is a block diagram showing a general configuration of a video printer.

FIG. 11 is a block diagram showing the configuration of a thermal head for NTSC.

FIG. 12 is a block diagram showing a configuration of a PAL thermal head.

FIG. 13 is a chart showing print timing of the thermal head.

FIG. 14 is a schematic diagram showing a print image of a PAL image.

[Explanation of symbols]

8, 83, 90 ... Thermal head drive circuit, 9 ... NTSC thermal head, 12 ... PAL thermal head, 13-19 ...
Shift register, 21-28 ... Heating element group, 29-38 ...
Shift register, 39-48 ... Heating element group, 49-57 ...
Memory, 58-65 ... selector, 66, 67 ... gate,
68 ... Memory control circuit, 69 ... Gate signal generation circuit, 7
0 ... Head control circuit, 91 ... White frame generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Ishihii 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture

Claims (4)

[Claims] 1. A thermal head drive circuit for a video printer, wherein nine memories for storing 64 words are arranged for one scanning line length, and a shift for receiving data of 64 dots to be supplied to a heating element is provided. A first thermal head for printing a video signal of the first signal format, which includes eight registers arranged as one scanning line length, is mounted on the video printer, and the first thermal head is connected to the nine thermal heads. Eight of the memory for one scanning line length is driven corresponding to the eight shift registers for one scanning line length, and ten shift registers for receiving 64-dot data to be supplied to the heating element are driven. When the second thermal head for printing a video signal having the second signal format, which includes the arrayed lines as one scanning line length, is mounted on the video printer, the nine thermal heads are used. Memory line length fraction, the 1
A thermal head drive circuit for a video printer, characterized in that it is driven corresponding to 9 shift registers out of 0 shift registers for one scanning line length. 2. A thermal head drive circuit for a video printer, comprising nine memory for storing 64 words arranged as one scanning line length, and transferring data read from the memory to the next stage. In order to print a video signal of the first signal format, which includes a selector and a gate, and which includes eight shift registers arranged to receive the data of 64 dots to be supplied to the heating element and arranged as one scanning line length. When the first thermal head is mounted on a video printer, the eight thermal heads from the end of the memory of the nine scanning line lengths are controlled by controlling the selector and the gate. One scan line is driven by corresponding to the shift register for one scanning line length, and 10 shift registers that receive the data of 64 dots to be supplied to the heating element are arranged in one scan. When a second thermal head for printing a video signal having a second signal format, which is included as a length, is attached to the video printer, the nine memories for one scanning line length are stored in the selector. And gates to control 0 .. at both ends in the shift register for the length of one scan line.
A thermal head drive circuit for a video printer, characterized in that it is driven corresponding to nine central shift registers excluding five each. 3. The thermal head drive circuit according to claim 1, wherein a white data writing circuit that writes image data to be written in the memory in the preceding stage of the data storage memory for one scanning line length by replacing it with white data. A thermal head drive circuit for a video printer, wherein a white frame is generated in a printed image by providing the. 4. The thermal head drive circuit according to claim 3, wherein the white data writing circuit includes a first register (94) for storing data indicating an area of an outer frame portion of the print image, and the print image. A second register (93) for storing data indicating a partial area and a third register (92) for storing data indicating a white frame area between print images are provided. A thermal head drive circuit for a video printer, which is characterized in that