JPH07111319A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents
Nonvolatile semiconductor storage device and manufacture thereofInfo
- Publication number
- JPH07111319A JPH07111319A JP5277855A JP27785593A JPH07111319A JP H07111319 A JPH07111319 A JP H07111319A JP 5277855 A JP5277855 A JP 5277855A JP 27785593 A JP27785593 A JP 27785593A JP H07111319 A JPH07111319 A JP H07111319A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- word line
- polycrystalline
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000003860 storage Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 239000010408 film Substances 0.000 description 118
- 229910004298 SiO 2 Inorganic materials 0.000 description 24
- 239000010410 layer Substances 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば、電気的に書き
換えが可能な不揮発性半導体記憶装置及びその製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an electrically rewritable nonvolatile semiconductor memory device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ＥＥＰＲＯＭ等の不揮発性半導体記憶装
置を含む半導体装置の一般的な素子分離方法としてＬＯ
ＣＯＳ法がある。図９に、ＬＯＣＯＳ法を用いて素子分
離を行ったＥＥＰＲＯＭメモリセルの部分の概略断面図
を示す。図示の如く、Ｓｉ基板１１１の表面にＬＯＣＯ
Ｓ法で素子分離用のＳｉＯ2 膜１１２が選択的に形成さ
れており、このＳｉＯ2 膜１１２に囲まれた素子領域の
表面にトンネル酸化膜としてのＳｉＯ2 膜１１３が形成
されている。Ｓｉ基板１１１上には浮遊ゲートとしての
多結晶Ｓｉ層１１４がメモリセル毎に形成されており、
この多結晶Ｓｉ層１１４はＳｉＯ2 膜１１５に覆われて
いる。そして、多結晶Ｓｉ層１１４の上には、素子分離
用のＳｉＯ2 膜１１２の延びる方向（紙面に垂直な方
向）に直交する方向の制御ゲート、即ち、ワード線とし
ての多結晶Ｓｉ層１１６が形成されている。2. Description of the Related Art LO is used as a general element isolation method for a semiconductor device including a nonvolatile semiconductor memory device such as an EEPROM.
There is the COS method. FIG. 9 shows a schematic cross-sectional view of a portion of an EEPROM memory cell in which element isolation has been performed using the LOCOS method. As shown in the figure, the LOCO is formed on the surface of the Si substrate 111.
The SiO 2 film 112 for element isolation is selectively formed by the S method, and the SiO 2 film 113 as a tunnel oxide film is formed on the surface of the element region surrounded by the SiO 2 film 112. A polycrystalline Si layer 114 as a floating gate is formed on the Si substrate 111 for each memory cell.
The polycrystalline Si layer 114 is covered with the SiO 2 film 115. On the polycrystalline Si layer 114, a control gate in a direction orthogonal to the extending direction of the element isolation SiO 2 film 112 (direction perpendicular to the paper surface), that is, the polycrystalline Si layer 116 as a word line is formed. Has been formed.
【０００３】ところが、このＬＯＣＯＳ法には、素子分
離用のＳｉＯ2 膜１１２に生じるバーズビークによって
素子領域の幅が狭められるという寸法シフトの問題があ
った。また、ＳｉＯ2 膜１１２を選択熱酸化により形成
する時の熱処理によってＳｉ基板１１１中の不純物が横
方向に拡散し、素子領域での基板濃度プロファイルを変
化させて、トランジスタにおける狭チャネル効果を発生
させるという問題もあった。これらの問題は、近年の微
細化の要求により、深刻化してきている。特に、ＥＥＰ
ＲＯＭ等の電気的に書き換えが可能な不揮発性半導体記
憶装置の場合には、書き込み又は消去の際に一般に５Ｖ
以上の高電圧がワード線である多結晶Ｓｉ層１１６に印
加され、このために、素子分離領域に寄生チャネルが形
成され易いので、素子分離構造に特別の配慮が必要とな
る。However, the LOCOS method has a problem of dimensional shift that the width of the element region is narrowed by the bird's beak generated in the SiO 2 film 112 for element isolation. Further, the impurities in the Si substrate 111 are laterally diffused by the heat treatment when the SiO 2 film 112 is formed by selective thermal oxidation, and the substrate concentration profile in the element region is changed to generate the narrow channel effect in the transistor. There was also a problem. These problems have become serious due to the recent demand for miniaturization. Especially EEP
In the case of an electrically rewritable non-volatile semiconductor memory device such as a ROM, it is generally 5 V when writing or erasing.
The above high voltage is applied to the polycrystalline Si layer 116 which is a word line, and a parasitic channel is easily formed in the element isolation region for this reason, so that special consideration needs to be given to the element isolation structure.
【０００４】そこで、図１０に示すようなトレンチ構造
による素子分離方法が提案されている。このトレンチ分
離法では、Ｓｉ基板２１１の素子分離領域にトレンチ２
１７が形成されており、トレンチ２１７が、その内面を
ＳｉＯ2 膜２１２で覆われるとともに、ホウ素をドープ
したＰＳＧ膜、即ち、ＢＰＳＧ膜２１８で埋め込まれて
いる。そして、この素子分離構造により、浮遊ゲートで
ある多結晶Ｓｉ層２１４及び制御ゲートである多結晶Ｓ
ｉ層２１６もメモリセル毎に分離されている。そして、
互いに分離された多結晶Ｓｉ層２１６がワード線である
ＷＳｉ配線２１９で接続されている。この構造により、
ＬＯＣＯＳ法を用いた場合よりも微細なセル面積を実現
することができる。Therefore, an element isolation method using a trench structure as shown in FIG. 10 has been proposed. In this trench isolation method, the trench 2 is formed in the element isolation region of the Si substrate 211.
17 are formed, and the trench 217 is covered with the SiO 2 film 212 on its inner surface and is filled with a boron-doped PSG film, that is, a BPSG film 218. With this element isolation structure, the polycrystalline Si layer 214 which is a floating gate and the polycrystalline S layer which is a control gate.
The i layer 216 is also separated for each memory cell. And
The polycrystalline Si layers 216 separated from each other are connected by a WSi wiring 219 which is a word line. This structure allows
A finer cell area can be realized than in the case of using the LOCOS method.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図１０
に示したようなトレンチ分離法は、実際には、トレンチ
２１７の形成が難しく、また、製造工程も複雑となるの
で、未だ実用化には到っていない。However, as shown in FIG.
Actually, the trench isolation method as shown in FIG. 3 has not been put to practical use because it is difficult to form the trench 217 and the manufacturing process is complicated.
【０００６】そこで、本発明の目的は、従来のＬＯＣＯ
Ｓ法とほぼ同等の簡易な製造方法で実現でき、且つ、Ｌ
ＯＣＯＳ法のようなバーズビークによる寸法シフトや狭
チャネル効果を発生させず、更に、例えば、ワード線に
高電圧を印加しても寄生チャネルが形成されない素子分
離構造を持った不揮発性半導体記憶装置及びその製造方
法を提供することである。Therefore, an object of the present invention is to improve the conventional LOCO.
It can be realized by a simple manufacturing method almost equivalent to the S method, and L
A non-volatile semiconductor memory device having an element isolation structure that does not cause a dimensional shift or a narrow channel effect due to bird's beak as in the OCOS method, and further does not form a parasitic channel even when a high voltage is applied to a word line, and the same. It is to provide a manufacturing method.
【０００７】[0007]
【課題を解決するための手段】上述した課題を解決する
ために、本発明では、各メモリセルが半導体基板とワー
ド線との間に電荷蓄積層を有する不揮発性半導体記憶装
置において、ワード線方向に隣接するメモリセル間を互
いに分離するための素子分離領域における前記半導体基
板の上に、前記ワード線の下で且つ前記ワード線と実質
的に直交する方向に延びる導電膜がシールド絶縁膜を介
して形成され、この導電膜の電位を固定することによ
り、その電界によって前記素子分離領域における前記半
導体基板の表面の電位を固定するように構成されてい
る。In order to solve the above-mentioned problems, according to the present invention, in a nonvolatile semiconductor memory device in which each memory cell has a charge storage layer between a semiconductor substrate and a word line, the word line direction A conductive film extending below the word line and in a direction substantially orthogonal to the word line on the semiconductor substrate in the element isolation region for separating the memory cells adjacent to each other via the shield insulating film. By fixing the electric potential of the conductive film, the electric potential of the conductive film fixes the electric potential of the surface of the semiconductor substrate in the element isolation region.
【０００８】本発明の一態様においては、前記電荷蓄積
層が浮遊ゲートである。In one aspect of the present invention, the charge storage layer is a floating gate.
【０００９】本発明の別の一態様においては、前記電荷
蓄積層が、シリコン酸化膜の上に形成されたシリコン窒
化膜である。In another aspect of the present invention, the charge storage layer is a silicon nitride film formed on a silicon oxide film.
【００１０】本発明の不揮発性半導体記憶装置の製造方
法は、半導体基板の表面に第１の絶縁膜、導電膜及び第
２の絶縁膜を順次積層形成する工程と、前記導電膜及び
前記第２の絶縁膜をパターニングして、素子分離領域に
のみこれらの膜を残す工程と、全面に第３の絶縁膜を形
成した後、これを異方性エッチングして、パターニング
された前記導電膜及び前記第２の絶縁膜の側部にサイド
ウォールスペーサーを形成する工程と、前記導電膜、前
記第２の絶縁膜及び前記サイドウォールスペーサーによ
り分離された素子領域の前記半導体基板の上に第４の絶
縁膜であるトンネル絶縁膜を形成する工程と、前記トン
ネル絶縁膜の上に、浮遊ゲートとなる第１の多結晶シリ
コン膜を前記素子領域にそって延びるパターンに形成す
る工程と、前記第１の多結晶シリコン膜の上に第５の絶
縁膜を形成する工程と、全面に第２の多結晶シリコン膜
を形成した後、この第２の多結晶シリコン膜並びに前記
第５の絶縁膜及び前記第１の多結晶シリコン膜をパター
ニングして、前記素子領域において前記第１の多結晶シ
リコン膜にオーバーラップし、且つ、前記導電膜と実質
的に直交する方向に延びるワード線を形成する工程とを
有する。A method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of sequentially laminating a first insulating film, a conductive film and a second insulating film on a surface of a semiconductor substrate, the conductive film and the second insulating film. Patterning the insulating film to leave these films only in the element isolation regions, and forming a third insulating film on the entire surface, and then anisotropically etching this to form the patterned conductive film and the patterned conductive film. Forming a sidewall spacer on a side portion of the second insulating film, and forming a fourth insulating film on the semiconductor substrate in an element region separated by the conductive film, the second insulating film, and the sidewall spacer. Forming a tunnel insulating film that is a film, forming a first polycrystalline silicon film that serves as a floating gate on the tunnel insulating film in a pattern extending along the element region, and Forming the fifth insulating film on the polycrystalline silicon film, and after forming the second polycrystalline silicon film on the entire surface, the second polycrystalline silicon film, the fifth insulating film, and the Patterning the first polycrystalline silicon film to form a word line that overlaps the first polycrystalline silicon film in the device region and extends in a direction substantially orthogonal to the conductive film. Have.
【００１１】[0011]
【作用】本発明においては、素子分離領域の導電膜と第
２の絶縁膜とは、例えばリソグラフィ及びエッチングに
よりパターン形成することができるので、バーズビーク
による寸法シフトが生じず、且つ、熱処理による狭チャ
ネル効果は殆ど生じない。また、動作時に電位が固定さ
れるように構成された導電膜が電界をシールドするの
で、ワード線に高電圧が印加されても素子分離領域に寄
生チャネルが形成されることがない。In the present invention, since the conductive film in the element isolation region and the second insulating film can be patterned by, for example, lithography and etching, dimensional shift due to bird's beak does not occur and a narrow channel due to heat treatment is obtained. There is almost no effect. In addition, since the conductive film configured so that the potential is fixed during operation shields the electric field, a parasitic channel is not formed in the element isolation region even when a high voltage is applied to the word line.
【００１２】[0012]
【実施例】以下、本発明を浮遊ゲート型ＥＥＰＲＯＭに
適用した実施例を図１〜図８を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a floating gate type EEPROM will be described below with reference to FIGS.
【００１３】図１は、本実施例のＥＥＰＲＯＭメモリセ
ル部分の製造過程における概略斜視図であり、図２
（ａ）〜（ｄ）は、夫々、図１のＡ−Ａ線、Ｂ−Ｂ線、
Ｃ−Ｃ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 1 is a schematic perspective view in the manufacturing process of the EEPROM memory cell portion of this embodiment.
(A)-(d) are respectively AA line, BB line of FIG.
It is a longitudinal cross-sectional view along the CC line and the DD line.
【００１４】まず、その製造方法について、図３〜図８
を参照して説明する。なお、図３〜図８の各図におい
て、（ａ）〜（ｃ）は、夫々、各製造工程における平面
図並びに図１のＡ−Ａ線に沿った縦断面図及びＤ−Ｄ線
に沿った縦断面図である。First, the manufacturing method will be described with reference to FIGS.
Will be described with reference to. In each of FIGS. 3 to 8, (a) to (c) are plan views in each manufacturing process, a vertical sectional view taken along the line AA of FIG. 1 and a line D-D, respectively. FIG.
【００１５】まず、図３に示すように、Ｐ型のＳｉ基板
１１の表面に熱酸化法でＳｉＯ2 膜２１を形成する。そ
して、このＳｉＯ2 膜２１の上に、膜厚が３００ｎｍ程
度でＰ型又はＮ型の不純物をドープした多結晶Ｓｉ膜２
２と膜厚が５００ｎｍ程度のＳｉＯ2 膜等の絶縁膜２３
とをＣＶＤ法により順次堆積させる。しかる後、フォト
リソグラフィ及び異方性ドライエッチングにより、素子
分離領域において絶縁膜２３と多結晶Ｓｉ膜２２とを帯
状のパターンに残す。First, as shown in FIG. 3, a SiO 2 film 21 is formed on the surface of a P-type Si substrate 11 by a thermal oxidation method. Then, on the SiO 2 film 21, a polycrystalline Si film 2 having a film thickness of about 300 nm and doped with P-type or N-type impurities is formed.
2 and an insulating film 23 such as a SiO 2 film having a thickness of about 500 nm
And are sequentially deposited by the CVD method. Then, by photolithography and anisotropic dry etching, the insulating film 23 and the polycrystalline Si film 22 are left in a strip-shaped pattern in the element isolation region.
【００１６】次に、図４に示すように、ＣＶＤ法でＳｉ
Ｏ2 膜等の絶縁膜２４を全面に堆積させた後、この絶縁
膜２４を異方性ドライエッチングして、多結晶Ｓｉ膜２
２及び絶縁膜２３の側面に絶縁膜２４からなるサイドウ
ォールスペーサーを形成する。なお、この絶縁膜２４に
対する異方性ドライエッチングによって、基板表面に露
出した部分のＳｉＯ2 膜２１も除去される。Next, as shown in FIG. 4, Si is formed by the CVD method.
After depositing an insulating film 24 such as an O 2 film on the entire surface, the insulating film 24 is anisotropically dry-etched to obtain a polycrystalline Si film 2
2 and side walls of the insulating film 23 are formed with sidewall spacers made of the insulating film 24. By anisotropic dry etching of the insulating film 24, the portion of the SiO 2 film 21 exposed on the substrate surface is also removed.
【００１７】次に、図５に示すように、Ｓｉ基板１１の
素子領域の表面にトンネル酸化膜としてのＳｉＯ2 膜１
３を熱酸化法で形成してから、膜厚が１５０ｎｍ程度で
Ｎ型の不純物をドープした多結晶Ｓｉ膜１４をＣＶＤ法
で堆積させる。そして、フォトリソグラフィ及び異方性
ドライエッチングにより、素子領域を被覆する帯状のパ
ターンに多結晶Ｓｉ膜１４を加工する。更に、多結晶Ｓ
ｉ膜１４の表面に熱酸化法によりＳｉＯ2 膜１５を形成
する。Next, as shown in FIG. 5, a SiO 2 film 1 as a tunnel oxide film is formed on the surface of the element region of the Si substrate 11.
3 is formed by a thermal oxidation method, and then a polycrystalline Si film 14 having a film thickness of about 150 nm and doped with N-type impurities is deposited by a CVD method. Then, the polycrystalline Si film 14 is processed into a band-shaped pattern that covers the element region by photolithography and anisotropic dry etching. Furthermore, polycrystalline S
A SiO 2 film 15 is formed on the surface of the i film 14 by a thermal oxidation method.
【００１８】次に、図６に示すように、膜厚が３００ｎ
ｍ程度でＮ型の不純物をドープした多結晶Ｓｉ膜１６と
ＳｉＯ2 膜２５をＣＶＤ法で順次に全面に堆積させる。
そして、フォトリソグラフィ及び異方性ドライエッチン
グにより、ＳｉＯ2 膜２５、多結晶Ｓｉ膜１６、ＳｉＯ
2 膜１５、多結晶Ｓｉ膜１４及びＳｉＯ2 膜１３を、多
結晶Ｓｉ膜２２及び絶縁膜２３、２４の延びる方向に直
交するパターンにエッチングする。Next, as shown in FIG. 6, the film thickness is 300 n.
A polycrystalline Si film 16 doped with N-type impurities and a SiO 2 film 25 of about m are sequentially deposited on the entire surface by a CVD method.
Then, by photolithography and anisotropic dry etching, the SiO 2 film 25, the polycrystalline Si film 16, the SiO
The 2 film 15, the polycrystalline Si film 14 and the SiO 2 film 13 are etched in a pattern orthogonal to the extending direction of the polycrystalline Si film 22 and the insulating films 23 and 24.
【００１９】これにより、多結晶Ｓｉ膜１６で制御ゲー
ト、即ち、ワード線が形成されるとともに、多結晶Ｓｉ
膜１４で、メモリセル毎に分離された浮遊ゲートがワー
ド線に対して自己整合的に形成される。一方、ワード線
が形成されなかった領域では、素子分離領域を構成する
多結晶Ｓｉ膜２２及び絶縁膜２３、２４とこれらの下の
ＳｉＯ2 膜２１とが残されるのみで、素子領域が露出す
る。そこで、ＳｉＯ2膜２５や絶縁膜２３、２４等をマ
スクにしてＳｉ基板１１にＮ型の不純物を導入し、ソー
ス拡散層２６及びドレイン拡散層２７を形成する。この
状態が、図１及び図２に示す状態である。As a result, a control gate, that is, a word line is formed by the polycrystalline Si film 16, and the polycrystalline Si film 16 is formed.
In the film 14, floating gates separated for each memory cell are formed in self alignment with the word lines. On the other hand, in the region where the word line is not formed, only the polycrystalline Si film 22 and the insulating films 23 and 24 forming the element isolation region and the SiO 2 film 21 thereunder are left, and the element region is exposed. . Therefore, N-type impurities are introduced into the Si substrate 11 using the SiO 2 film 25, the insulating films 23, 24, etc. as a mask to form the source diffusion layer 26 and the drain diffusion layer 27. This state is the state shown in FIGS. 1 and 2.
【００２０】次に、図７に示すように、ＳｉＯ2 膜等の
絶縁膜２８をＣＶＤ法により全面に堆積させた後、この
絶縁膜２８を異方性ドライエッチングして、ＳｉＯ2 膜
２５及びその下の多結晶Ｓｉ膜１６の側面に絶縁膜２８
からなるサイドウォールスペーサーを形成する。しかる
後、スパッタ法でＷＳｉ膜を全面に堆積させ、このＷＳ
ｉ膜をフォトリソグラフィ及び異方性ドライエッチング
でパターニングして、ワード線の方向に並んでいるソー
ス拡散層２６を結ぶソース線としてのＷＳｉ配線３１を
形成するとともに、各メモリセルのドレイン拡散層２７
にコンタクトするドレインパッドとしてのＷＳｉ膜３２
を形成する。その後、ＳｉＯ2 膜等の層間絶縁膜３３を
ＣＶＤ法により全面に堆積させる（但し、図７（ａ）で
は、層間絶縁膜３３を図示省略した。）。Next, as shown in FIG. 7, after an insulating film 28 such as a SiO 2 film is deposited on the entire surface by a CVD method, this insulating film 28 is anisotropically dry-etched to form the SiO 2 film 25 and The insulating film 28 is formed on the side surface of the polycrystalline Si film 16 under the insulating film 28.
To form a sidewall spacer. After that, a WSi film is deposited on the entire surface by a sputtering method, and this WS
The i film is patterned by photolithography and anisotropic dry etching to form a WSi wiring 31 as a source line connecting the source diffusion layers 26 arranged in the direction of the word line and a drain diffusion layer 27 of each memory cell.
Film 32 as a drain pad that contacts the
To form. After that, an interlayer insulating film 33 such as a SiO 2 film is deposited on the entire surface by the CVD method (however, the interlayer insulating film 33 is not shown in FIG. 7A).
【００２１】次に、図８に示すように、フォトリソグラ
フィ及び異方性ドライエッチングにより、ドレインパッ
ドであるＷＳｉ膜３２に達するコンタクト孔３４を層間
絶縁膜３３に開口する（但し、図８（ａ）では、便宜
上、層間絶縁膜３３を図示省略し、コンタクト孔３４の
位置のみを破線で示す。）。そして、スパッタ法でＡｌ
膜を全面に堆積させ、このＡｌ膜をフォトリソグラフィ
及び異方性ドライエッチングでパターニングして、ワー
ド線の方向とは直交する方向に並んでいるＷＳｉ膜３２
を結ぶビット線としてのＡｌ配線３５を形成する。Next, as shown in FIG. 8, by photolithography and anisotropic dry etching, a contact hole 34 reaching the WSi film 32 which is a drain pad is opened in the interlayer insulating film 33 (however, in FIG. ), For convenience, the interlayer insulating film 33 is omitted in the drawing, and only the positions of the contact holes 34 are shown by broken lines. Then, Al is sputtered.
A film is deposited on the entire surface, the Al film is patterned by photolithography and anisotropic dry etching, and the WSi film 32 is lined up in the direction orthogonal to the word line direction.
An Al wiring 35 is formed as a bit line connecting the two.
【００２２】以上のようにして形成したＥＥＰＲＯＭメ
モリセルでは、その動作時、素子分離領域にある多結晶
Ｓｉ膜２２を接地電位に固定することにより、その上を
通るワード線に高電圧が印加された場合でも、それによ
り素子分離領域のＳｉ基板１１の表面の電位が変動し
て、そこに寄生チャネルが形成されることが防止され
る。In the EEPROM memory cell formed as described above, a high voltage is applied to the word line passing therethrough by fixing the polycrystalline Si film 22 in the element isolation region to the ground potential during its operation. Even in such a case, the potential of the surface of the Si substrate 11 in the element isolation region fluctuates and a parasitic channel is prevented from being formed there.
【００２３】以上に説明した実施例の製造方法では、Ｌ
ＯＣＯＳ法のように熱酸化によって膜厚の大きな酸化膜
を作る必要がないので、素子領域のＳｉ基板１１中の不
純物の横方向拡散に起因する狭チャネル効果を殆ど無視
することができる。In the manufacturing method of the embodiment described above, L
Since it is not necessary to form an oxide film having a large film thickness by thermal oxidation as in the OCOS method, the narrow channel effect caused by the lateral diffusion of impurities in the Si substrate 11 in the element region can be almost ignored.
【００２４】以上、本発明を浮遊ゲート型のＥＥＰＲＯ
Ｍに適用した実施例を説明したが、本発明は、Ｓｉ基板
の素子領域にＳｉＯ2 膜とＳｉＮ膜とを順次形成し、Ｓ
ｉＯ2 膜との界面部分のＳｉＮ膜に電荷を蓄積するＭＮ
ＯＳ型の不揮発性半導体記憶装置にもほぼ同様にして適
用することができる。As described above, the present invention is applied to the floating gate type EEPRO.
Although the embodiment applied to M has been described, in the present invention, the SiO 2 film and the SiN film are sequentially formed in the element region of the Si substrate, and S
MN that accumulates charges in the SiN film at the interface with the iO 2 film
It can be applied to the OS type nonvolatile semiconductor memory device in almost the same manner.
【００２５】[0025]
【発明の効果】本発明による不揮発性半導体記憶装置
は、ＬＯＣＯＳ法のような寸法シフトや狭チャネル効果
を無視できるので、メモリセルをより微細化できるとと
もに、ワード線に高電圧が印加された場合でも素子分離
領域に寄生チャネルが形成されることを防止することが
できるので、その信頼性が高い。Since the nonvolatile semiconductor memory device according to the present invention can ignore the size shift and the narrow channel effect as in the LOCOS method, the memory cell can be further miniaturized and a high voltage is applied to the word line. However, since it is possible to prevent the formation of a parasitic channel in the element isolation region, its reliability is high.
【００２６】また、本発明による不揮発性半導体記憶装
置の製造方法は、素子分離構造を、トレンチを形成する
ことなく、例えばリソグラフィ及び薄膜のエッチングに
より形成することができるので、ＬＯＣＯＳ法とほぼ同
程度の簡易な工程で実施可能である。Further, in the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the element isolation structure can be formed by, for example, lithography and etching of a thin film without forming a trench, and therefore, it is substantially the same as the LOCOS method. Can be implemented in a simple process.
【図１】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の製造過程における概略斜視図であ
る。FIG. 1 is a floating gate type EEPR according to an embodiment of the present invention.
It is a schematic perspective view in the manufacturing process of an OM memory cell part.
【図２】図１のＡ−Ａ線、Ｂ−Ｂ線、Ｃ−Ｃ線及びＤ−
Ｄ線に沿った縦断面図である。2 is a line AA, a line BB, a line C-C and a line D- in FIG.
It is a longitudinal cross-sectional view along the D line.
【図３】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 3 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図４】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 4 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図５】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 5 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図６】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 6 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図７】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 7 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図８】本発明の一実施例による浮遊ゲート型ＥＥＰＲ
ＯＭメモリセル部分の一製造工程を示す平面図並びに図
１のＡ−Ａ線及びＤ−Ｄ線に沿った縦断面図である。FIG. 8 is a floating gate type EEPR according to an embodiment of the present invention.
FIG. 3 is a plan view showing one manufacturing process of the OM memory cell portion and a vertical cross-sectional view taken along the lines AA and DD of FIG. 1.
【図９】従来のＥＥＰＲＯＭメモリセル部分の縦断面図
である。FIG. 9 is a vertical sectional view of a conventional EEPROM memory cell portion.
【図１０】従来の別のＥＥＰＲＯＭメモリセル部分の縦
断面図である。FIG. 10 is a vertical cross-sectional view of another conventional EEPROM memory cell portion.
１１ Ｓｉ基板 １３、１５、２１、２５ ＳｉＯ2 膜 １４、１６、２２ 多結晶Ｓｉ膜 ２３、２４、２８ 絶縁膜 ２６ ソース拡散層 ２７ ドレイン拡散層 ３１ ＷＳｉ配線 ３２ ＷＳｉ膜 ３３ 層間絶縁膜 ３４ コンタクト孔 ３５ Ａｌ配線11 Si substrate 13, 15, 21, 25 SiO 2 film 14, 16, 22 Polycrystalline Si film 23, 24, 28 Insulating film 26 Source diffusion layer 27 Drain diffusion layer 31 WSi wiring 32 WSi film 33 Interlayer insulating film 34 Contact hole 35 Al wiring
Claims (4)
の間に電荷蓄積層を有する不揮発性半導体記憶装置にお
いて、 ワード線方向に隣接するメモリセル間を互いに分離する
ための素子分離領域における前記半導体基板の上に、前
記ワード線の下で且つ前記ワード線と実質的に直交する
方向に延びる導電膜がシールド絶縁膜を介して形成さ
れ、この導電膜の電位を固定することにより、その電界
によって前記素子分離領域における前記半導体基板の表
面の電位を固定するように構成されていることを特徴と
する不揮発性半導体記憶装置。1. A non-volatile semiconductor memory device in which each memory cell has a charge storage layer between a semiconductor substrate and a word line, and in the element isolation region for separating memory cells adjacent to each other in the word line direction from each other. A conductive film extending below the word line and in a direction substantially orthogonal to the word line is formed on the semiconductor substrate via a shield insulating film, and the electric field of the conductive film is fixed by fixing the potential of the conductive film. The non-volatile semiconductor memory device is configured to fix the potential of the surface of the semiconductor substrate in the element isolation region.
を特徴とする請求項１に記載の不揮発性半導体記憶装
置。2. The non-volatile semiconductor memory device according to claim 1, wherein the charge storage layer is a floating gate.
に形成されたシリコン窒化膜であることを特徴とする請
求項１に記載の不揮発性半導体記憶装置。3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage layer is a silicon nitride film formed on a silicon oxide film.
膜及び第２の絶縁膜を順次積層形成する工程と、 前記導電膜及び前記第２の絶縁膜をパターニングして、
素子分離領域にのみこれらの膜を残す工程と、 全面に第３の絶縁膜を形成した後、これを異方性エッチ
ングして、パターニングされた前記導電膜及び前記第２
の絶縁膜の側部にサイドウォールスペーサーを形成する
工程と、 前記導電膜、前記第２の絶縁膜及び前記サイドウォール
スペーサーにより分離された素子領域の前記半導体基板
の上に第４の絶縁膜であるトンネル絶縁膜を形成する工
程と、 前記トンネル絶縁膜の上に、浮遊ゲートとなる第１の多
結晶シリコン膜を前記素子領域にそって延びるパターン
に形成する工程と、 前記第１の多結晶シリコン膜の上に第５の絶縁膜を形成
する工程と、 全面に第２の多結晶シリコン膜を形成した後、この第２
の多結晶シリコン膜並びに前記第５の絶縁膜及び前記第
１の多結晶シリコン膜をパターニングして、前記素子領
域において前記第１の多結晶シリコン膜にオーバーラッ
プし、且つ、前記導電膜と実質的に直交する方向に延び
るワード線を形成する工程とを有することを特徴とする
不揮発性半導体記憶装置の製造方法。4. A step of sequentially stacking a first insulating film, a conductive film and a second insulating film on a surface of a semiconductor substrate, and patterning the conductive film and the second insulating film,
A step of leaving these films only in the element isolation region, and a third insulating film is formed on the entire surface and then anisotropically etched to form the patterned conductive film and the second conductive film.
A side wall spacer is formed on a side portion of the insulating film, and a fourth insulating film is formed on the semiconductor substrate in the element region separated by the conductive film, the second insulating film and the sidewall spacer. Forming a tunnel insulating film, forming a first polycrystalline silicon film to be a floating gate on the tunnel insulating film in a pattern extending along the element region, and forming the first polycrystalline film A step of forming a fifth insulating film on the silicon film, and a step of forming a second polycrystalline silicon film on the entire surface,
Patterning the polycrystalline silicon film, the fifth insulating film, and the first polycrystalline silicon film so as to overlap the first polycrystalline silicon film in the element region and substantially to the conductive film. Forming a word line extending in a direction orthogonal to each other, the method for manufacturing a non-volatile semiconductor memory device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27785593A JP3330700B2 (en) | 1993-10-08 | 1993-10-08 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27785593A JP3330700B2 (en) | 1993-10-08 | 1993-10-08 | Nonvolatile semiconductor memory device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07111319A true JPH07111319A (en) | 1995-04-25 |
| JP3330700B2 JP3330700B2 (en) | 2002-09-30 |
Family
ID=17589223
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011018941A (en) * | 2010-10-12 | 2011-01-27 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| KR101016335B1 (en) * | 2003-10-24 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of manufacturing a nonvolatile memory device |
-
1993
- 1993-10-08 JP JP27785593A patent/JP3330700B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101016335B1 (en) * | 2003-10-24 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of manufacturing a nonvolatile memory device |
| JP2011018941A (en) * | 2010-10-12 | 2011-01-27 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3330700B2 (en) | 2002-09-30 |
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