JP2000183193A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress leakage current and reverse tunneling failures from occurring by forming trenches in a Si substrate, so as to be adjacent to a conductive film and embedding an oxide film in the trenches to form a trench-structured element isolating film. SOLUTION: Rectangular-strip like element isolating films 32, having an oxide film embedded in trenches formed in a p-type Si substrate 31, are formed to define element regions. A floating gate 34 is disposed independently in each memory cell to enter into between the adjacent element isolating films 32 through a gate oxide film 33A on the Si substrate 31, a selective oxide film 35 on the floating gate 34 is formed through selective oxidation method so as to be thick at the center of the floating gate 34 and form a sharp edge 34A on the top of the floating gate 34. Hence, in the data erasing operation the electric field concentration is apt to occur at the end of the floating gate 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a device isolation film formed on a silicon substrate and a floating gate formed in an active region other than the device isolation film and disposed between adjacent device isolation films. The present invention relates to a nonvolatile semiconductor memory device having a control gate formed so as to overlap with the floating gate via a tunnel oxide film covering the floating gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
In d Programmable ROM), each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a memory cell transistor having a double gate structure,
Data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. And F-
Data is erased by extracting charges from the floating gate to the control gate by N-conduction (Fowler-Nordheim tunnelling).

FIG. 9 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
0 is a sectional view taken along line X2-X2. FIG. 1 shows a split gate structure in which a control gate is arranged alongside a floating gate.

[0006] LO is applied to the surface region of the P-type silicon substrate 1.
A plurality of element isolation films 2 made of a LOCOS oxide film formed selectively and thickly by a COS (Local Oxidation Of Silicon) method are formed in a strip shape, and an element region is partitioned.
A floating gate 4 is formed on a silicon substrate 1 so as to extend between adjacent element isolation films 2 via an oxide film 3A.
Is arranged. This floating gate 4 is arranged independently for each memory cell. The selective oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 by a selective oxidation method, and a sharp corner 4A (see FIG. 15) is formed at the end of the floating gate 4. I have. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation.

A control gate 6 is arranged on a silicon substrate 1 on which a plurality of floating gates 4 are arranged via a tunnel oxide film 3 integrated with the oxide film 3A corresponding to each column of the floating gates 4. Is done. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3A. The floating gate 4 and the control gate 6 are
The adjacent rows are arranged so as to be plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in a substrate region between the control gate 6 and a substrate region between the floating gates 4. The drain region 7 is formed between the control gate 6 and the device isolation film 2.
Are separated from each other, and the source region 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.

Then, on the control gate 6,
Aluminum wiring 10 is arranged via oxide film 9 in a direction crossing control gate 6. This aluminum wiring 10 is connected to drain region 7 through contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line. Further, aluminum wiring 10 connected to drain region 7 becomes a bit line.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed, and the resulting difference in the operating characteristics of each memory cell transistor is made to correspond to the stored data. ing.

The data write, erase, and read operations in the above nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, the potential of the control gate 6 is 2 V, the potential of the drain region 7 is 0.5 V, and the high potential of the source region 8 is 12 V. Then, between the control gate 6 and the floating gate 4 and between the floating gate 4 and the substrate (source region 8) are capacitively coupled (the capacitance between the control gate 6 and the floating gate 4 <the floating gate 4 and the substrate (source region 8). ) The capacity between),
Due to this capacitance coupling ratio, the potential of the floating gate 4 is raised to about 9 V, hot electrons generated near the drain region 7 are accelerated to the floating gate 4 side, and injected into the floating gate 4 through the oxide film 3A to write data. Done.

On the other hand, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, the charges (electrons) accumulated in the floating gate 4 are transferred from the FN (Fowler-Nor
The tunnel oxide film 3 is formed by conduction.
Is released to the control gate 6 to erase the data.

In the read operation, the potential of the control gate 6 is set at 4 V, and the drain region 7 is set at 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) are not injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows.

Hereinafter, a method for manufacturing such a nonvolatile semiconductor memory device will be described. 11 to 16, (a) is a plan view, (b) is a cross-sectional view along AA,
(C) is BB sectional drawing.

Referring to FIG. 11, an LO
The element isolation film 2 is formed by the COS method. That is, FIG.
As shown in FIG. 1B, a pad oxide film 21 and a pad polysilicon film 22 are formed on the silicon substrate 1, and the element isolation film 2 is formed by selective oxidation using the silicon nitride film 23 having an opening as a mask. . The pad polysilicon film 2
2 is not always necessary and may be omitted.

Next, as shown in FIG. 12, the pad oxide film 21 and the pad polysilicon film 22 are removed.

Subsequently, as shown in FIG. 13, a gate oxide film 3A is formed by thermally oxidizing the silicon substrate 1, a polysilicon film 24 is formed thereon, and a silicon nitride film 25 having an opening is formed. Form.

Next, as shown in FIG. 14, the polysilicon film 24 is selectively oxidized using the silicon nitride film 25 as a mask to form a selective oxide film 5.

Subsequently, as shown in FIG. 15, after the silicon nitride film 25 is removed, the polysilicon film 24 is etched using the selective oxide film 5 as a mask to form a sharp corner 4A.
Is formed.

After forming a tunnel oxide film 3 on the entire surface as shown in FIG. 16, a conductive film composed of a polysilicon film and a tungsten silicide film is formed and patterned to form a control gate 6. Incidentally, the control gate 6 may be a single-layer film made of a polysilicon film.

Hereinafter, although the description is omitted, FIGS.
The memory cell of the nonvolatile semiconductor memory device is formed by forming the source region 8 and the drain region 7 as shown in FIG.

[0020]

However, FIG.
As shown in FIG. 16B (partially enlarged view of FIG. 16B), the control gate 6 that covers the floating gate 4 running over the end of the element isolation film 2 is sharply pointed (see A in a dotted-line circle shown in FIG. 17). ), There is a problem that since the electric field concentration occurs at that portion, the breakdown voltage between the floating gate 4 and the control gate 6 is reduced, so that a so-called reverse tunneling failure easily occurs.

Another problem is that high alignment accuracy is required between the floating gate 4 and the element isolation film 2. That is, when a mask shift occurs between the element isolation film forming mask and the floating gate forming mask, the ends of the floating gates 4B do not overlap or become shallow on the element isolation film 2 (see FIG. 18). ).

In this case, for example, when a high voltage is applied to the source region 8 to increase the potential of the floating gate 4B during the above-described write operation, a leak current flows from the source region 8 to the drain region 7 as shown in FIG. The flow (see IL in the drawing) causes the problem that the potential of the floating gate 4B is not sufficiently increased and the writing operation becomes insufficient.

To cope with this, if the size of the floating gate is unnecessarily increased, a problem occurs that the floating gates come into contact with each other because the interval between the adjacent floating gates is narrow as shown in FIG. I do.

Therefore, the present invention provides a non-conductive semiconductor memory device which suppresses the occurrence of a leakage current due to a mask shift between a mask for forming an element isolation film and a mask for forming a floating gate, and a reverse tunneling failure. It is an object of the present invention to provide a manufacturing method thereof.

[0025]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and a nonvolatile semiconductor memory device according to the present invention comprises a groove 55 formed in a silicon substrate 31 of one conductivity type. Isolation film 3 having an oxide film embedded therein
2 is formed in an active region separated by the device isolation film 32 in a self-aligned manner so that an end portion of the device isolation film 32 coincides with an end of the device isolation film 32, and is disposed between adjacent device isolation films 32. A floating gate 34 having a sharp corner 34A at the top, a tunnel oxide film 33 covering the floating gate 34, and a region overlapping the floating gate 34 via the tunnel oxide film 33 are formed. The control gate 36, the floating gate 34 and the control gate 36
And source / drain regions 37 and 38 of the opposite conductivity type formed on the surface of the silicon substrate 31 adjacent to the silicon substrate 31.

Then, the manufacturing method is such that a gate oxide film 33A and a polysilicon film 52 are formed on the silicon substrate 31.
Is formed, a silicon nitride film 53 having an opening 53A is formed on the polysilicon film 52, and the polysilicon film 52 is selectively oxidized by a LOCOS method using the silicon nitride film 53 as a mask to form a selective oxide film. 35 is formed. Next, an opening 54A is formed on the silicon nitride film 53.
After the formation of the photoresist film 54 having a pattern, the selective oxide film 35 and the silicon nitride film 5 in a portion exposed under the opening 54A are formed using the photoresist film 54 as a mask.
3 is removed. Subsequently, after removing the photoresist film 54, the selective oxide film 35 and the silicon nitride film 5 are removed.
Using the mask 3 as a mask, the polysilicon film 52, the gate oxide film 33A and a part of the silicon substrate 31 in the region where the opening 54A was present are removed to form a groove 55. Next, after removing the silicon nitride film 53, a CVD oxide film is formed on the entire surface including the groove 55 by a CVD method.
By etching back the oxide film using wet etching, the CVD oxide film is buried in the groove 55 to form the element isolation film 32. Subsequently, the polysilicon film 52 is anisotropically etched using the selective oxide film 35 as a mask to form a floating gate 34 having a sharp corner 34A on the upper portion. A tunnel oxide film 33 is formed so as to cover 35. And forming a control gate 36 having a region overlapping with the floating gate 34 via the tunnel oxide film 33.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
FIGS. 2A and 2B are sectional views taken along the line X1-X1 of FIG.
It is 1-Y1 sectional drawing. This figure shows a split gate structure in which a control gate is arranged side by side so as to overlap a floating gate via a tunnel oxide film.

An oxide film is buried in a groove formed in a P-type silicon substrate 31 (a so-called trench structure).
A plurality of element isolation films 32 are formed in a strip shape to define an element region. Gate oxide film 33A on silicon substrate 31
Floating gate 34 is arranged so as to enter between adjacent element isolation films 32 through. This floating gate 34 is arranged independently for each memory cell. The selective oxide film 35 on the floating gate 34 is formed thick at the center of the floating gate 34 by a selective oxidation method, and a sharp corner 34A (see FIG. 7) is formed on the floating gate 34. As a result, electric field concentration is likely to occur at the end of the floating gate 34 during the data erasing operation.

On a silicon substrate 31 on which a plurality of floating gates 34 are arranged, floating gates 34
Of the control gate 3 via the tunnel oxide film 33 integrated with the gate oxide film 33A corresponding to each of the columns.
6 are arranged. The control gate 36 is arranged so that a part thereof overlaps the floating gate 34 and the remaining part is in contact with the silicon substrate 31 via the tunnel oxide film 33. The floating gate 34 and the control gate 36 are arranged such that adjacent rows are plane-symmetric with each other.

In the substrate region between the control gate 36 and the floating gate 34, N
A drain region 37 and a source region 38 are formed. The drain region 37 is surrounded by the element isolation film 32 between the control gates 36 and is independent from each other, and the source region 38 is continuous in the direction in which the control gate 36 extends. These floating gate 34, control gate 36, drain region 37 and source region 3
8 constitutes a memory cell transistor.

Then, an aluminum wiring 40 is arranged on the control gate 36 via an oxide film 39 in a direction crossing the control gate 36. This aluminum wiring 40 is connected to drain region 37 through contact hole 41. Each control gate 36 becomes a word line, and a source region 38 extending in parallel with the control gate 36 becomes a source line. Further, the aluminum wiring 40 connected to the drain region 37 becomes a bit line.

Hereinafter, a method for manufacturing a memory cell of such a nonvolatile semiconductor memory device will be described. 3A to 8, (a) is a plan view, (b) is an AA sectional view, and (c) is a BB sectional view.

First, in FIG. 3, a selective oxidation film 35 made of a thermal oxide film is formed on the silicon substrate 31 by selective oxidation by the LOCOS method. That is, as shown in FIG. 3B, after forming a gate oxide film 33A and a conductive polysilicon film 52 on the silicon substrate 31, the opening 5 is formed.
Using the silicon nitride film 53 having 3A as a mask, the polysilicon film 52 is selectively oxidized to form a selective oxide film 35.

Next, as shown in FIG. 4, a photoresist film 54 having an opening 54A on the silicon nitride film 53 is formed.
Is formed, and the photoresist film 54 is used as a mask to expose the portion of the selective oxide film 35 below the opening 54A.
Is removed using hydrofluoric acid or the like. Subsequently, after removing the silicon nitride film 53 in a portion exposed below the opening 54A, the photoresist film 54 is removed.

Then, as shown in FIG. 5, using the selective oxide film 35 and the silicon nitride film 53 as a mask, the polysilicon film 52 in the region where the opening 54A was present (corresponding to the element isolation region forming portion) and the gate oxide are formed. The groove 55 is formed by removing the film 33A and part of the surface of the silicon substrate 31.

Next, as shown in FIG. 6, after removing the silicon nitride film 53, the entire surface including the groove 55 is subjected to CVD.
An oxide film made of a TEOS film (Tetra Ethyl Ortho Silicate) or the like is formed by a method, and the oxide film is etched back by a predetermined amount to bury the oxide film in the groove 55 to form the element isolation film 32. In this etch-back step, the thermal oxide film forming the selective oxide film 35 and the element isolation film 3 are formed.
The wet etching is performed by utilizing the difference in the etching rate from the TEOS film constituting No. 2. That is, the etching rate ratio between the two is: thermal oxide film: TEOS film =
1: 2.5, the floating gate 34 and the substrate 3
1 (source region 38) and the capacitance coupling ratio between the capacitive coupling between the floating gate 34 and the control gate 36 (the floating gate 34).
In order to maintain the capacitance between the gate electrode and the control gate 36 <the capacitance between the floating gate 34 and the substrate 31 (source region 38), the TEOS film is formed without reducing the thickness of the selective oxide film 35 as much as possible. The element isolation film 32 is formed by leaving the oxide film in the groove 55 by utilizing the characteristic that the oxide film clogged in the groove by the wet etching is easily left.

Subsequently, as shown in FIG. 7, the polysilicon film 52 is anisotropically etched using the selective oxide film 35 as a mask to form a floating gate 34 having a sharp corner portion 34A on the upper portion. Thereby, as shown in FIGS. 1 and 7A, the floating gate 34 is arranged between the adjacent element isolation films 32 in a self-aligned manner.

Then, as shown in FIG. 8, after a tunnel oxide film 33 is formed on the entire surface, a conductive film composed of a polysilicon film and a tungsten silicide film is formed and patterned to form a control gate 36. As the tunnel oxide film 33, for example, a TEOS (Tetra Ethyl Ortho Silicate) film or an HTO
An oxide film formed by forming a CVD oxide film such as a (High Temperature Oxide) film and then thermally oxidizing the same is used. Further, the control gate 36 may be a single-layer film made of a polysilicon film.

Hereinafter, although not described, a source region 38 and a drain region 37 are formed as shown in FIGS. 1 and 2, and an oxide film 39 is formed on the control gate 36.
A contact hole 41 in the drain region 37 through
Is connected to the aluminum wiring 40, thereby forming a memory cell of the nonvolatile semiconductor memory device.

As described above, in the present invention, FIG.
Since the floating gate 34 and the element isolation film 32 are formed in a self-aligned manner as shown in FIG. The problem that the writing operation becomes insufficient due to the current flowing is solved.

Further, since the structure of the present invention is not a structure in which the floating gate 4 rides on the end of the element isolation film 2 as in the conventional structure (FIG. 15), the floating gate 4
The control gate 6 covering the gate is sharpened in a square shape, and the electric field concentration occurs at that point, so that the problem that the withstand voltage between the floating gate 4 and the control gate 6 is reduced and so-called reverse tunneling failure easily occurs is also solved. . In addition, since the floating gate 4 does not ride on the end of the element isolation film 2, flattening can be achieved.

[0043]

According to the present invention, a trench is formed in a silicon substrate so as to be adjacent to a conductive film serving as a floating gate, and an element isolation film having a trench structure is formed by burying an oxide film in the trench. As a result, since the floating gate and the element isolation film are formed in a self-aligned manner, high alignment accuracy between the floating gate and the element isolation film as in the related art is unnecessary, and the write operation is performed due to the flow of leak current. The problem of becoming insufficient can be solved.

Further, since the floating gate does not ride over the end of the element isolation film as in the conventional case, the control gate covering the floating gate is sharpened in an angular shape, and the electric field is concentrated at that portion, so that the floating gate is floating. The problem that the withstand voltage between the gate and the control gate is reduced and so-called reverse tunneling failure easily occurs can also be solved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a memory cell of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a partial sectional view of FIG.

FIG. 3 is a first diagram illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a second diagram showing the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a third diagram showing the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a fourth diagram showing the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 7 is a fifth diagram showing the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 8 is a sixth diagram illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the present invention.

FIG. 9 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 10 is a sectional view taken along line X2-X2 in FIG. 9;

FIG. 11 is a first diagram illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 12 is a second diagram illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 13 is a third diagram showing the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 14 is a fourth diagram showing the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 15 is a fifth diagram illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 16 is a sixth diagram illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device.

FIG. 17 is a diagram for explaining a conventional problem.

FIG. 18 is a diagram for explaining a conventional problem.

Continued on front page F-term (reference) 5F001 AA09 AA25 AA63 AB03 AC02 AC06 AC20 AD12 AD41 AD60 AE02 AE08 AF06 AF25 AG21 AG29 5F083 EP02 EP25 ER02 ER05 ER09 ER14 ER17 ER21 GA11 GA30 JA36 KA01 KA05 LA12 NA01 PR05 PR29

Claims (3)

[Claims] An element isolation film in which an oxide film is buried in a groove formed in a silicon substrate of one conductivity type; and an element isolation film in a self-aligned manner so that an end of the element isolation film coincides with the element isolation film. A floating gate formed in an active region separated by a film and having a sharp corner at an upper portion disposed between adjacent element isolation films; a tunnel oxide film covering the floating gate; A control gate formed to have a region overlapping the floating gate via a film; and a diffusion region of a reverse conductivity type formed on a surface of the silicon substrate adjacent to the floating gate and the control gate. A nonvolatile semiconductor memory device. 2. An element isolation film in which an oxide film is buried in a groove formed in a silicon substrate of one conductivity type, and said element isolation film is self-aligned so that an end of the oxide film is coincident with the element isolation film. A floating gate formed in an active region separated by a film and having a sharp corner at an upper portion disposed between adjacent element isolation films; a tunnel oxide film covering the floating gate; A control gate formed to have a region overlapping the floating gate via a film, and a diffusion region of a reverse conductivity type formed on a surface of the silicon substrate adjacent to the floating gate and the control gate. Forming a gate oxide film and a conductive film on the silicon substrate; and forming a gate oxide film and a conductive film on the silicon substrate. The silicon nitride film after forming a silicon nitride film having an opening in the mask the conductive film L
Forming a selective oxide film by selective oxidation by the OCOS method; and forming a photoresist film having an opening on the silicon nitride film and selecting a portion exposed under the opening using the photoresist film as a mask. Removing the oxide film and the silicon nitride film; and, after removing the photoresist film, using the selective oxide film and the silicon nitride film as a mask, the conductive film, the gate oxide film, and the silicon substrate in the region where the opening was present. Forming a groove by removing a part thereof; and, after removing the silicon nitride film, forming an oxide film on the entire surface including the groove and etching back the oxide film to bury the oxide film in the groove. Forming an element isolation film by etching the conductive film using the selective oxide film as a mask to form a floating gate having a sharp corner at the top. Forming a tunnel oxide film so as to cover the floating gate and the selective oxide film; and forming a control gate having a region overlapping the floating gate via the tunnel oxide film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 3. The selective oxide film is a thermal oxide film, and the element isolation film is a CVD oxide film formed by a CVD method.
3. The method according to claim 2, wherein the step of etching back the VD oxide film and burying the VD oxide film in the trench employs wet etching.