JP2000277634A - Nonvolatile semiconductor memory and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory which is advantageous for improving device characteristics. SOLUTION: This nonvolatile semiconductor memory is provided with a gate oxide film formed on a P-type silicon substrate 51 having source/drain regions 61 and 74, a floating gate 67 formed via the gate oxide film so as to be made adjacent to the both edge parts of the source region 61, a control gate 70 formed via the gate oxide film to be made adjacent to the floating gate 67 and the drain region 74, and an erasure gate 64 formed on the source region 61 so as to be made adjacent via a tunnel oxide film 62B to the floating gate 67.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor memory device capable of improving device characteristics and miniaturizing a split gate flash memory. An object of the present invention is to provide a manufacturing method thereof.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
In d Programmable ROM), each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In the case of such a memory cell transistor having a double gate structure,
Data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. And F-
Data is erased by extracting charges from the floating gate to the control gate by N-conduction (Fowler-Nordheim tunnelling).

FIGS. 6 and 7 are a plan view and a sectional view showing a memory cell portion of a nonvolatile semiconductor memory device having a floating gate. FIG. 1 shows a split gate structure in which a control gate is arranged alongside a floating gate.

[0006] LO is applied to the surface region of the P-type silicon substrate 1.
A plurality of element isolation films 2 (see FIG. 6) made of a LOCOS oxide film which is selectively thickened by a COS (Local Oxidation Of Silicon) method are formed in a strip shape, and an element region is partitioned. On a silicon substrate 1 via an oxide film 3A,
Floating gate 4 is arranged so as to straddle between adjacent element isolation films 2. This floating gate 4 is arranged independently for each memory cell. Further, the selective oxide film 5 on the floating gate 4 is formed thick at the center of the floating gate 4 by a selective oxidation method, and the end of the floating gate 4 is formed at an acute angle. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation.

A control gate 6 is arranged on a silicon substrate 1 on which a plurality of floating gates 4 are arranged via a tunnel oxide film 3 integrated with the oxide film 3A corresponding to each column of the floating gates 4. Is done. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3A. The floating gate 4 and the control gate 6 are
The adjacent rows are arranged so as to be plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in a substrate region between adjacent control gates 6 and a substrate region between adjacent floating gates 4. The drain region 7 is surrounded by the element isolation film 2 between the control gates 6 and is independent of each other.
Continue in the direction in which the control gate 6 extends.
These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.

Then, on the control gate 6,
Metal wiring 10 is arranged via oxide film 9 in a direction crossing control gate 6. This metal wiring 10
It is connected to the drain region 7 through the contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line. The metal wiring 10 connected to the drain region 7 becomes a bit line.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed, and the resulting difference in the operating characteristics of each memory cell transistor is made to correspond to the stored data. ing.

The data write, erase, and read operations in the above nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, the potential of the control gate 6 is 2 V, the potential of the drain region 7 is 0.5 V, and the high potential of the source region 8 is 12 V. Thus, by applying a high potential to the source region 8, the coupling ratio between the control gate 6 and the floating gate 4 and between the floating gate 4 and the source region 8 (capacity between the control gate 6 and the floating gate 4 <floating The potential of the floating gate 4 is raised to about 9 V by the capacitance between the gate 4 and the source region 8, and hot electrons generated near the drain region 7 are discharged from the floating gate 4.
Is accelerated to the side and injected into the floating gate 4 through the oxide film 3A to write data.

On the other hand, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, the charges (electrons) accumulated in the floating gate 4 are transferred from the FN (Fowler-Nor
The tunnel oxide film 3 is formed by conduction.
Is released to the control gate 6 to erase the data.

In the read operation, the potential of the control gate 6 is set at 4 V, and the drain region 7 is set at 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed under the floating gate 4 and the drain current (both the cell current and the read cell current) Say) does not flow. Conversely, charges (electrons) are applied to the floating gate 4.
Is not injected, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a drain current flows.

[0012]

In such a nonvolatile semiconductor memory device, data (erasing) is performed by extracting charges (electrons) accumulated in the floating gate 4 to the control gate 6. That is, the control gate 6 has a role of generating a read current at the time of the above read operation and serving as an erase gate.

Therefore, as described above, the thickness of the gate oxide film under the control gate 6 to which a high voltage is applied during the erasing operation cannot be made thin in order to ensure reliability. Therefore, the read current is low, especially at low voltages, and when the substrate concentration is increased to suppress punch-through, the threshold voltage must be relatively high, thereby increasing the write efficiency. There was a structural problem that it could not be done.

Furthermore, as shown in FIG. 8, during the read operation, the same word line (WL) as the selected memory cell is used.
There is also the danger that a so-called read disturb failure occurs, in which data in the unselected memory cell connected to 1) is erased.

Further, there is a problem that a high mask alignment accuracy is required between the floating gate 4 and the control gate 6, and there is a problem when further miniaturization is attempted.

Accordingly, it is an object of the present invention to provide a non-volatile semiconductor memory device having excellent device characteristics and forming a floating gate and a control gate by self-alignment, and a method of manufacturing the same.

[0017]

Therefore, a nonvolatile semiconductor memory device according to the present invention has a source memory as shown in FIG.
P-type silicon substrate 5 having drain regions 61 and 74
1, a floating gate 67 formed via the gate oxide film 53 so as to be adjacent to both ends of the source region 61, the floating gate 67 and the drain, respectively. A control gate 70 formed adjacent to the region 74 via the gate oxide film 69, and an erase gate formed on the source region 61 adjacent to the floating gate 67 via the tunnel oxide film 62B. 64 is provided.

1B, a first gate oxide film 53, a polysilicon film 54, a silicon oxide film 55, and a silicon nitride film 56 are formed on a P-type silicon substrate 51, as shown in FIG. After the formation, the resist 5 is etched using the mask as a mask to form the recess 5 reaching a part of the silicon nitride film 56, the oxide film 55 and the polysilicon film 54.
8 is formed. Next, as shown in FIG. 1C, after the resist film 57 is removed, the inside of the concave portion 58 is buried with a silicon oxide film 59. Subsequently, as shown in FIG. 2A, a resist film 60 having an opening on the source region formation region
After the formation of the resist film 60 and the oxide film 5
The polysilicon film 54 is patterned using the mask 9 as a mask, and an N-type impurity is ion-implanted to form the source region 6.
Form one. Further, as shown in FIG. 2B, after the resist film 60 is removed, the entire surface is subjected to a wet treatment to retreat the oxide film 59 on the polysilicon film 54, and a silicon oxide film 62 is formed on the entire surface. Next, as shown in FIG. 2C, the polysilicon film 5 is interposed through the oxide film 62.
The erase gate 64 is formed so as to be adjacent to the oxide film 4 and the oxide film 59A. Subsequently, as shown in FIGS. 3A and 3B, after forming a resist film 65 having an opening on the drain region forming region, the resist film 65 and the oxide film 59 are formed.
The silicon nitride film 56, the oxide film 55, and the polysilicon film 54 are patterned using the masks A (59B) and 62 as masks to form a floating gate 67 on which the oxide film 59B is laminated. Further, after a CVD oxide film is formed on the entire surface as shown in FIG. 3 (c), the CVD oxide film is anisotropically etched (formation of an oxide film 68), and then, as shown in FIG. Thermally oxidized to form second gate oxide film 6
9 is formed. Subsequently, after forming a conductive polysilicon film on the entire surface, the polysilicon film is anisotropically etched to form a control gate 70 on the side wall of the floating gate 67 via the oxide film 68, N-type impurities are ion-implanted into the entire surface, and a low-concentration N
A mold drain region 71 is formed. Further, as shown in FIG. 4B, a CVD oxide film is formed on the entire surface, and the CVD oxide film is anisotropically etched to form a sidewall insulating film 73. Then, N-type impurities are ion-implanted on the entire surface. Forming a high-concentration N-type drain region 74 in the surface layer of the substrate so as to be adjacent to the side wall insulating film 73.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First, as shown in FIG. 1A, an element isolation film 52 is formed on a semiconductor silicon substrate 51.
The element isolation film 52 may be formed by the LOCOS method, but in the present embodiment, the element isolation film 52 is formed by using the trench method. This trench element isolation film is formed by a well-known process. For example, the substrate 51 is thermally (gate) oxidized on the substrate 51 to about 80 ° to 150 °.
A first gate oxide film 53 having a thickness of Å is formed, and a polysilicon film 54 having a thickness of approximately 1500 上 is formed thereon. Then, the polysilicon film 54 is subjected to phosphorus doping using POCl ₃ as a thermal diffusion source. To make it conductive. Note that a conductive method in which N-type impurities such as phosphorus ions and arsenic ions are ion-implanted may be used. Next, a silicon oxide film having a thickness of about 200 ° is formed on the polysilicon film 54, a silicon nitride film having a thickness of about 500 ° is formed thereon, and the silicon nitride film is formed using a resist film as a mask. After the silicon oxide film, the polysilicon film 54, the silicon oxide film 53, and a portion of the substrate 51 are removed by etching to form a recess reaching the portion of the substrate 51, the silicon that completely fills the recess is formed. An oxide film (constituting the element isolation film 52) is formed on the entire surface. The polysilicon film 54 is polished using a CMP (Chemical Mechanical Polishing) method until the upper surface of the polysilicon film 54 is exposed.

FIGS. 1B to 5 used in the following description.
(B) is a cross-sectional view showing a formation region of the memory cell portion, which is used for describing a process of forming the memory cell portion in particular, as viewed from a direction perpendicular to the paper surface of FIG. is there.

Next, as shown in FIG. 1B, a silicon oxide film 55 having a thickness of about 200 ° is formed on the entire surface, a silicon nitride film 56 having a thickness of about 4000 ° is formed thereon, and a resist film is formed. Using the mask 57 as a mask, a part of the silicon nitride film 56, the silicon oxide film 55, and the polysilicon film 54 is removed by etching to form a concave portion 58 that reaches a part of the polysilicon film 54. Then, the resist film 5
7 is removed, a silicon oxide film is formed on the entire surface only to completely embed the recess 58, and the entire surface is polished by the CMP method, so that the inside of the recess 58 is
(See FIG. 1 (c)).

Subsequently, as shown in FIG. 2A, a resist film 60 is formed, and the silicon nitride film 56 is isotropically etched using the resist film 60 as a mask. The film 54 is anisotropically etched. In this step, the polysilicon films 54 for forming the floating gates constituting the adjacent memory cells described later are separated from each other. Subsequently, ion implantation of N-type impurities such as phosphorus ions and arsenic ions forms source regions 61 in the surface layer of the substrate between the adjacent floating gates 67. The source region 61 becomes a source / drain region by diffusion of ions in a later annealing step together with a drain region described later, but is described here for convenience.

Further, as shown in FIG. 2B, the entire surface is treated with hydrofluoric acid to retreat the silicon oxide film 59 on the polysilicon film 54 (refer to the silicon oxide film 59A), and to sharpen the polysilicon film 54. After exposing the portion 54A, a CVD silicon oxide film (for example, HTO (High Temperature Oxi
de) film and TEOS (Tetra Ethyl Ortho Silicate) film 62). The silicon oxide film 62
Becomes a tunnel oxide film 62B described later. Further, the tunnel oxide film 62B may be formed of a CVD silicon oxide film and a thermal oxide film by performing thermal oxidation after forming the CVD silicon oxide film. Further, the sharp portion 54
Due to the presence of A, when electric charges (electrons) stored in the floating gate 67 to be described later are extracted to the erase gate 64 (during data erase operation), the electric field concentration easily occurs at the sharp portion 54A, and the erase efficiency is reduced. improves.

Subsequently, as shown in FIG. 2C, a conductive polysilicon film is formed so that the recess 63 between the adjacent floating gates 67 is completely buried, and then the entire surface is formed by the CMP method. By polishing, the concave 6
3 is buried by an erase gate 64 made of a polysilicon film. Then, after forming a resist film 65 so as to completely cover at least the erase gate 64 (see FIG. 3A), the resist film 65 is formed on the side of the silicon oxide film 59 using the resist film 65 as a mask. The silicon nitride film 56 is isotropically etched.

Next, as shown in FIG. 3B, the entire surface is treated with hydrofluoric acid to form a silicon oxide film 55 on the polysilicon film 54.
Is removed and the silicon oxide films 59A and 62A are retracted to form silicon oxide films 59B and 62A.
Further, using the resist film 65 as a mask, the polysilicon film 54 is used.
The floating gate 6 by anisotropically etching
7 is formed. By this etching step, a part of the silicon oxide film 53 is also removed (see the silicon oxide film 53A). In addition, it may be completely removed by etching.

Subsequently, as shown in FIG.
After forming a silicon oxide film having a thickness of about 400 ° by the VD method, the silicon oxide film is etched back to form the floating gate 67 and the silicon oxide film 59B.
The silicon oxide film 6 is left only on the side wall of the laminated portion of
8 is formed. By this etch back step, the silicon oxide film 53A is completely removed.

Further, as shown in FIG. 4A, the entire surface is thermally (gate) oxidized to form a second gate oxide film 69 having a thickness of about 50 °, on which a conductive film having a thickness of about 4000 ° is formed. After forming the modified polysilicon film, the polysilicon film is anisotropically etched to form a control gate 70 on the side wall of the silicon oxide film 68. Thereafter, a resist film (not shown) is formed so as to completely cover the erase gate 64, and the polysilicon film for forming the control gate is removed by etching using the resist film as a mask, thereby forming adjacent memory cells. Control gate 70 is completely separated.

Subsequently, a low concentration drain region 71 is formed in the surface layer of the substrate adjacent to the control gate 70 by ion-implanting N-type impurities such as phosphorus ions or arsenic ions into the entire surface. Further, as shown in FIG. 4B, after a silicon oxide film having a thickness of about 1500 ° is formed on the entire surface by the CVD method, this silicon oxide film is etched back to leave a residual film only on the side wall of the control gate 70. Thus, the sidewall insulating film 73 is formed. At this time, the thickness of the silicon oxide film or the amount of the etch back is adjusted so that the upper portion of the control gate 70 is exposed, so that the gate oxide on the formation position of the high-concentration drain region 74 described later is formed. While removing the film 69, the silicon oxide film formed on the erase gate 64 during the gate oxidation is also removed.

Then, N-type impurities such as phosphorus ions and arsenic ions are ion-implanted into the entire surface to form a high-concentration drain region 74 in the surface layer of the substrate so as to be adjacent to the side wall insulating film 73. It becomes a drain region.

Next, as shown in FIG. 4C, a metal film as a film to be silicided, for example, a titanium (Ti) film is formed on the entire surface by sputtering, and then the titanium film is deposited and heat-treated (Rapid Thermal. Annealing, hereinafter referred to as RTA) is performed to form a silicide, and the unreacted titanium film on the side wall insulating film 73 and the silicon oxide film 59B is removed to thereby form the drain region 74, the control gate 70, and the erase gate. The titanium silicide (TiSi ₂ ) films 75 and 7 are selectively and self-aligned on
6,77 are formed. The RTA process is performed in two steps so that excessive silicidation does not proceed. That is, the first RTA process is performed at about 650 ° C. to 700 ° C.
Then, the second RTA process is performed at about 750 ° C. to 850 ° C. for about 10 to 45 seconds. The titanium silicide (TiSi ₂ ) films 75, 76, 77 formed on the drain region 74, the control gate 70, and the erase gate 64 reduce the resistance.

Then, as shown in FIG. 5A, after an interlayer insulating film 78 made of a BPSG film is formed on the entire surface, a contact hole 79 is formed on the drain region 74 so as to make contact therewith. A contact plug (made of, for example, a tungsten film) 80 is formed via a not-shown barrier metal film (for example, a laminated film of a titanium film and a titanium nitride (TiN) film), and a metal is formed on the contact plug 80. The film 81 (for example, A
1, Al-Si, Al-Cu, Al-Si-Cu, etc.) to form metal wiring. In addition, for example, Al, Al-Si, Al-C
A metal wiring made of u, Al-Si-Cu or the like may be formed.

Through the above steps, a nonvolatile semiconductor memory device is formed. FIG. 5B is a plan view showing each component of the memory cell of FIG. 5A for convenience sake.

The operations of writing, erasing and reading data in the above nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, for example, the potential of the control gate 70 is 1 V, the potential of the drain region 74 is 0.5 V, and the potential of the source region 61 is 10 V. Thus, by applying a high potential to the source region 61, the coupling ratio between the control gate 70 and the floating gate 67 and between the floating gate 67 and the substrate (source region 61) (between the control gate 70 and the floating gate 67). (Capacity <capacitance between floating gate 67 and source region 61), the potential of floating gate 67 is 9 V
Hot electrons generated near the drain region 74 are accelerated toward the floating gate 67 and injected into the floating gate 67 through the gate oxide film 53 to write data.

On the other hand, in the erase operation, for example, the drain region 74, the source region 61, the control gate 7
The potential of 0 and the substrate is set to 0V, and the potential of the erase gate 64 is set to 14V. At this time, the floating gate 6
The potential of 7 is attracted to a potential close to 0 V because the capacitance between the floating gate 67 and the substrate and the source region 61 is large. As a result, charges (electrons) accumulated in the floating gate 67 are transferred from the sharp portion 54A of the floating gate 67 to the FN (Fowler-N).
The data is erased by passing through the tunnel oxide film 62B and discharged to the control gate 70 due to conduction.

In the read operation, for example, the potential of the control gate 70 is set to 1.5 V, the drain region 74 is set to 1 V, and the potentials of the source region 61 and the erase gate 64 are set to 0 V. If charges (electrons) are injected into the floating gate 67 at this time, the potential of the floating gate 67 becomes low, so that no channel is formed below the floating gate 67 and a drain current (cell current or read cell Also called current)
Does not flow. Conversely, if charges (electrons) have not been injected into the floating gate 67, the potential of the floating gate 67 increases, so that the floating gate 6
A channel is formed under 7 and a drain current flows.

Here, when the features of the present invention are arranged, a cell (readout) which also served as an erase gate in the conventional structure was used.
By forming the erase gate 64 dedicated to erasing in place of the current control gate 6, a high voltage is not applied to the control gate during the erasing operation, and the thickness of the gate oxide film 69 thereunder (the gate oxide The film 69 <the gate oxide film 53 under the floating gate 67 <the gate oxide film 53 under the erase gate 64 + the tunnel oxide film 62B) can be set to an appropriate film thickness, and the read current generation efficiency is improved as compared with the conventional configuration. be able to. Therefore, it is also effective, for example, in the case of multi-value conversion. Further, the threshold voltage is relatively low, and the electric field between the control gate 70 and the floating gate 67 during the write operation can be increased. Therefore, the write efficiency is high and the structure is advantageous for low voltage operation.

Furthermore, since the control gate 70 and the erase gate 64 are separately formed, the control gate 70 and the erase gate 64 are connected to the same word line (WL1) as the selected memory cell, which is generated during the conventional read operation. It is possible to avoid the danger of a so-called read disturb defect in which data in a selected memory cell is erased. Therefore, the thickness of the tunnel oxide film 62B can be reduced, and the ratio of charges (electrons) trapped in the tunnel oxide film 62B during the erasing operation decreases in proportion to the film thickness. Can be done.

Since the erase gate 64, floating gate 67, and control gate 70 can be formed in a self-aligned manner, the configuration is advantageous for miniaturization.

Since the device isolation film 52 is formed by burying a silicon oxide film by a CVD method in a concave portion formed by shaving a part of the substrate 51, the device isolation film 52 is compared with a conventional device isolation film by a LOCOS method. Since a thick device isolation film can be formed in a shorter device isolation region, device isolation capability is improved.

[0041]

According to the present invention, the formation of the erasing-dedicated gate eliminates the application of a high voltage to the control gate during the erasing operation, and sets the thickness of the underlying gate oxide to an appropriate thickness. As a result, the read current can be increased.

Since the threshold voltage is relatively low, the writing efficiency is high and the structure is advantageous for low voltage operation.

Further, it is possible to suppress the occurrence of the read disturb defect which has occurred during the read operation in the conventional configuration.

Since the erase gate, floating gate and control gate can be formed in a self-aligned manner, the configuration is advantageous for miniaturization.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a non-volatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a non-volatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a non-volatile semiconductor memory device according to one embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing the non-emissive semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is a diagram illustrating a method of manufacturing the non-emissive semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a plan view showing a conventional non-volatile semiconductor memory device.

FIG. 7 is a cross-sectional view showing a conventional non-volatile semiconductor memory device.

FIG. 8 is a diagram for explaining a problem of a conventional non-volatile semiconductor memory device.

Continued on the front page F term (reference) 5F001 AA21 AA32 AA33 AB03 AB06 AB30 AC02 AC61 AD12 AD41 AD51 AD62 AE02 AE03 AE08 AF10 5F083 EP15 EP25 EP30 ER02 ER05 ER09 ER14 ER18 ER21 GA01 GA05 GA19 GA30 JA35 JA05 MA06 MA05 NA02

Claims (6)

[Claims] 1. A nonvolatile semiconductor memory device having a floating gate and a control gate on a semiconductor substrate having first and second diffusion regions, wherein the floating gates of adjacent memory cells are connected via a tunnel oxide film. A nonvolatile semiconductor memory device comprising an erase gate formed so as to be adjacent to the nonvolatile semiconductor memory device. 2. The semiconductor device according to claim 1, wherein said first and second gate oxide films are formed on a semiconductor substrate having first and second diffusion regions, and said first and second gate oxide films are adjacent to both ends of said first diffusion region. A floating gate formed on the first gate oxide film; a control gate formed on the second gate oxide film so as to be adjacent to the floating gate and the second diffusion region; A non-volatile semiconductor memory device, comprising: an erase gate formed on the first diffusion region so as to be adjacent via a film. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a sharp portion is formed on the floating gate toward the erase gate. 4. The nonvolatile semiconductor memory according to claim 1, wherein said control gate and said erase gate are made of a polysilicon film at least partially silicided. apparatus. 5. A method according to claim 5, wherein a first oxide film, a polysilicon film, a second oxide film and a silicon nitride film are formed on a semiconductor substrate of one conductivity type and then etched using a resist film as a mask. Forming a recess reaching a part of the oxide film and the polysilicon film of Step 2; filling the recess with a third oxide film after removing the resist film; and forming a first diffusion region forming region. Forming a resist film having an opening thereon and then patterning the polysilicon film using the resist film and the third oxide film as a mask; and using the resist film and the third oxide film as a mask, Forming a first reverse-conductivity-type diffusion region in the substrate surface adjacent to the polysilicon film by ion-implanting a reverse-conductivity-type impurity, and removing the entire surface after removing the resist film. A step of recessing the third oxide film on the polysilicon film by performing an etching process; and forming a CVD oxide film on the entire surface and adjoining the polysilicon film and the third oxide film via the CVD oxide film. Forming an erase gate as described above, forming a resist film having an opening on the second diffusion region forming region, and then using the resist film and the third oxide film as a mask to form the silicon nitride film and the second Patterning an oxide film and a polysilicon film to form a floating gate on which a third oxide film is laminated; forming a CVD oxide film on the entire surface; and then anisotropically etching the CVD oxide film to form a fourth gate. Forming a fifth oxide film by thermally oxidizing the surface layer of the substrate after forming the oxide film; and forming an electrically conductive polysilicon film on the entire surface and then anisotropically etching the polysilicon film. Forming a control gate on the side wall portion of the floating gate via the fourth oxide film, and ion-implanting a reverse conductivity type impurity into the entire surface to form a control gate on the surface of the substrate adjacent to the control gate. Forming a low concentration second reverse conductivity type diffusion region; forming a CVD oxide film on the entire surface; anisotropically etching the CVD oxide film to form a sidewall insulating film; Forming a high-concentration second reverse conductivity type diffusion region in the surface layer of the substrate so as to be adjacent to the side wall insulating film by ion-implanting an impurity. . 6. A method for forming a first oxide film, a polysilicon film, a second oxide film and a silicon nitride film on a semiconductor substrate of one conductivity type and etching the silicon nitride film using a resist film as a mask. Forming a recess reaching a part of the oxide film and the polysilicon film of Step 2; filling the recess with a third oxide film after removing the resist film; and forming a first diffusion region forming region. Forming a resist film having an opening thereon and then patterning the polysilicon film using the resist film and the third oxide film as a mask; and using the resist film and the third oxide film as a mask, Forming a first reverse-conductivity-type diffusion region in the substrate surface adjacent to the polysilicon film by ion-implanting a reverse-conductivity-type impurity, and removing the entire surface after removing the resist film. A step of recessing the third oxide film on the polysilicon film by performing an etching process; and forming a CVD oxide film on the entire surface and adjoining the polysilicon film and the third oxide film via the CVD oxide film. Forming an erase gate as described above, forming a resist film having an opening on the second diffusion region forming region, and then using the resist film and the third oxide film as a mask to form the silicon nitride film and the second Patterning an oxide film and a polysilicon film to form a floating gate on which a third oxide film is laminated; forming a CVD oxide film on the entire surface; and then anisotropically etching the CVD oxide film to form a fourth gate. Forming a fifth oxide film by thermally oxidizing the surface layer of the substrate after forming the oxide film; and forming an electrically conductive polysilicon film on the entire surface and then anisotropically etching the polysilicon film. Forming a control gate on the side wall portion of the floating gate via the fourth oxide film, and ion-implanting a reverse conductivity type impurity into the entire surface to form a control gate on the surface of the substrate adjacent to the control gate. Forming a low concentration second reverse conductivity type diffusion region; forming a CVD oxide film on the entire surface; anisotropically etching the CVD oxide film to form a sidewall insulating film; A step of ion-implanting an impurity to form a high-concentration second reverse conductivity type diffusion region in the surface layer of the substrate so as to be adjacent to the side wall insulating film; Forming a silicide film on the high concentration second reverse conductivity type diffusion region, the control gate and the erase gate. Construction method.