KR100276542B1 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

This invention suppresses generation | occurrence | production of the defect resulting from the mask shift | offset between the mask for element isolation film formation and the mask for floating gate formation.

A nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention are formed in an element isolation film 2 formed on a silicon substrate 1 of one conductivity type and in an active region other than the element isolation film 2, Floating gate 34 having a sharp corner at an upper portion disposed in the narrow space of the adjacent device isolation film 2, a tunnel oxide film covering the floating gate 34, and one end of the floating gate 34 through the tunnel oxide film A control gate 36 formed so as to overlap in floating, the floating gate 34 and the drain region 37 of the reverse conductivity type formed on the surface of the silicon substrate 1 adjacent to the control gate 36, the source region (38) is provided.

Description

Nonvolatile semiconductor memory device and manufacturing method therefor {NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a device isolation film formed on a silicon substrate and an active region other than the device isolation film, which is formed in the narrow space of the device isolation film adjacent to each other, and through the tunnel oxide film covering the floating gate. A nonvolatile semiconductor memory device having a control gate formed overlying a phase and a manufacturing method thereof.

In an electrically erasable nonvolatile semiconductor memory device in which a memory cell is a single transistor, in particular, an electrically erasable and programmable ROM (EEPROM), each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. Is formed. In a memory cell transistor having such a double gate structure, data is written by accelerating and injecting photoelectrons generated at the drain region side of the floating gate into the floating gate. Then, data is erased by extracting charge from the floating gate to the control gate by F-N conduction (Fowler-Nordheim tunneling).

8 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, and FIG. 9 is a cross-sectional view of the X2-X2 line thereof. In this figure, the split gate structure in which the control gate is arranged in parallel with the floating gate is shown.

In the surface region of the P-type silicon substrate 1, an element isolation film 2 made of a LOCOS oxide film selectively formed by LOCOS (Local Oxidation of Silicon) method is formed in a rectangular shape, and the element region is partitioned. On the silicon substrate 1, the floating gate 4 is arrange | positioned through the oxide film 3A so that it may span between the adjacent element isolation films 2. This floating gate 14 is arranged independently for each memory cell. In addition, the selective oxide film 5 on the floating gate 14 is thickly formed at the center of the floating gate 4 by the selective oxidation method to sharpen the end portion of the floating gate 4. As a result, electric field concentration is likely to occur at the end of the floating gate 4 during the data erasing operation.

On the silicon substrate 1 on which the plurality of floating gates 4 are arranged, the control gate 6 is provided through the tunnel oxide film 3 integrated with the oxide film 3A corresponding to each column of the floating gate 4. Is placed. This control gate 6 is disposed so that a part thereof overlaps on the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3A. In addition, these floating gate 4 and the control gate 6 are arrange | positioned so that the mutually adjacent columns may surface-symmetrically mutually.

An N-type drain region 7 and a source region 8 are formed in the substrate region between the control gate 6 and the substrate region between the floating gate 14. The drain region 7 is surrounded by the element isolation film 2 between the control gates 6 and is independent of each other, and the source region 8 is continuous in the extending direction of the control gate 6. These floating gates 4, the control gate 6, the drain region 7 and the source region 8 constitute a memory cell transistor.

Then, on the control gate 6, the aluminum wiring 10 is disposed in the direction crossing the control gate 6 via the oxide film 9. The aluminum wiring 10 is connected to the drain region 7 through the contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line. In addition, the aluminum wiring 10 connected to the drain region 7 becomes a bit line.

In the case of such a double gate structure memory cell transistor, the on-resistance value between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting electric charge into the floating gate 4, the on-resistance value of a specific memory cell transistor is varied, and the data corresponding to the data storing the difference in the operating characteristics of each of the memory cell transistors thus generated is changed.

Each operation of writing, erasing, and reading data in the nonvolatile semiconductor memory device described above is performed as follows, for example. In the write operation, the potential of the control gate 6 is 2V, the potential of the drain region 7 is 0.5V, and the high potential of the source region is 12V. Thus, by applying the high potential to the source region 8, the potential of the floating gate 14 can be increased to about 9V by the coupling ratio between the source region 8 and the floating gate 4, and the drain region 7 Hot electrons generated in the vicinity are accelerated toward the floating gate 4 side and injected into the floating gate 4 through the oxide film 3A to write data.

In the erase operation, on the other hand, the potentials of the drain region 7 and the source region 8 are set to 0V, and the control gate 6 is set to 14V. As a result, charges (electrons) accumulated in the floating gate 4 pass through the tunnel oxide film 3 by Fowler-Nordheim tunnelling (FN) conduction at an acute angle of each portion of the floating gate 14 to control gate 6. ) To erase the data.

In the read operation, the potential of the control gate 6 is 4V, the drain region 7 is 2V, and the source region 8 is 0V. At this time, when charge (electrons) are injected into the floating gate 4, the potential of the floating gate 14 is lowered, so that no tunnel is formed under the floating gate 4, and drain charges do not flow. On the contrary, when charge (electron) is not injected into the floating gate 4, the charge of the floating gate 4 increases, so that a channel is formed under the floating gate 4, and a drain current flows.

Hereinafter, a method of manufacturing such a nonvolatile semiconductor memory device will be described. 10-15, (a) is a top view, (b) is A-A sectional drawing, (c) is B-B sectional drawing.

In Fig. 10, the element isolation film 2 is formed on the silicon substrate 1 by the LOCOS method. That is, as shown in Fig. 10B, a pad oxide film 21 and a pad polysilicon film 22 are formed on the silicon substrate 1, and a silicon nitride film 23 having an opening is used as a mask. Selective oxidation is performed to form the element isolation film 2. In addition, since the pad polysilicon film 22 is not necessarily required, you may abbreviate | omit.

Next, as shown in FIG. 11, the pad oxide film 21 and the pad polysilicon film 22 are removed.

Subsequently, as shown in FIG. 12, the gate oxide film 3A is formed by thermally oxidizing the silicon substrate 1, and after the polysilicon film 24 is formed thereon, the silicon nitride film 25 having an opening is formed. Form.

Next, as illustrated in FIG. 13, the polysilicon film 24 is selectively oxidized using the silicon nitride film 25 as a mask to form a selective oxide film 5.

Subsequently, after removing the silicon nitride film 25 as shown in FIG. 14, the polysilicon film 24 is etched using the selective oxide film 5 as a mask to form the floating gate 14.

After the tunnel oxide film 3 is formed on the entire surface as shown in FIG. 15, a conductive film made of a polysilicon film and a tungsten silicide film is formed and patterned to form the control gate 6. However, the control gate 6 may be a single layer film made of a polysilicon film.

Hereinafter, although description is abbreviate | omitted, as shown to FIG. 8 and FIG. 9, the source area | region 8 and the drain area | region 7 are formed, and the memory cell of a nonvolatile semiconductor memory device is formed.

However, as shown in FIG. 16 (partially enlarged view of FIG. 15B), the control gate 6 covering the floating gate 4 placed on the end of the device isolation film 2 is sharp in an angular shape. (See A in the dotted line circle shown in Fig. 16), since electric field concentration occurs at the portion, the internal pressure between the floating gate 4 and the control gate 6 is lowered, so that a so-called reverse tunneling failure is likely to occur. There was a challenge.

In addition, there has been a problem that a high bonding density is required between the floating gate 4 and the device isolation film 2. That is, when a mask shift occurs between the element isolation formation mask and the floating gate formation mask, the end portions of the floating gate 4 do not overlap or the overlap is shallow on the element isolation film 2 (FIG. 17). Reference).

In this case, for example, in the above-described read operation, even when the floating gate 4 is in a writing state (a state in which electrons are accumulated) and no drain current (read current) flows in the original channel region, the element isolation film 2 In the channel region where the ends of the floating gate 4 do not overlap or the overlap is shallow, leakage current flows from the source region 8 to the drain region 7 side as shown in FIG. (Refer to < RTI ID = 0.0 > IL >) < / RTI >

In order to cope with this, however, if the size of the floating gates is unnecessarily increased, a problem arises in that floating gates come into contact with each other because the distance between adjacent floating gates is narrow as shown in FIG. 8.

Accordingly, the present invention suppresses the occurrence of leakage current due to mask misalignment between the mask for forming an isolation film and the mask for forming a floating gate, and at the same time suppresses the occurrence of a reverse tunneling defect and a manufacturing method thereof. The purpose is to provide.

Therefore, the present invention has been made to solve the above problems, and the nonvolatile semiconductor memory device of the present invention is self-aligned so that an element isolation film formed on a silicon substrate of one conductivity type and an end portion of the element isolation film coincide with each other. And a floating gate formed in an active region separated by the device isolation film and disposed in a narrow space between adjacent device isolation films, a tunnel oxide film covering the floating gate, and a region overlapping the floating gate through the tunnel oxide film. And a reversely-conductive diffusion region formed on a surface of the semiconductor substrate adjacent to the floating gate and the control gate.

Further, the nonvolatile semiconductor memory device of the present invention is formed in an element isolation film formed on a silicon substrate of one conductivity type and in an active region self-aligned separated by the element isolation film so that an end portion thereof coincides with the element isolation film. And a floating gate having a sharp corner at an upper portion disposed in a narrow space between adjacent element isolation films, a tunnel oxide film covering the floating gate, and a region overlapping the floating gate through the tunnel oxide film. A gate, a floating gate, and a reverse conductive diffusion region formed on a surface of the silicon substrate adjacent to the control gate.

In addition, the manufacturing method of the nonvolatile semiconductor memory device of the present invention includes an element isolation film formed on a silicon substrate of one conductivity type, and an active region separated by the element isolation film in a self-aligning manner so that an end portion thereof coincides with the element isolation film. A floating gate formed in the interstices of the device isolation films adjacent to each other, a tunnel oxide film covering the floating gate, a control gate formed to have a region overlapping the floating gate through the tunnel oxide film, and the floating gate. A method of manufacturing a nonvolatile semiconductor memory device having a reverse conductivity type diffusion region formed on a surface of a silicon substrate adjacent to a gate and the control gate, wherein the element isolation film and the floating gate are formed of the same film.

In addition, the manufacturing method of the nonvolatile semiconductor memory device of the present invention includes an element isolation film formed on a silicon substrate of one conductivity type and an active region self-aligned separated by the element isolation film so that an end portion thereof coincides with the element isolation film. Formed to have a floating gate having a sharp corner at an upper portion disposed in a narrow space of an element isolation film adjacent to each other, a tunnel oxide film covering the floating gate, and a region overlapping the floating gate through the tunnel oxide film. A method of manufacturing a semiconductor memory device having a control gate, a floating gate, and a reverse conductive diffusion region formed on a surface of the silicon substrate adjacent to the control gate, wherein a gate oxide film and a conductive film are formed on the silicon substrate. And a silicon nitride film having a first opening on the conductive film. Thereafter, the silicon nitride film is used as a mask to selectively oxidize the conductive film by a LOCOS method to form an element isolation film, and after the photoresist film is formed on the silicon nitride film, the photoresist film is used as a mask. Removing the narrow silicon nitride film to form a second opening in the silicon nitride film; and removing the photoresist film, using the silicon nitride film as a mask, selectively oxidizing the conductive film under the second opening to form a second opening on the conductive film. Forming a selective oxide film, removing the silicon nitride film, and then anisotropically etching the conductive film using the selective oxide film as a mask to form a floating gate having sharp portions on the top, and forming the floating gate and the selective oxide film. Forming a tunnel oxide to cover Through the step, the tunnel oxide film to have a step of forming a control gate having the area which overlaps onto the floating gate.

1 is a plan view showing the structure of a memory cell of the nonvolatile semiconductor memory device of the present invention.

2 is a cross-sectional view taken along the line X1-X1 of FIG.

3 is a first diagram showing a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

4 is a second diagram showing a method for manufacturing a nonvolatile semiconductor memory device of the present invention.

5 is a third view showing a method of manufacturing the nonvolatile semiconductor memory device of the present invention.

Fig. 6 is a diagram showing the manufacturing method of the nonvolatile semiconductor memory device of the present invention.

Fig. 7 is a diagram showing the manufacturing method of the nonvolatile semiconductor memory device of the present invention.

8 is a plan view showing the structure of a memory of a conventional nonvolatile semiconductor memory device.

9 is a cross-sectional view taken along the line X2-X2 of FIG. 8.

10 is a first diagram showing a conventional method for manufacturing a nonvolatile semiconductor memory device.

Fig. 11 is a second diagram showing a conventional method for manufacturing a nonvolatile semiconductor memory device.

12 is a third diagram showing a conventional method for manufacturing a nonvolatile semiconductor memory device.

13 is a fourth diagram showing a conventional method for manufacturing a nonvolatile semiconductor memory device.

Fig. 14 is a diagram showing the manufacturing method of the conventional nonvolatile semiconductor memory device.

Fig. 15 is a diagram showing the manufacturing method of the conventional nonvolatile semiconductor memory device.

16 is a diagram for explaining a conventional problem.

17 is a diagram for explaining a conventional problem.

<Description of the code | symbol about the principal part of drawing>

1: P-type silicon substrate

2: device separator

31: gate oxide film

33: tunnel oxide film

34: floating gate

36: control gate

37: drain region

38: source area

40: aluminum wiring

EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of the manufacturing method of the nonvolatile semiconductor memory device of this invention is described, referring drawings. However, the same code | symbol is attached | subjected to the structure similar to a conventional structure, and description is abbreviate | omitted.

1 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate, and FIG. 2 is a cross-sectional view of the X1-X1 line thereof. In this figure, the split gate structure in which the control gate is arranged in parallel with the floating gate is shown.

In the surface region of the P-type silicon substrate 1, a plurality of element isolation films 2 made of LOCOS oxide films formed selectively thick (for example, 4000 to 8000 GPa) by LOCOS (Local Oxidation Of Silicon) method are rectangular in shape. The element region is partitioned. Here, the width d1 of the element isolation region is approximately 0.5 µm to 1.5 µm (microns), and the width d2 of the active region sandwiched in these adjacent element isolation regions is approximately 0.5 µm to 1.5 µm (microns). A floating gate 34 having a thickness of approximately 1500 kPa is disposed on the silicon substrate 1 through the gate oxide film 31 so as to be pushed into the narrow space of the adjacent device isolation film 2. This floating gate 34 is arranged independently for each memory cell. Further, the selective oxide film 35 on the floating gate 34 is formed thick at the center of the floating gate 34 by the selective oxidation method, and forms sharp corners on the floating gate 34. This makes it easy to cause electric field concentration at the end of the floating gate 34 during the data erasing operation.

On the silicon substrate 1 on which the plurality of floating gates 34 are disposed, the control gate 36 is formed through the tunnel oxide layer 33 integrated with the gate oxide layer 31 corresponding to each column of the floating gate 34. Is placed. This control gate 36 is disposed so that a part thereof overlaps on the floating gate 34, and the remaining part is in contact with the silicon substrate 1 through the tunnel oxide film 33. In addition, these floating gates 34 and control gates 36 are arranged such that the columns adjacent to each other are face-symmetric with each other.

An N-type drain region 37 and a source region 38 are formed in the substrate region between the control gate 36 and the substrate region between the floating gate 34. The drain region 37 is surrounded by the device isolation film 2 between the control gates 36 and is independent of each other, and the source region 38 is continuous in the extending direction of the control gate 36. The floating cell 34, the control gate 36, the drain region 37, and the source region 38 constitute a memory cell transistor.

Then, on the control gate 36, the aluminum wiring 40 is disposed in the direction crossing the control gate 36 via the oxide film 39. This aluminum wiring 40 is connected to the drain region 37 via the contact hole 41. Each control gate 36 becomes a word line, and the source region 38 extending in parallel with the control gate 36 becomes a source line. In addition, the aluminum wiring 40 connected to the drain region 37 becomes a bit line.

Hereinafter, a method of manufacturing a memory cell of such a nonvolatile semiconductor memory device will be described. 3-7, (a) is a top view, (b) is A-A sectional drawing, (c) is B-B sectional drawing.

First, in FIG. 3, the element isolation film 2 is formed on the silicon substrate 1 by the LOCOS method. That is, as shown in Fig. 3B, a gate oxide film 31 and a polysilicon film 32 are formed on the silicon substrate 1, and the silicon nitride film 23 having an opening is selected as a mask. Oxidation is performed to form the device isolation film 2. In this process, the region exposed in the silicon nitride film 23 of the polysilicon film 32 is oxidized to become the device isolation film 2, and the region left unoxidized under the silicon nitride film 23 is the floating gate ( 34, so that the device isolation film 2 and the floating gate 34 are formed continuously, and the interface becomes self-aligning.

Next, as shown in FIG. 4, after the photoresist film (not shown) is formed on the silicon nitride film 23, the silicon nitride film at the narrow position of the element isolation film 2 adjacent to each other (the photoresist film as a mask) is formed. 23 is etched to form openings 23A. However, the polysilicon film 23 below the opening 23A becomes the floating gate 34 in a later step.

Next, as shown in FIG. 5, the polysilicon film 32 under the said opening part 23A is selectively oxidized using the silicon nitride film 23 as a mask, and the selective oxide film 35 is formed.

Next, as shown in FIG. 6, after the polysilicon nitride film 23 is removed, the polysilicon film 32 is etched using the selective oxide film 35 as a mask, and the floating gate 34 having sharp corner portions on the top thereof is etched. ). Thereby, the floating gate 34 is arrange | positioned so that it may push into the narrow space of the adjacent element isolation film 2 as shown to FIG. 6 (a).

Then, as shown in FIG. 7, after the tunnel oxide film 33 is formed on the entire surface, a conductive film made of a polysilicon film and a tungsten silicide film is formed and patterned to form a control gate 36. However, the control gate 36 may be a single layer film made of a polysilicon film.

Hereinafter, although description is abbreviate | omitted, the memory cell of the nonvolatile semiconductor memory device by which the source area | region 38 and the drain area | region 37 are formed is formed as shown in FIGS.

As described above, in the present invention, the polysilicon film 32 for forming the element isolation film 2 (corresponding to the conventional pad polysilicon film 3) is not removed after the element isolation film 2 is formed and then subjected to a subsequent step. By using it as a floating gate 34 formation film, a manufacturing process can be simplified compared with the past.

In addition, as shown in FIG. 1, FIG. 7 and the like, since the floating gate 34 and the element isolation film 2 are formed in a self-aligning manner, the floating gate 4 and the element isolation film 2 are conventionally separated. This eliminates the need for high junction density and eliminates the problem of poor readability due to the leakage current.

In addition, since the structure of the present invention is not a structure in which the floating gate 4 is placed on the end of the device isolation film 2 as in the prior art (FIG. 16), the control gate 6 covering the floating gate 4 is provided. Since it is sharp in each form and electric field concentration arises in the part, the problem that the internal pressure between the floating gate 4 and the control gate 6 falls, and the so-called reverse tunneling defect is easy to occur is also eliminated. In addition, since the floating gate 4 is not mounted on the end of the device isolation film 2, planarization can be achieved.

Further, in one embodiment of the present invention, the selective oxide film 35 is formed on the polysilicon film 32, the polysilicon film 32 is etched using the selective oxide film 35 as a mask, and the floating gate 34 is etched. The present invention is not limited thereto, and the present invention is not limited thereto, and the polysilicon film may be applied to a nonvolatile semiconductor memory device having a floating gate formed by patterning the polysilicon film by a photolithography process. do.

In addition, although the floating gate was comprised with the polysilicon film also in this embodiment, you may comprise with a single crystal film, an amorphous silicon film, these laminated films, etc.

According to the present invention, a polysilicon film for forming an element isolation film is used as a floating gate forming film after the formation of an element isolation film and then removed, and then the manufacturing process can be simplified.

In addition, since the floating gate and the device isolation film are formed in a self-aligning manner, the conventional high gate density between the floating gate and the device isolation film is unnecessary, and the problem that a read failure occurs due to the leakage current flows can be solved. have.

In addition, since the structure of the present invention is not a structure in which the floating gate is placed on the end of the device isolation film as in the prior art, since the control gate covering the floating gate is sharp in each shape, and electric field concentration occurs in the portion, the floating The problem that the breakdown voltage between the gate and the control gate is lowered and so-called reverse tunneling defects are easily generated can also be solved. In addition, since the floating gate is not mounted on the end of the device isolation film, planarization can be achieved.

Claims (6)

An isolation layer formed on the silicon substrate of one conductivity type; A floating gate formed in an active region self-aligned separated by the device isolation layer so that an end portion of the device isolation layer coincides with the device isolation layer, and disposed in a narrow space of the device isolation layer adjacent to each other; A tunnel oxide film covering the floating gate; A control gate formed to have a region overlapping the floating gate through the tunnel oxide film; And A reverse conductive diffusion region formed on a surface of the semiconductor substrate adjacent to the floating gate and the control gate. And a nonvolatile semiconductor memory device. An isolation layer formed on the silicon substrate of one conductivity type; A floating gate formed in an active region self-aligned with the device isolation layer so that an end portion of the device isolation layer is coincident with the device isolation layer, and having a sharp portion at an upper portion of the device isolation layer adjacent to each other; A tunnel oxide film covering the floating gate; A control gate formed to have a region overlapping the floating gate through the tunnel oxide film; And A reverse conductive diffusion region formed on a surface of the silicon substrate adjacent to the floating gate and the control gate. And a nonvolatile semiconductor memory device. A device isolation film formed on a silicon substrate of one conductivity type, and floating in a narrow region of the device isolation film adjacent to each other, formed in an active region separated by the device isolation film so as to coincide with the device isolation film at an end thereof. A control gate formed to have a gate, a tunnel oxide film covering the floating gate, a region overlapping the floating gate through the tunnel oxide film, and formed on a surface of the silicon substrate adjacent to the floating gate and the control gate. In the method of manufacturing a nonvolatile semiconductor memory device having a reverse conductivity type diffusion region, And the device isolation film and the floating gate are formed of the same film. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the same film is a polysilicon film, a single crystal silicon film, an amorphous silicon film, or a laminated film thereof. A device isolation film formed on a silicon substrate of one conductivity type, and an upper portion formed in an active region separated by the device isolation film so as to coincide with the device isolation film, and arranged in a narrow space between adjacent device isolation films. A control gate formed to have a floating gate having a sharp corner portion, a tunnel oxide film covering the floating gate, a region overlapping the floating gate through the tunnel oxide film, and adjacent to the floating gate and the control gate. In the method of manufacturing a nonvolatile semiconductor memory device having a reverse conductivity type diffusion region formed on a surface of the silicon substrate, Forming a gate oxide film and a conductive film on the silicon substrate; Forming a silicon nitride film having a first opening on the conductive film and then selectively oxidizing the conductive film by a LOCOS method using the silicon nitride film as a mask to form an element isolation film; Forming a photoresist film on the silicon nitride film, and then removing the silicon nitride film in the upper part of the narrow space between adjacent device isolation films by using the photoresist film as a mask and forming a second opening in the silicon nitride film; Removing the photoresist film and then selectively oxidizing the conductive film under the second opening using the silicon nitride film as a mask and forming a selective oxide film on the conductive film; Anisotropically etching the conductive film using the selective oxide film as a mask after removing the silicon nitride film to form a floating gate having sharp portions on the top; Forming a tunnel oxide film so as to cover said floating gate and said selective oxide film; And Forming a control gate having a region overlapping the floating gate through the tunnel oxide film A method of manufacturing a nonvolatile semiconductor memory device, comprising: The method for manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein the conductive film is a polysilicon film, a single crystal silicon film, an amorphous silicon film, or a laminated film thereof.