JPH07111032A - Rotary servo circuit for disk player - Google Patents

Abstract

PURPOSE:To simplify circuit constitution in a rotary servo circuit for an earthquake-proof disk player utilizing a large capacity memory by using high speed and low speed modes as a driving mode of a disk and making the high speed mode when a track jump occurs. CONSTITUTION:In a spindle servo signal processing circuit 18, when the track jump occurs when low speed mode reproduction of e.g. 1.33 times speed is performed based on a reference clock, a mode switching signal with a high level is outputted from a controller not shown in figure, and the mode is moved to the high speed mode with a double speed. Further, when a large capacity RAM becomes an overflow state, an overflow signal is outputted from a control signal processing circuit not shown in figure, and the reference clock is switched by the circuit 18, and the mode is made to move from the high speed mode with the double speed to the low speed mode of 1.33 times speed. That is, the mode switching signal is supplied to an AND gate 31 by the controller, and the switching signal inverted by an inverter 34 is supplied to the AND gate 33, and the dealing with a low level and a high level are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital disc called a CD (compact disc) or an MD (mini disc).
The present invention relates to a rotary servo circuit of a disc player for reproducing an information recording disc (hereinafter, simply referred to as a disc) such as an audio disc, in particular, after reading data from the disc is temporarily stored in a large-capacity memory and then read from the large-capacity memory. The present invention relates to a rotation servo circuit of a disc player configured to output.

[0002]

2. Description of the Related Art In a disc player such as a CD player, when a so-called track jump occurs due to a disturbance such as a vibration during reproduction, continuity of reproduced data is ensured and sound skipping occurs. There are seismic resistant disc players that are configured not to. Here, the track jump means that an information reading light spot of a pickup that reads recording information while following a recording track (pit row) of a disc jumps over the recording track.

By the way, in a normal CD player, a data rate for reproducing from a disc (hereinafter referred to as a reproduction data rate) and a data rate for outputting audio (hereinafter referred to as an output data rate) are the same. On the other hand, in the conventional seismic CD player, by playing back the disc at a rotation speed twice as high as that of the normal CD player, the reproduction data rate higher than that of the normal CD player is obtained. The data is read at a rate and the read data is temporarily stored in a large-capacity memory, while the data is read from the large-capacity memory at an output data rate of a normal CD player and output.

When a track jump occurs during reproduction, the information reading light spot of the pickup is returned to the position immediately before the occurrence of the track jump, reproduction is restarted from that position, and the data stored in the large capacity memory is saved. The reproduced audio data obtained immediately after the reproduction is restarted is linked to the reproduced audio data immediately before the occurrence of the track jump, thereby ensuring the continuity of the reproduced audio data and preventing the sound skip.

The data stored in the large-capacity memory is always driven by rotating the disc at a rotation speed twice as high as that of a normal CD player, and always operating the focus, tracking, sled, and spindle servo systems. While monitoring the amount, when the amount of data exceeds a certain set amount, it is determined to be an overflow, and for example, the reverse jump of one track is repeated and the system waits. However, in such an earthquake-resistant CD player, since the disc is constantly driven to rotate at a high speed, the power consumption becomes large, and when low power consumption is required as in a portable CD player, for example. It was a disadvantage.

[0006]

On the other hand, only when a track jump occurs due to a disturbance such as a vibration,
The disk is rotatably driven at double speed (high-speed mode) to quickly store data in the large-capacity memory, while at other times it is rotatably driven at normal speed (low-speed mode) to reduce power consumption. An applicant CD player has been proposed by the present applicant (see Japanese Patent Laid-Open No. 4-268249).

In this seismic resistant CD player, when the rotary servo circuit for controlling the rotation of the spindle motor for driving the disk switches the drive mode from the low speed mode to the high speed mode or from the high speed mode to the low speed mode.
A configuration in which a frequency error signal is obtained by gradually changing a frequency division ratio of a clock signal, which is a reference for speed control, and a so-called pitch control of a cycle of the clock signal, and speed control of a spindle motor is performed based on the frequency error signal. It was.

As described above, in the conventional rotary servo circuit having the pitch control of the period of the clock signal which is the reference of the speed control, the ideal speed control can be performed, but the VCO (voltage controlled oscillator) or the PLL is used. (Phase Loc
Since there is a need to use a ked loop) circuit, the circuit configuration becomes complicated and the cost becomes high. Therefore, it is an object of the present invention to provide a rotary servo circuit capable of reducing the power consumption and the cost of an earthquake-resistant disc player.

[0009]

A rotary servo circuit according to the present invention monitors a large-capacity memory for storing data read from a disk and a predetermined amount of the data while monitoring the amount of data stored in the large-capacity memory. In a disc player equipped with a memory control means for outputting an overflow signal when the set amount is exceeded, the disc is normally driven to rotate in a low speed mode, and when a track jump occurs, it is driven to rotate in a high speed mode. In addition, when the overflow signal is output, it is a rotation servo circuit for controlling the rotation drive again in the low speed mode.
Clock generating means for generating a clock signal, a frequency dividing means for dividing the first clock signal by a predetermined fixed frequency division ratio and outputting a second clock signal, and a second clock signal in the low speed mode. And gate means for selectively outputting the first clock signal in the high speed mode, and the drive control of the disk is performed on the basis of the clock signal output from the gate means.

[0010]

In the rotation servo circuit of the seismic resistant disk player using a large capacity memory, the player has low power consumption by having a high speed mode and a low speed mode as a disk drive mode and setting the high speed mode only when a track jump occurs. Plan. Further, two clock signals having different frequencies corresponding to the respective drive modes are prepared as the clock signal serving as the reference of the speed control, and the drive mode is switched by appropriately selecting the clock signal having any one of the frequencies. With this, since it is sufficient to simply switch the frequency of the reference clock signal, the circuit structure can be simplified and the cost of the player can be reduced accordingly.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3 is a block diagram showing a configuration example of a control system of, for example, a CD player to which the present invention is applied. Figure 3
In FIG. 1, a disc (CD) 1 is rotationally driven by a spindle motor 2, and its recorded information is read by an optical pickup (hereinafter, simply referred to as a pickup) 3.

The pickup 3 includes a laser diode 4,
An objective lens 5 for focusing a laser light beam emitted from the laser diode 4 on the signal surface of the disc 1 as an information reading light spot, a polarization beam splitter 6 for changing the traveling direction of the reflected light beam from the disc 1, and the reflected light It is composed of a photodetector 7 for receiving a beam and the like, and is provided so as to be movable in the disk radial direction using a thread feed motor (not shown) as a drive source.

Although not shown, the pickup 3 further includes a tracking actuator for biasing the information reading light spot with respect to the recording track of the disc 1 in the disc radial direction, and a focus actuator for moving the objective lens 5 in the optical axis direction. And are built in. The output signal of the pickup 3 is converted from a current signal to a voltage signal by an I (current) / V (voltage) amplifier 8 and further waveform-shaped by an RF equalizer circuit 9, and then a DSP (Digital Signal Processor) circuit 10. Supplied.

Next, the signal processing in the DSP circuit 10 will be described. First, the PLL asymmetry correction circuit 11 corrects asymmetry to obtain a binary signal, and continuous clock pulses are generated by the configuration of the PLL based on the edge of the binary signal. Here, asymmetry means R
The state in which the center of the eye pattern of the F signal deviates from the center of the amplitude.

Next, in the EFM demodulation circuit 12, the EF
M (Eight to Fourteen Modulation) is demodulated to become digital audio data and parity for error correction / detection, and the subcode immediately after the frame synchronization signal is demodulated. EFM demodulation circuit 12
The subcode demodulated in (1) is supplied to the controller 20 described later via the subcode processing circuit 13.

The data after the EFM demodulation is temporarily stored in the RAM 14, and the error correction circuit 15 performs error correction based on the error correction / detection parity. The data after the error correction is deinterleaved by the de-interleave circuit 16 by CIRC (Cross Interleave Reed-Solomon Code). The DSP circuit 10 includes a clock generator 17 that generates a system clock based on the oscillation output of the crystal oscillator 21, and executes signal processing based on the system clock.

The data that has passed through the DSP circuit 10 is passed through the RAM control signal processing circuit 22 and has a large capacity RAM 23.
Once stored in. The data stored in the large-capacity RAM 23 is read through the RAM control signal processing circuit 22, filtered by the digital filter 24, analogized by the D / A converter 25, and derived as L and R audio outputs. To be done.

Here, the large capacity RAM 23 is
This is used for ensuring continuity of reproduced audio data and preventing skipping when a track jump occurs due to a disturbance such as a vibration.
That is, when a track jump occurs, under the control of the controller 20, the information reading light spot of the pickup 3 is returned to the position immediately before the occurrence of the track jump, and reproduction is restarted from that position, while the RAM control signal processing circuit 22 Under control, the reproduced audio data immediately after occurrence of the track jump stored in the large capacity RAM 23 is linked with the reproduced audio data obtained after the reproduction is restarted.

The DSP circuit 10 includes a spindle motor 2 based on the phase difference between the reproduction clock and the reference clock.
A spindle / servo signal processing circuit (rotational servo circuit) 18 for controlling the rotation of is provided. The optical system servo signal processing circuit 26 is a servo system related to the operation of the pickup 3, that is, a tracking servo system for causing the information reading light spot to follow the recording track of the disc 1, and the optical spot of the disc 1 of the disc 1. This is for controlling the focus servo system for always focusing on the signal surface and the sled servo system for controlling the position of the pickup 3 in the disk radial direction.

The spindle / servo signal processing circuit 18 is
Normally, the spindle motor 2 for driving the disk 1 is rotationally driven in the low speed mode, is rotationally driven in the high speed mode when a track jump occurs, and is again driven when the large capacity RAM 23 is in the memory full state in the high speed mode. Rotate in low speed mode. Here, the low speed mode refers to a drive mode in which the spindle motor 2 is rotationally driven at a speed slightly higher than the rotation speed (normal speed) of a normal CD player, for example, 1.33 times speed. Is a drive mode in which the spindle motor 2 is rotationally driven at a double speed, for example.

The drive mode of the spindle motor 2 is switched by a mode switching signal from the controller 20. The controller 20 constantly monitors the subcode during reproduction in the low-speed mode, detects the occurrence of the track jump by detecting that the timecode of the subcode is discontinuous, and drives the spindle motor 2 at that time. It outputs a high level mode switching signal for switching the mode to the high speed mode.

At this time, the controller 20 searches for the last subcode having continuity, returns the pickup 3 to the position immediately before the occurrence of the track jump, controls the reproduction from that position again, and reproduces from that position. RA to perform linking processing for connecting audio data
The M control signal processing circuit 22 is controlled. here,
The reason why the reproduction is performed at the double speed in the high speed mode will be described. When 4 Mbits are used as the large capacity RAM 23, the speed at which the large capacity RAM 23 is charged with data is the difference between the speed at which the data is written in the large capacity RAM 23 and the speed at which the data is read (2 times-1 times).

That is, since the digital signal is recorded on the disk 1 with a sampling frequency of 44.1 KHz and a quantization number of 16 bits,

[Equation 1] 4,194,304 ^{bits / (} 44.1 ^KHz × 2)
^{(L, R)} × 16) ^bit × 1 = 2.97 [seconds] Therefore, it takes about 3 seconds to charge the large capacity RAM 23. Even if the data is not reproduced from the disc 1 due to the occurrence of the track jump, the time of 3 seconds
It is the time when the sound can be played back without interruption. This time is practically no problem and is determined by the memory capacity of the large capacity RAM 23 and the reproduction speed in the high speed mode, that is, the reproduction data rate.

Further, the controller 20 switches the drive mode of the spindle motor 2 to the low speed mode in response to the overflow signal output from the RAM control signal processing circuit 22 during the reproduction in the high speed mode. It outputs a low-level mode switching signal. By the way, since the data writing to the large capacity RAM 23 is performed at a higher speed than the reading, the large capacity RAM 23 immediately overflows, and thus the large capacity RA
It is necessary to constantly monitor the amount of data stored in M23.

The RAM control signal processing circuit 22 monitors the data amount of the large capacity RAM 23. That is, the RAM control signal processing circuit 22
Recognizes the final address of the data written in the large-capacity RAM 23 as the definite address, and always recognizes the address of the read data as the address 0. Then, the amount of data is monitored based on this fixed address, and when the amount of data exceeds a predetermined set amount, an overflow signal is output.

The RAM control signal processing circuit 22 includes
The recognized address is always given to the controller 20, and an overflow signal is sent to the controller 20.
Supply to 0. The controller 20 is composed of a CPU, and recognizes the definite address given from the RAM control signal processing circuit 22 as a definite subcode in correspondence with the subcode.

FIG. 1 is a block diagram showing an embodiment of a spindle servo signal processing circuit (rotary servo circuit) 18 according to the present invention. In FIG. 1, the clock generator 17
16.9344 MHz supplied from (see Figure 3)
(44.1 KHz × 384) becomes one input of the AND gate 31 and is divided by the 2/3 frequency divider 32 to obtain 1
It becomes a clock signal of 1.2896 MHz and becomes one input of the AND gate 33.

The other input of the AND gate 31 is supplied with the mode switching signal output from the controller 20 (see FIG. 3), and the AND gate 33 is supplied with the mode switching signal inverted by the inverter 34.
The output clocks of the AND gates 31 and 33 are output as a reference clock via the OR gate 35. This AN
By the gate circuit composed of the D gates 31 and 33, the inverter 34 and the OR gate 35, a clock of 16.9334 MHz is used as a reference clock when the mode switching signal is high level, and a clock of 11.28896 MHz is used when the mode switching signal is low level. The clock is output as the reference clock.

This reference clock is supplied to the phase comparator 36. The phase comparator 36 uses this reference clock as a reference for phase comparison, and detects a phase difference between the reproduction clock synchronized with the reproduction data from the disc 1 and the reference clock,
Output the phase difference signal. This phase difference signal is supplied to a motor drive circuit 39 as a spindle error signal via an LPF (low pass filter) 37 and an amplifier 38. In the spindle servo signal processing circuit 18 having the above-mentioned configuration, the feature of the present invention is that the frequency of the reference clock is appropriately selected according to the mode switching signal, and the spindle error is generated based on this reference clock. The portion for generating a signal is not limited to the above circuit configuration.

This spindle / servo signal processing circuit 18
Based on a reference clock of 11.2896 MHz.
When a track jump occurs due to disturbance such as vibration during playback in the 33-speed low-speed mode, and the controller 20 outputs a high-level mode switching signal, the reference clock is changed from 11.2896 MHz to 169334 MH.
Then, the mode is switched to z and the mode shifts to the double speed mode based on the reference clock of 16.9334 MHz. Then, during the above-mentioned 3 seconds, the linking process for maintaining the continuity of the reproduced audio data and the data charge of the large capacity RAM 23 are performed.

On the other hand, when the large-capacity RAM 23 is in an overflow state, the RAM control signal processing circuit 22 outputs an overflow signal, and in response to this overflow signal, the controller 20 outputs a low-level mode switching signal. -The servo signal processing circuit 18 switches the reference clock from 16.93334 MHz to 11.2896 MHz, and this 11.289
The mode shifts to the low speed mode of 1.33 times speed based on the 6 MHz reference clock.

Now, the reason why the speed in the low speed mode is set to 1.33 times speed instead of 1 times speed will be described. The above-mentioned spindle / servo signal processing circuit 18 has a configuration in which the frequency of the reference clock is simply switched in order to simplify the circuit configuration. Therefore, when the drive mode is switched, the entire system is locked. It takes about 1 second. Since data is read from the large-capacity RAM 23 during this 1 second, the amount of data in the large-capacity RAM 23 is insufficient by one second.

Therefore, when the disturbance such as a vibration disappears from the double speed high speed mode and the mode shifts to the low speed mode, the reproduction data rate and the output data rate become the same if the reproduction is performed at the single speed, and the data equivalent to one second. The deficiency is not eliminated, and it always remains deficient until the next double speed reproduction. Therefore, when the next disturbance occurs, the large capacity RAM 23 will be charged with data for only 2 seconds. However, as in the case of the present embodiment, by performing the reproduction at 1.33 times speed, the large-capacity RAM 2 while performing the normal reproduction.
Data can be gradually charged to 3. In addition,
The double speed in the low speed mode is not limited to 1.33 times, and may be slightly faster than the 1 times speed.

FIG. 2 is a block diagram showing an example of a concrete circuit configuration of the 2/3 frequency divider 32 in FIG. Figure 2
, The 16.9334 MHz clock signal is inverted by the inverter 41 to become one input of the AND gate 42, and further inverted by the inverter 43.
One input of the D gate 44 and the D flip-flop 45,
It becomes each clock input of 46. D flip-flop 45
Q becomes the D (data) input of the D flip-flop 46 and one input of the NAND gate 47. Also, D
Q _N output of flip-flop 45 (inverted output of Q output)
Becomes the other input of the AND gate 42.

The Q output of the D flip-flop 46 is the D input of the D flip-flop 48 and the NAND gate 47.
Other input. The output of the NAND gate 47 becomes the D input of the D flip-flop 45. The Q _N output of the D flip-flop 48 becomes the other input of the AND gate 44.
Each output of the AND gates 42 and 44 becomes two inputs of the OR gate 49. With the logic circuit having the above-described configuration, an 11.28334 MHz clock signal obtained by dividing the 16.9334 MHz clock signal by 2/3 is derived as the output of the OR gate 49.

In the above embodiment, the case where the present invention is applied to the CD player has been described, but the present invention is not limited to this, and is similarly applied to other disc players for reproducing MD and CD-ROM discs. I will get it.

[0037]

As described above, according to the present invention,
In the rotation servo circuit of the seismic disk player that uses a large capacity memory, the disk drive mode has a high-speed mode and a low-speed mode, and the high-speed mode is set only when a track jump occurs. By preparing two clock signals of different frequencies corresponding to each drive mode and switching the drive mode by appropriately selecting a clock signal of any frequency, only the frequency of the reference clock signal is switched. Since the above configuration is sufficient, the circuit configuration can be simplified, and the cost of the player can be reduced accordingly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a spindle servo signal processing circuit (rotary servo circuit) according to the present invention.

FIG. 2 is a block diagram showing an example of a specific circuit configuration of a 2/3 frequency divider.

FIG. 3 is a block diagram showing an example of a configuration of a control system of a CD player to which the present invention is applied.

[Explanation of symbols]

1 disk 2 spindle motor 3 optical pickup 10 D
SP circuit 12 EFM demodulation circuit 17 Clock generator 18 Spindle servo signal processing circuit 20 Controller 22 RAM control signal processing circuit 23 Large capacity RAM 26 Optical system servo signal processing circuit 32 2
/ 3 frequency divider 36 phase comparator 39 motor drive circuit

Claims (1)

[Claims] 1. A large capacity memory for storing read data from a disk, and an overflow signal is output when the amount of data stored in the large capacity memory exceeds a predetermined set amount while monitoring the amount of data. In a disc player provided with a memory control means, the disc is normally rotationally driven in a low speed mode, and when a track jump occurs, the disc is rotationally driven in a high speed mode and when the overflow signal is output, the low speed mode is resumed. A rotation servo circuit for controlling the rotation of the first clock signal to generate a first clock signal having a predetermined frequency; and a second fixed frequency division circuit for dividing the first clock signal by a predetermined fixed frequency division ratio. Frequency dividing means for outputting the clock signal, the second clock signal in the low speed mode, and the first clock signal in the high speed mode. A rotation servo circuit for a disc player, comprising: a gate means for selectively outputting a clock signal, and performing drive control of the disc based on the clock signal output from the gate means.