JPH02156470A - Data reproducing device - Google Patents

Abstract

PURPOSE:To promote the operability of the subject reproducing device by setting a 1st speed for an acoustic signal whose read speed is specified and a 2nd speed as faster than the 1st speed for a relevant signal at the time of reproducing a data from a compact disk digital audio tape recorder, etc. CONSTITUTION:When an initial read operation of a CD 31 is performed, switch circuits SW1 and SW42 are controlled by using a control device 50, so that an oscillator circuit 41 for generating a frequency as double as many as in a normal reproducing operation f2 = 2f1 is connected to a VCO circuit 39, and a quartz oscillator 46 for generating the double frequency f2 to a divide circuit 47 respectively. Thus, the read speed of a 2nd data such as TOC, etc., from the CD 31 is promoted to be doubled. Then, as to a search operation for finding out a reproducing position at the time of reproducing a prescribed 1st data by an operator with an input means 51, the search operation is started by connecting an individual contact 58 of the circuit SW1 to a common contact 56.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to CD (compact disc) playback devices and DA playback devices.
The present invention relates to a data reproducing device such as a digital audio recorder (T), and more particularly to a data reproducing device that can quickly reproduce desired data from a recording medium.

BACKGROUND OF THE INVENTION FIG. 3 is a block diagram showing the basic configuration of a conventional compact disc playback device 1. A compact disc 2 mounted on a compact disc reproducing apparatus 1 is rotationally driven in the direction of arrow R by a motor 3, and first data and second data recorded on the compact disc 2 are read by an optical pickup 4.

The compact disc 2 includes an audio signal, a video signal, or other digitized first data, and controls related to the first data to which r= is added for convenience such as retrieval of the first data. Information is recorded in advance as digitized second data. 1st data and 2nd data
Data is allocated to a first data recording area and a second data recording area in a recording unit called a plurality of frames, and each of these plurality of frames is an E F M
(Eight to Fourteer + Modula
tion) The compact disc 2 is made up of a large number of recesses called pits.

The optical pickup 4 is movable by a motor 23 near the compact disc 2 in the radial direction indicated by arrows 2a and 2b. The optical pickup 4 is provided with a light emitting element and a light receiving element. The light from the light emitting element of the optical pickup 4 is reflected by the pit portions of the compact disc 2 and portions other than the pit portions called lands, and the light intensity is modulated accordingly. This modulated reflected light is received by the light receiving element of the optical pickup 4, and a current generated according to the light intensity is sequentially applied to the level slice circuit 5 and the waveform shaping circuit 6 as a reproduction signal converted into current and voltage.

The reproduced signal converted into an electrical signal passes through the level slicing circuit 5 and the waveform shaping circuit 6, thereby correcting the uneven center level of the waveform called the eye pattern of the reproduced signal, and shaping the waveform into a square wave. Ru. The reproduced signal in the form of a square wave is branched and sent to an EFM demodulation circuit 7 and a phase locked loop (hereinafter abbreviated as rPLL) circuit 8.

The PLL circuit 8 includes a phase comparator circuit 9, a voltage controlled oscillation (Vo
ltage Control 0scillator,
The circuit 10 (hereinafter abbreviated as "VCO"), the oscillation circuit 11 that generates the first clock signal CKI, etc., generates a clock signal related to the rotational speed of the motor 3 based on the input reproduction signal as described later. Generate a signal. This clock signal has a frequency of 43218 MHz
The frequency divider circuit 12 divides the frequency F→7 for every 588 bits constituting one frame of the reproduced signal.
．． The second clock signal CK2 having a frequency of 35 kHz is divided and provided to the frequency detection circuit 13 and the phase comparison circuit 14.

The phase comparator circuit 14 receives a reference frequency Pa = 7.3 generated by dividing a crystal oscillated clock signal by a frequency dividing circuit 16 to which a crystal oscillation circuit 15 is connected in advance.
A third clock signal CK3 having a frequency of 5 kHz is provided. Therefore, the phase comparison circuit 14 outputs a voltage level corresponding to the phase difference to the line 16 based on the input second clock signal CK2 and third clock signal CK3.

On the other hand, the frequency detection circuit 13 outputs to the line 15 a voltage level corresponding to the frequency F of 7.35 kHz of the input second clock signal CK2.

In this way, the output voltage level of the frequency detection circuit 13 and the output voltage level of the phase comparison circuit 14 are added to the line 17 and applied to the motor drive circuit 17.

The motor drive circuit 17 drives the motor 3 to rotate at a rotation speed corresponding to the input voltage level.

In this way, the frequency F of the second clock signal CK2 output from the frequency divider circuit 12 to the line 13 is
Reference frequency F of the third clock signal CK3 output on line 14 from . The rotational speed of the motor 3 that rotates the compact disc 2 is controlled so as to match the rotational speed of the compact disc 2. Therefore, the reading means including the optical pickup 4 is equipped with a CLV (Co-operated voltage reading system) that reads the first data and the second data recorded on the compact disc 2 so that the circumferential speed thereof is constant.
Instant Linear Velocity) control is performed.

On the other hand, the reproduction signal given to the EFM demodulation circuit 7 is
The zero-separated first data, which is separated into first data and second data after being MI-tuned, is digital-to-analog converted and restored to an audio signal, a video signal, or the like. The second data is input to the subcode demodulation circuit 18, which performs data processing such as deinterleaving and descrambling, which undoes data rearrangement by interleaving and scrambling previously applied to the recorded data, and error correction during playback. After processing, the TOC (Table or C) recorded in the lead-in area RIA of the compact disc 2
Subcode data attached to each content (contents) and Freno are given to one control circuit.

The control circuit 19 temporarily stores +71 I related to the first data included in the input TOC and subcode data in a memory (not shown). Along with this, this control circuit 1
The operator performs an input operation f? using the subcode data sequentially input to 9 and the input means 20. Based on the search operation signal, the display means 21 displays the reproduction operation status and the like to the operator.

Mana M time! 81 sends data regarding the running drive of the compact disc 2 of the optical pickup 4 in the radial directions 2a and 2b to the arithmetic circuit 22 when performing an initial reading operation or a search operation. The calculation circuit 22 executes a predetermined calculation based on the input data, and outputs a drive control signal to the motor drive circuit 24. Motor drive circuit 2
4 drives the motor 23 based on the input drive control signal to drive the optical pickup 4 to travel in the radial directions 2a and 2b of the compact disc 2 to a predetermined reading position.

Next, a conventional operation for reading desired first data according to a program regarding the playback order of the first data inputted in advance by the operator using the input means 20 or a playback start goal of a search operation will be described. compact disc 2
When the compact disc 2 is loaded into the compact disc reproducing apparatus 1, the optical pickup 4 first reads second data related to the TOC recorded on the innermost circumference of the recording surface of the compact disc 2, called the glue-in area RIA. The read reproduction signal is subjected to EFMfi modulation and subcode demodulation as described above, and is stored in a memory (not shown) by one control circuit. Along with this, the control circuit 19 also controls the display means 21.
For example, if the first data is music data,
Information such as the total number of songs and total performance time recorded on the compact disc 2 is displayed.

The operator inputs the compact disc 2 using the input means 20.
When an input operation is performed to reproduce desired data of the first data recorded in The circuit 19 is an arithmetic circuit 22
A signal indicating the current position of the optical pickup 4 and a signal indicating a reproduction start target are given to the optical pickup 4.

The ii4 arithmetic circuit 22 calculates a driving-side tn signal necessary for moving the optical pickup 4 to the reproduction start position from the two input signals and supplies it to the motor driving circuit 24. As a result, the optical pickup 1 is moved to the vicinity of the playback start position l\. The optical pickup 4 picks up the second compact disc 2 facing the optical pickup 4 at the arrival position.
Read data. The above search operation is repeated until, for example, the total play time of the read second data matches the play start time of the input playback start target. When the search operation is thus completed, the optical pickup 4 that has reached the input playback start position reads the desired first data and starts the playback operation.

Problems to be Solved by the Invention In the conventional compact disc playback device 1, data related to the first data is detected in the initial reading operation or search operation performed when the compact disc 2 is loaded into the compact disc playback device 1. The operation of reading the second data is as follows:
The CLV control was performed under the same conditions as the rotational speed of the compact disc 2 when reading the first data.

That is, the PLL circuit 8 operates on the line 11 based on the first clock signal CKI generated by the oscillation circuit 11.
A clock signal having a frequency I"p4.3218 MHz in which the rise and fall of the square wave constituting the playback signal coincides with the playback signal input to the PLL circuit 8 via the playback signal is sent to the frequency dividing circuit 12. The frequency Fa-97, 35 kHz of the second tarlock signal CK2 output from the frequency divider circuit 12 to the line 13 is generated in advance by the crystal oscillator circuit 15 and divided by the frequency divider circuit 16.
The reference frequency F0 of the third tarlock signal CK3 output to
The rotational speed of the compact disc 2 is controlled so as to coincide with =7.35kHz. Therefore, the first data recorded on the compact disc 2 and the second data, which is information related to the first data, are reproduced at exactly the same speed.

However, the lead-in area RIA of Compact Disc 2
If there is a large amount of second data, it will take a long time to perform the initial reading operation in proportion to the amount of data. In addition, when a search operation is performed, in order to move the optical pickup 4 to the target playback start position, the optical pickup 4 is moved to the compact disc 2 facing at that point between the start and end of the search operation. Second recorded
Multiple operations are required to read the data. Therefore, the time from when the reproduction start target is input by the input means 20 until the optical pickup 4 is moved to the reproduction start position and the search operation is completed includes the time for multiple second data reading operations. ing.

An object of the present invention is to shorten the reading time of the second data in the initial reading operation, search operation, etc., thereby realizing a high-speed initial reading operation and a high-speed search operation.
An object of the present invention is to provide a data reproducing device with improved performance.

Means for Solving the Problems The present invention provides a recording medium in which a plurality of first data are recorded in a first data recording area and a second data recording area, respectively, together with second data related to the first data. 1st above
A data reproducing device for reproducing data and second data, comprising: reading means for reading first data and second data from a recording medium; first signal generating means for generating a plurality of predetermined types of reference frequency signals; a second signal generating means that generates a signal of a predetermined frequency corresponding to the type based on the output of each type of signal generating means, first data and second data; and the first signal generating means. a third signal generating means for generating a plurality of predetermined types of reference frequency signals corresponding to each type of output of the means, and based on each output of the second signal generating means and the third signal generating means, This data reproducing device is characterized in that the running speed of the recording medium is controlled so that the frequency and phase of each output match.

Operation The data reproducing device of the present invention includes a first signal generating means for generating a plurality of predetermined reference frequency signals of NM, and a plurality of predetermined types of reference frequency signals corresponding to each type of output of the first signal generating means. and third signal generating means for generating a reference frequency signal. Further, based on the output of each type of the first signal generating means and the first data and second data read from the recording medium by the reading means, a predetermined frequency signal corresponding to the above type is generated as a second signal. generated by means. Based on the frequency signals output from the second signal generating means and the third signal generating means, the recording medium is run in relation to the output of the second signal generating means so that the frequencies and phases of these signals match each other. Speed is controlled.

Therefore, according to the present invention, by varying the types of reference frequency signals generated by the first signal generating means and the third signal generating means in correspondence with each other, the running speed of the recording medium can be changed to a plurality of possible types. With this, the reading speed of the first data and the second data read from the recording medium by the reading means can be set to a desired speed, and the reading speed of the first data and the reading speed of the first data can be set to a desired speed. It is also possible to set the reading speeds of the second data to different speeds.

Embodiment Hereinafter, a description will be given based on an embodiment in which the data reproducing apparatus of the present invention is applied to a compact disc reproducing apparatus 30. 1st
The figure is a block diagram showing the basic configuration of a compact disc playback device 30 that is an embodiment of the present invention. A compact disc 31 mounted on a compact disc reproducing device 30 is rotated in the direction of arrow iR by a spindle motor 32, and first data and second data recorded on the compact disc 31 are read by an optical pickup 33.

The compact disc 31 contains audio signals, video signals, or other digitized first data, and this first data.
The first item added for convenience such as data searches, etc.
Second data in which control information related to the data is digitized is recorded in advance. The first data and the second data are recorded in units of recording called multiple frames.
The frames are allocated to the data recording area and the second data recording area, respectively, and each of these multiple frames is EFM-modulated to form a large number of concave portions called bits (convex portions from the direction in which the optical pickup 33 faces the compact disk 31). Department).

The compact disc 31 has a disc-shaped transparent plastic made of polycarbonate or the like, and on one surface thereof, a number of recesses called pintos are spirally formed in the circumferential direction. After a thin metal film made of aluminum or the like is vapor-deposited to reflect light, a relatively hard resin is coated to protect the bit portion and the signal layer made of the metal film.

The optical pink-up 33 is movable in the radial direction shown by arrows 31a and 31b near the compact disc 31 by a feed motor 54. This light pickup 3
3 is provided with a light emitting element such as a semiconductor laser and a light receiving element such as a photodiode. The amount of laser light focused from the light emitting element of the optical pickup 33 onto the bit portion of the compact disc 31 differs between the bit portion and the land portion other than the bit portion. Further, several types of bits Pi of different lengths corresponding to the data to be recorded are spirally connected on the recording surface of the compact disc 31 to form a track. Therefore, the optical pickup 33 can read the first data and the second data recorded in the circumferential direction by tracking the length of the bit part of this track according to the amount of light reflected at the bit part.

The laser beam from the light emitting element of the optical pickup 33 is reflected by the bit part and land part of the compact disc 31, and the reflected light whose light intensity is modulated is received again by the light receiving element of the optical pickup 33, and the light is The current generated in accordance with the intensity is applied to the level slice circuit 34 as a reproduction signal converted into current and voltage. The reproduced signal whose center level of the eye pattern waveform has been aligned by the level slice circuit 34 is provided to the waveform shaping circuit 35. In the waveform shaping circuit 35, the waveform of the reproduced signal is shaped into a square wave. The reproduction signal made into a square wave is sent to the EFM demodulation circuit 36 and the PLL.
The signal is branched to the circuit 37 and provided thereto.

The PLL circuit 37 includes a phase comparison circuit 38 and a VCO circuit 39.
, oscillation circuits 40, 41 . and switch circuit SW 1
It consists of: In this way, in the PLL circuit 37 of the compact disc playback device 30 of this embodiment, the oscillation circuit 40.4 generates mutually different reference frequency signals.
1 is provided.

In contrast to the frequency I of the signal output by the oscillation circuit 40, the oscillation circuit 41 outputs a signal with a frequency f 2 '' 21 , for example.

The reproduction signal input to the PLL circuit 37 via the line t'll generates a clock signal related to the rotation speed of the spindle motor 32, which will be described later, by the function of the PLL circuit 37, and sends it to the frequency dividing circuit 42. . In the frequency dividing circuit 42, the input clock signal is transmitted to the compact disc 31.
The second clock signal C has a frequency of one rate for every 588 bits constituting one frame of data recorded on the clock.
The frequency is divided into K2, and the signal is branched to a frequency detection circuit 43 and a phase comparison circuit 14, respectively.

The phase comparison circuit 44 has a reference frequency generated by dividing the crystal oscillated clock signal by a frequency dividing circuit 47 which is selectively connected to the crystal oscillation circuit 45 and 46 by the switch circuit SW2. 3 clock signal CK3 is provided. As described above, in the compact disc playback device 30 of this embodiment, the crystal oscillation circuits 45 and 46 that generate mutually different reference frequency signals are provided, and for the frequency I of the signal output from the crystal oscillation circuit 45, The crystal oscillation circuit 46 has a frequency relationship f2 in the oscillation circuits 40 and 41 of the PLL circuit 37 described above.
The 0 phase comparator circuit 44, which is set to output a signal with a frequency f4=2I corresponding to 2f, receives the second clock signal CK2 and the third clock signal CK3.
Based on the phase difference, a voltage level corresponding to the phase difference is sent to line 116.

On the other hand, the frequency detection circuit 43 detects a voltage level corresponding to the frequency of the input second clock signal CK2 on the line 11.
Send to 5. In this way, the output voltage level of the frequency detection circuit 43 and the output voltage level of the phase comparison circuit 44 are added to the line 717 and applied to the motor drive circuit 48.

The motor drive circuit 48 rotates the spindle motor 32 at a rotation speed corresponding to the input voltage level.

In this way, the frequency F2 of the second clock signal CK2 sent from the frequency dividing circuit 42 to the line f13 is the same as the frequency F2 of the second clock signal CK2 sent from the frequency dividing circuit 47 to the line f13.
The rotational speed of the spindle motor 32 that rotates the compact disk 31 is controlled so as to match the reference frequency F of K3. Therefore, the reading means including the optical pickup 33 has a CLV that reads the first data and the second data recorded on the compact disc 31 as a spiral track consisting of a pit part and a land part so that the circumferential speed of the data is constant. Control takes place.

On the other hand, EFMr! J, reproduction 13 given to the tuning circuit 36
The signal is EFM-demodulated and then separated into first data and second data. The zero-separated first data is digital-to-analog converted and restored to a sound g signal, a video signal, or the like. The second data is input to the subcode demodulation circuit 49, and is subjected to data processing such as deinterleaving and descrambling, which undoes data rearrangement by interleaving, scrambling, etc. applied to the recorded data in advance, and processing such as data error correction. The TOC recorded in the lead-in area RIA of the compact disc 31 and the subcode data attached to each frame are provided to the control circuit 50.

The control circuit 50 temporarily stores information regarding the first data included in the input TOC and subcode data in a memory (not shown). Along with this, subcode data and input means 51 are sequentially input to this control circuit 50.
Based on the search operation signal inputted by the operator, the display means 52 displays the reproduction operation status and the like to the operator.

Furthermore, when performing an initial reading operation or a search operation for the compact disc 31, the control circuit 50 sends data regarding the traveling drive of the optical pickup 33 in the radial directions 31a, 31b of the compact disc 31 to the arithmetic circuit 53. The calculation circuit 53 executes a predetermined calculation based on the input data, and outputs a drive control signal to the motor drive circuit 55. The motor drive circuit 55 drives the feed motor 54 based on the input drive control signal to move the optical pickup 33 in the radial direction 31 of the compact disc 31.
a and 31b to move to a predetermined reading position.

Furthermore, the control circuit 50 mutually switches the switch circuits SWI and SW2 in accordance with the initial reading operation and search operation of the compact disc 31, which will be described later, and other normal playback operations.

Next, a description will be given of an operation for reading desired first data in accordance with, for example, a program regarding the playback order of the first data, a playback start goal of a search operation, etc. inputted in advance by the operator using the input means 51. When the compact disc 31 is loaded into the compact disc 1 to the disc playback device 30, the second TOC recorded in the lead-in area RTA on the innermost circumference of the recording surface of the compact disc 31 is displayed.
Data is first read by optical pickup 33.

The read reproduction signal is subjected to E F M demodulation and subcode demodulation as described above, and is stored in a memory (not shown) by the control circuit 50. At the same time, the control circuit 50 displays information such as the total number of songs recorded on the compact disc 31 and the total playing time on the display means 52, for example, when the first data is music data.

When the optical pickup 33 performs an initial reading operation of reading the TOC recorded in the lead-in area RIA of the compact disc 31, the control circuit 50 controls the switch circuit SWI to connect the common contact 56 and the individual contacts 58. do. Oscillation times in this state! ? I41 is VCO circuit 39
A reference frequency signal of constant frequency 12 generated by the oscillation circuit 41 is applied to the three VCO circuits as a first clock signal CKI. This oscillation circuit 41 is a VC
The generated clock signal is sent from the PLL circuit 37 connected to the three O circuits to the frequency divider circuit 42 via the line 112.
will be sent to. The clock signal inputted to the frequency dividing circuit 42 is frequency-divided and branched to the frequency detection circuit 43 and the phase ratio axis circuit 44 as a second clock signal CK2 having a frequency F2.

The control circuit 50 also controls the switch circuit SW2 to connect the five common contacts and the individual contacts 61.

As a result, the frequency generated by the crystal oscillation circuit 46! A reference frequency signal of , is applied to the frequency dividing circuit 47. The reference frequency signal input to the frequency dividing circuit 47 is frequency-divided and output as a third clock signal CK3 of frequency F to the line 11.
4 to the phase comparator circuit 44.

Based on the input 220th clock signal CK2 and third clock signal CK3, the phase comparison circuit 44 outputs a voltage level corresponding to the phase difference to line /16. On the other hand, the frequency detection circuit 43 outputs to the line 115 a voltage level corresponding to the frequency F2 of the input second clock signal CK2. In this way, the output voltage level of the frequency detection circuit 43 and the output voltage level of the phase comparator circuit 44 are added to the line l17 and applied to the motor drive circuit 48, which rotationally drives the spindle motor 32.

The second signal input from the frequency dividing circuit 42 to the frequency detection circuit 43
The clock signal CK2 is supplied to the oscillation circuit 40 of the PLL circuit 37.
is connected to the VCO circuit 39, the frequency F'q7.
It has a frequency F, which is twice 35kHz, =2F. Therefore, a voltage level twice as high as the output voltage level during normal reproduction operation is outputted to line 117. Motor drive circuit 4
8 provides the spindle motor 32 with a drive control signal corresponding to this inputted double output voltage level.

In this way, the circumferential speed of the compact disc 31 is rotationally driven by the spindle motor 32 so that recorded data is reproduced at twice the speed of the normal reproduction operation.

As mentioned above, the initial reading operation I of the compact disc 31
When performing Y, the control circuit 50 switches the switch circuits SWI, S
By controlling W2, the frequency f2 = 2, which is twice the frequency of normal playback operation.
By connecting the oscillation circuit 41 that generates f, to the ■C○ circuit 39, and the crystal oscillation circuit 46 that generates twice the frequency f,=2f, to the frequency dividing circuit 47, the TOC etc. The speed of reading the second data can be increased to 2f&.

In addition, the control circuit 50 also connects the individual contacts 58 of the switch circuit SWI to the common contact 56 to reproduce the first data desired by the operator using the input means 51, so that the oscillation circuit 41 A first clock signal CKI having a generated frequency f2=2f is applied to the VCO circuit 39. Further, the control circuit 50 controls the switch circuit S W 2 to connect the crystal oscillation circuit 46 to the frequency dividing circuit 47 . As a result, the circumferential speed of the compact disc 31 is doubled, and the speed at which the second data such as subcodes recorded on the compact disc 31 is read is doubled, similar to the P4 self of the initial reading operation described above. be enhanced.

FIG. 2 is a block diagram showing the basic configuration of a compact disc playback device 80, which is another embodiment of the present invention. The configuration of the compact disk playback device 80 of this embodiment is similar to the structure of the compact disk playback device 30 shown in FIG. The explanation thereof will be omitted. The reproduction signal of the optical big adder from the compact disk 31 which is rotationally driven in the direction of the arrow R by the spindle motor 32 passes through the level slice circuit 34 and the waveform shaping circuit 35, whereby irregularities in the center level of the waveform are corrected. At the same time, a reproduction signal shaped into a square wave is applied to the PLL circuit 37 via the line 121.

The PLL circuit 37 of the compact disc playback device 80 of this embodiment includes a phase comparison circuit 38, a vCO circuit 39, an oscillation circuit 62, a frequency division circuit 63, and a switch circuit SW3.
It consists of: The switching mode of the switch circuit SW3 is determined according to the playback mode of the compact disc 31, which will be described later, and is switched by the control circuit 50.

Switch circuit SW3 has a common contact 67 and individual contacts 68.6
It has 9. With the common contact 67 connected to the individual contact 68, the oscillation circuit 62 is connected to the CO circuit 39 via the line 128. Therefore, the reference frequency signal generated by the oscillation circuit 62 is applied to the VC without being divided.
It is directly applied to the O circuit 39 as the first clock signal CKI.

Also, the common contact 67 of the switch circuit SW3 is the individual contact 69.
When the oscillation circuit 62 is connected to the three CO circuits via the frequency dividing circuit 63, the oscillation circuit 62 is connected to three CO circuits. Therefore, the reference frequency signal generated by the oscillation circuit 62 is
At step 3, the frequency is applied to the vCO circuit 39 as a first clock signal CK1 whose frequency is divided by, for example, 1/2.

The first tally signal CK is applied to the VCO circuit 39 according to the switching mode of the switch circuit SW3.
A clock signal is generated based on I and the first data and second data input to the PLL circuit 37 via the line N21, and is provided to the frequency divider circuit 42. This clock signal is passed to the frequency divider circuit 42 to generate a 220th clock signal C, which has a frequency divided by 6 for every 588 bits constituting one frame of data recorded on the compact disc 31.
The frequency is divided into K2 and branched and applied to a frequency detection circuit 43 and a phase comparison circuit 44.

On the other hand, the third tarlock signal CK3 is transmitted to the crystal oscillation circuit 66.
, the frequency division ratio of the 6 frequency divider circuit 64 and the frequency divider circuit 65 generated by the switch circuit SW4 and the frequency divider circuit 6465 is as follows.
It is set in accordance with the frequency of the clock signal applied from the oscillation circuit 62 of the PLL circuit 37 to the VCO circuit 39 via line /28 and the frequency of the clock signal applied via the frequency divider circuit 63. Therefore, the switch circuit S
Corresponding to the manner in which the common contact 67 of W3 is connected to six individual contacts, the common contact 70 of switch circuit SW4 is connected to individual contacts 71. In this state, the clock signal generated by the crystal oscillator circuit 66 is frequency-divided by the frequency divider circuit 64 and applied to the phase comparator circuit 44 via the line 124 as a third clock signal CK3.

On the other hand, corresponding to the mode in which the common contact 67 of the switch circuit SW3 is connected to the individual contact 68, the switch circuit SW4
A common contact 70 is connected to an individual contact 72 . In this state, the tarlock signal generated by the crystal oscillation circuit 66 is frequency-divided by the frequency dividing circuit 65 to generate the third clock signal CK3.
The signal is applied to the phase comparison circuit 44 via line 124 as a signal.

Therefore, the phase comparison circuit 44 receives the second clock signal CK2 input via the line 123 and the second clock signal CK2 inputted via the line 123.
A voltage level corresponding to the phase difference is output to line 126 based on the third tarlock signal CK3 inputted via the line 126. The frequency detection circuit 43 also receives the input second signal.
A voltage level corresponding to the frequency of clock signal CK2 is output on line 125. In this way, the frequency detection circuit 43
The output voltage level of the phase comparison circuit 44 and the output voltage level of the phase comparison circuit 44 are added to the line 127 and applied to the motor drive circuit 48. The motor drive circuit 48 rotates the spindle motor 32 at a rotation speed corresponding to the input voltage level.

The above-mentioned switch circuit SW3. The switching mode of SW4 is controlled by the control circuit 50 in accordance with the initial reading operation of the compact disc 31 or the search operation instructed by the input means 51. For the third clock signal CK3 output to the line 124, the frequency dividing circuit 42
The second clock signal CK2 is output on line 123.
The rotational speed of the compact disc 31 is controlled so that the values match.

For example, if the frequency dividing ratio of the frequency dividing circuit 63 is 1/2, the frequency dividing circuit 63
Assume that the frequency division ratio of 4 is 1/2 of the frequency division ratio of the frequency divider circuit 650. Normal reproduction operation f1: Dark, that is, a reproduction operation of reading the first data recorded on the compact disc 31 is performed! 4.6, switch times I'f! rsW3. S
W4 is controlled by the control circuit 50 in the manner shown by the solid line. In this switching mode, the tarok signal output from the PLL circuit 37 to the frequency dividing circuit 42 has a frequency f'-
p4.3218MHz, and when it is divided by the frequency divider circuit 42 and output to the line 123, the frequency F'
-F7° is reduced to a second tally signal CK2 having a frequency of 35 kHz.

On the other hand, the third tarlock signal CK3 outputted from the crystal oscillation circuit 66 to the line 124 via the frequency dividing circuit 64 has a reference frequency F o =7, 35 kHz.

Therefore, the rotational speed of the compact disc is controlled so that the second clock signal CK2 and the third clock signal CK3 input to the phase comparator circuit 44 match.

For example, the compact disc 31 may be
When a search operation for specific first data recorded in is instructed, the control circuit 50 switches the switch circuit SW3. Switching of SW4 also changes the state to the state shown by the broken line. In this state, the clock signal generated by the oscillation circuit 62 is not frequency-divided by the frequency dividing circuit 63 and is directly applied to the three vCo circuits as the first tally signal CKI via the line t28. Therefore, the line 12 is connected to the frequency divider circuit 42.
The clock signal provided via 2 is the 2
It has twice the frequency 2f, and the line 1 is connected to the phase comparator circuit 4/1.
The second clock signal CK2 provided via 23 also has a frequency 2F which is twice as high as that in normal operation.

On the other hand, the clock signal generated by the crystal oscillation circuit 66 is frequency-divided by the frequency dividing circuit 65 and output to the line 24. Since the frequency division ratio of the frequency division circuit 65 is twice that of the frequency division circuit 64, the third clock signal CK3 outputted to the line I24 is equal to the frequency division ratio of the frequency division circuit 64. It has twice the frequency 2Fu. Therefore, the phase comparator circuit 44 has twice the input frequency 2.
F.

2Fo exists in the second clock signal CK 2 and the third clock signal CK 2
Based on the signal CK3, a voltage level corresponding to the phase difference is output to the line 1!26.

On the other hand, the frequency detection circuit 43 outputs to the line 125 a voltage level corresponding to the frequency 2F of the input second clock signal CK2. In this way, the output voltage level of the frequency detection circuit 43 and the output voltage level of the phase comparator circuit 4.1 are added to the line 127 and sent to the motor drive circuit 48. The motor drive circuit 48 rotationally drives the spindle motor 32 so that the compact disc 31 rotates at a rotation speed corresponding to the input voltage level, that is, twice the circumferential speed as compared to the normal first data reproducing operation. .

When the initial reading operation or the cerner movement ('f=) is performed in this way, the second data is read from the compact disc 31 under CLV control so that the circumferential speed of the compact disc 31 is doubled. A read is made.

Therefore, according to the compact disc playback device 80 according to the present invention, the second data can be processed at twice the speed, and the time required for the processing is halved. This realizes a high-speed initial reading operation and a high-speed search operation, thereby improving operability.

Compact disc recycling bag w3o according to the present invention as described above
, so, the speed in the circumferential direction of the compact disc 31 when reading the second data is twice the speed when reading the first data, but there is no need to limit it to this. The object of the present invention can be achieved if the speed at which the second data is read is increased more than the speed at which the first data is read by providing an oscillation circuit, a switch circuit, or a frequency divider circuit.

In the above embodiment, the case where the data reproducing apparatus of the present invention is applied to the compact disc reproducing apparatus 30.80 is explained, but the first data of the number Pi is recorded together with the second data related to this first data. The present invention can be broadly implemented in data reproducing apparatuses such as DAT, which reproduces the first data and second data from the recorded recording medium.

Effects of the Invention According to the present invention, the first data and the second data from the recording medium
The data reading speed can be set to a desired speed, and it is also possible to perform the first data reading speed and the second data reading speed at different speeds. Therefore, for example, when playing a compact disc, for example, first data such as an acoustic signal whose reading speed is specified in advance, the reading speed is not particularly specified and can be read at any speed. , the second data related to the first data can be read at a speed higher than the traveling speed of the recording medium when reading the first data.

As a result, the second data can be read quickly to quickly obtain information related to the first data, and the reading means can be quickly brought into a state where it can read the desired first data. Furthermore, by increasing the reading speed of the second data, the overall reading time for reading the first data and the second data recorded on the recording medium is shortened, and the operability of the data reproducing device is significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a compact disc playback device 30 which is an embodiment of the present invention, and FIG. 2 is a block diagram showing the basic configuration of a compact disc playback device 80 which is another embodiment of the present invention. FIG. 3 is a block diagram showing the basic configuration of a conventional converter disc playback device W11. 1.30.80...Compact disc playback device, 2
．． 31... Compact disc, 3.32... (spindle) motor, 4.33... Optical pickup, 8
．． 37... Phase-locked loop (PLL) circuit,
11,40,41.62...Oscillation circuit, 13°43.
...Frequency detection circuit, 14.44...Phase comparison circuit,
15,45,46.66...Crystal oscillation circuit, 16.4
7.63... Frequency divider circuit, 19° path, 23.54...
(Feed) motor, 3... 1st to 3rd clock signals, I
. F,,Fco F,... (reference) frequency, 11...
switch circuit

Claims (1)

[Scope of Claims] A plurality of first data and second data related to the first data are recorded from a recording medium in a first data recording area and a second data recording area, respectively. A data reproducing device for reproducing two data, comprising: a reading means for reading the first data and the second data from a recording medium; a first signal generating means for generating a plurality of predetermined types of reference frequency signals; and the first signal generating means. a second signal generating means that generates a signal of a predetermined frequency corresponding to the type based on the output of each type of means, first data and second data; and an output of the first signal generating means. and a third signal generating means for generating a plurality of predetermined types of reference frequency signals corresponding to each type of the reference frequency signal, and a third signal generating means for generating a plurality of predetermined types of reference frequency signals, A data reproducing device characterized in that the running speed of a recording medium is controlled so that frequencies and phases match.