JPH07109711B2 - Dynamic random access memory - Google Patents

Description

The present invention relates to a dynamic random access memory (hereinafter referred to as "dynamic random access memory").
The term "DRAM" refers to, in particular, the bit line (1/2) _{Vcc is} a CMOS DRAM that employs a precharge method.

[Conventional technology]

FIG. 6 shows the configuration of the bit line and sense amplifier of the conventional DRAM shown in, for example, Digest of Technical Papers p.252-253 of the International Solid State Circuit Conference (ISSCC'85). Then bit line BLj and ▲ ▼
About, only the main part is shown. In the figure,
Q _j1 , Q _j2 and Q _j3 , Q _j4 are an N-channel MOSFET and a P-channel MOSFET which form an N-channel sense amplifier NSA and a P-channel sense amplifier PSA, respectively.
Bit line BLj is connected to the drain of Q _j1
A bit line ▲ ▼ is connected to the drains of _j2 and Q _j4 . Further, the gates of the FETs Q _j1 and Q _j3 are connected to the bit line ▲ ▼, and the gates of the FETs Q _j2 and Q _j4 are connected to the bit line BLj. Also, FET Q _j1 and Q
_The sense amplifier drive signal φ _N is connected to the source of _j2 ,
The FET Q _j3 and Q _j4 sources have a sense amplifier drive signal φ
_P is connected.

The sense amplifier drive signal φ _N is connected to the drain of the sense amplifier drive N-channel MOSFET Q _SN , the sense trigger signal S _N is connected to the gate, and the source is the ground potential V _SS.
It is connected to the. Further, the sense amplifier drive signal φ _P is connected to the drain of the P-channel MOSFET Q _SP for driving the sense amplifier.
However, the sense trigger signal S _P is connected to the gate, and the source is connected to the power supply potential V _CC . Further, WL _i is a word line, and Q _Sij and C _Sij are FETs and capacitors which form the memory cell M _ij . Q _j5 is the bit line BLj and ▲
▼ _Equalizing MOSFET for equalizing and, Q _j6
And Q _j7 are FETs for precharging the bit lines BLj and ▲ ▼ to the bit line precharge potential V _BL , and Q _j5 , Q _j6
An equalizing signal EQ is connected to the gates of Q _jn and Q _jn , respectively. Here, the bit line precharge potential V _BL is
Intermediate of normal power supply potential V _CC and ground potential V _SS , that is, (1/2) V
Selected as _CC . Yj is a column address selection signal, Q _j8 and Q
_j9 is a transfer FET, and the selected bit line BLj and ▲
Switching between ▼ and input / output line I / O and ▲ ▼.

Next, regarding the operation of the dynamic random access memory configured as described above, FIG. 6 and an operation waveform diagram thereof in the case of reading the stored contents of the capacitor C _sij of the memory cell M _ij of FIG. Description will be given with reference to the drawings. It is assumed here that the storage content of the capacitor C _sij is “1”.

External ▲ ▼ signal shown in Fig. 7 (Ext. ▲ ▼
(Referred to as a signal) and the falling edge activates the DRAM. When the active state is entered, the external row address signal is latched inside the chip due to the fall of the Ext. ▲ ▼ signal. Next, the equalization signal EQ becomes low level, the equalization of the bit lines BLj and ▲ ▼ is stopped, and at the same time, the bit line precharge potential V _BL and the bit lines BLj and ▲ ▼ are stopped.
▼ and are disconnected.

Next, the word line selected according to the row address latched inside the chip becomes high level. In Figure 6, WL _i
Is selected. F when word line WL _i goes high
ETQ _sij is turned on and the charge stored in the capacitor Q _sij is transferred to the bit line BLj, and the potential of the bit line BLj is the bit line potential at the time of equalization, that is, the bit line precharge potential V
_It will be higher than _BL . Next, by setting the sense trigger signal S _N high and S _P low, the FETs Q _SN and Q _SP
Is turned on, the sense amplifier drive signal φ _N becomes low level, and φ _P becomes high level. As a result, the N-channel (first sense amplifier) NSA and the P-channel sense amplifier (second sense amplifier) PSA operate, the potential difference between the bit lines BLj and ▲ ▼ is amplified, and the bit line BLj is The stored content “1” of the capacitor C _sij is read.

Next, the column address selection signal goes high. When the bit lines BLj and ▲ ▼ are selected, the column address signal Yj becomes high level, and the bit lines BLj and ▲
The data of ▼ is transferred to the input / output line I / O and ▲ ▼ through the transfer _FETs Q _j8 and Q _j9 .

Next, when the DRAM enters the inactive state at the rising edge of the Ext. ▲ ▼ signal, the Ext. ▲ ▼ signal goes high, and then the selected word line WLi goes low and the FET
Q _sij turns off. Next, the sense amplifier trigger signal S _N goes low and S _P goes high. Next, when the equalize signal EQ becomes high level, the sense amplifier drive signal φ _N changes from low level to intermediate level, and φ _P changes from high level to intermediate level. In the case of this example, the intermediate level between φ _N and φ _P is a potential equal to the bit line precharge potential V _BL by a circuit (not shown). Further, since the equalizing signal EQ becomes high level, the bit lines BLj and ▲ ▼ which have been at the power supply voltage V _CC and the ground potential V _SS during the read operation are equalized to (1/2) V _CC potential at the same time. , The bit lines BLj and ▲ ▼ are connected to the bit line precharge potential V _BL to set the potentials of the bit lines BLj and ▲ ▼ to V _BL equal to (1/2) V _CC .

As described above, in the conventional DRAM CMOS dynamic sense amplifier, in order to prevent the bit line precharge potential from fluctuating due to a leak current or the like in the DRAM inactive state, the bit line is precharged to the bit line precharge potential V _BL. To prevent fluctuations in the potential. Further, in the above-mentioned conventional example, the sense amplifier driving signal holding means (not shown) holds N
Channel and P channel sense amplifier drive signal φ _N
And φ _P are kept at the bit line precharge potential V _BL . As a result, the bit line and the sense amplifier drive signal are kept at the same potential.

However, as shown in the structure of the conventional DRAM of FIG. 8, many bit line pairs, sense amplifiers, etc. are arranged in the DRAM chip, and the bit line precharge potential is increased.
Since V _BL and the sense amplifier drive signals φ _N and φ _P are shared by these many bit line pairs and sense amplifiers, the wiring length of the bit line precharge potential V _BL and the sense amplifier drive signal becomes long. Therefore, as described above, the bit line BLj
And ▲ ▼ and the sense amplifier drive signals φ _N and φ _P are connected to the bit line precharge level V _BL outside the portion where a large number of bit line pairs and sense amplifiers are arranged (hereinafter referred to as the array portion). The number of wirings crossing the wirings for the bit line precharge potential V _BL and the sense amplifier driving signals φ _N and φ _P increases, and the noise easily occurs due to capacitive coupling with these wirings.

When such noise causes the N-channel sense amplifier drive signal φ _N to drop further below the potential lower by the threshold voltage of the N-channel FET than the precharge potential of the bit line, or the P-channel sense amplifier drive signal φ _P becomes P for the precharge potential of the line
If the potential rises higher than the absolute value of the absolute value of the threshold voltage of the channel FET, it is unnecessary to activate the sense amplifier as shown in, for example, Proceeding Paper No. 439 of the General Conference of the Institute of Electronics and Communication Engineers, 1982. Early or
There has been a problem that sensitivity deterioration of the sense amplifier is likely to occur due to variations in characteristics of transistors forming the sense amplifier.

As a method for solving some of these problems, for example, there is one disclosed in JP-A-54-8430, which is shown in FIG. The figure shows a sense amplifier section composed of only N-channel transistors. In addition to the FETs Q ₁ and Q ₂ forming the sense amplifier, the bit line BL and ▲
FET Q ₃ and Q ₄ between ▼ and the sense amplifier drive signal φ _N
Is provided. As a result, the bit lines BL and ▲ ▼ and the sense amplifier drive signal φ _N are made to have the same potential in the immediate vicinity of the sense amplifier in the inactive state of the DRAM, so that the above sense amplifier is activated too early. Is avoided. In FIG. 9, Q ₅ and Q ₆ are sense amplifier activation FETs, and Q ₇ and Q ₈ are precharge FETs.

By the way, when the sense amplifier section is composed of only N-channel transistors as in the example of FIG. 9, the bit line is normally precharged to the power supply potential V _CC . Since the precharging FETs Q ₇ and Q ₈ are usually provided for each sense amplifier, the power supply potential V _CC is necessarily wired in the array section.
However, in the case of the CMOS sense amplifier, it is necessary to wire the bit line precharge potential V _BL in the array section by some method as described above. However, in this case, the wiring as shown in FIG. 6 causes the above problems due to noise.

[Problems to be solved by the invention]

The present invention has been made to solve the above problems, and an object thereof is to obtain a dynamic random access memory having a highly sensitive CMOS sense amplifier and a bit line which are not affected by manufacturing process fluctuations and internal noise. To do.

[Means for solving problems]

The dynamic random access memory according to the present invention,
A plurality of word lines, a plurality of bit line pairs, an equalizing MOSFET provided for each bit line pair, a memory cell provided at each intersection of the word line and the bit line, and each bit line pair. Amplify the stored information of the memory cell read to the bit line pair provided for each of the N-channel first and
In a dynamic random access memory including a first sense amplifier including a second MOSFET and a second sense amplifier including P-channel third and fourth MOSFETs, a drain and a source are the first or second MOSFET
Of the first gate connected to the drain and source of
A N-channel fifth MOSFET connected to the signal of, or a P-channel fifth MOSFET whose drain and source are respectively connected to the drain and source of the third or fourth MOSFET and whose gate is connected to the second signal. One of the first or second sense amplifiers is provided, and the drive signal of the sense amplifier provided with the fifth MOSFET is supplied to the power supply potential and the ground potential via the first switching means. It is configured to be connected to an intermediate potential of.

[Action]

In the present invention, the sense amplifier portion is provided with means for making the bit line and the drive signal of the sense amplifier have the same potential in the sense amplifier portion, and means for equalizing the bit line pairs forming the bit line pair. Since the precharge potential of the line is supplied into the array section through the drive signal wiring of the sense amplifier, malfunction of the sense amplifier is prevented even if the precharge potential of the bit line receives noise, and its high sensitivity Is guaranteed.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a DRAM bit line pair and a CM according to an embodiment of the present invention.
It is a figure which shows the structure of OS sense amplifier. The figure shows the case where the N-channel sense amplifier and the P-channel sense amplifier are arranged separately. In the figure,
Q _j1, Q _j2 and Q _j3, Q _j4 is an N-channel MOSFET and a P-channel MOSFET constituting the N-channel sense amplifier NSA and P-channel sense amplifier PSA, the FETs Q _j1 and
Bit line BLj is connected to the drain of Q _j3 , and FET Q _j2
And the bit line ▲ ▼ is connected to the drain of Q _j4 . In addition, the gates of _FETs Q _j1 and Q _j3 have bit line ▲
▼ is connected, and the bit line BLj is connected to the gates of the _FETs Q _j2 and Q _j4 . Further, the sense amplifier drive signal φ _N is connected to the sources of the _FETs Q _j1 and Q _j2 , and the sense amplifier drive signal φ _P is connected to the sources of the _FETs Q _j3 and Q _j4 . Also, N channel MOSF for driving sense amplifier
The drain of ETQ _SN sense amplifier driving signal phi _N is the sense trigger signal S _N is connected to the gate is connected to the source ground potential V _SS. The sense amplifier drive signal φ is applied to the drain of the P-channel MOSFET Q _SP for driving the sense amplifier.
_The sense trigger signal S _P is connected to _{P 2} and the gate, and the source is connected to the power supply potential V _CC .

Q _j10 is an N-channel MOSF for _making the bit line ▲ ▼ and the N-channel sense amplifier drive signal φ _N have the same potential.
ET (fifth MOSFET), the drain of FETQ _J10 is connected to the bit line ▲ ▼, the source is connected to the N-channel sense amplifier drive signal φ _N , and the gate is connected to the sense amplifier pull-up signal (first MOSFET). Signal) connected to BH.

WLi is a word line, and Q _Sij and C _Sij are FETs and capacitors that form the memory cell M _ij . Q _j5 is the bit line BLj
It is a FET that equalizes and ▲ ▼, and an equalize signal EQ is connected to its gate. Yj is a column address selection signal, Q _j8 and Q _j9 are transfer EETs, and perform switching between the selected bit lines BLj and ▲ ▼ and the input / output lines I / O and ▲ ▼. FET
Q _BN switches between the bit line precharge potential generation circuit 10 and the N channel sense amplifier drive signal φ _N
It is a FET (first switching means), and a precharge signal PR is connected to its gate.

Next, regarding the operation of the dynamic sense amplifier configured as described above, in the case of reading the stored contents of the capacitor C _sij of the memory cell of FIG. 1, refer to FIG. 1 and its operation waveform diagram, FIG. While explaining. Here, it is assumed that the storage content of the capacitor C _sij is “1”.

The falling edge of the Ext. ▲ ▼ signal shown in Fig. 2 causes the DRAM to
Enters the active state. When you enter the active state, Ext. ▲ ▼
An external row address signal due to the falling edge of the signal is latched inside the chip.

Next, equalize signal EQ, sense amplifier pull-up signal B
H and precharge signal PR go low. Next, the word line selected according to the row address latched inside the chip becomes high level. In FIG. 1, it is assumed that WLi is selected. When the word line WLi goes high, the _{FET Q sij} turns on and the charge stored in the capacitor C _sij becomes the bit line BL.
The potential of the bit line BLj is transferred to j and becomes higher than the bit line potential at the time of equalization, that is, the bit line precharge potential V _BL . Next, the FET Q _SNP and Q _SP are turned on by setting the sense trigger signal S _N to high level and S _P to low level, and the sense amplifier drive signal φ _N becomes low level,
φ _P goes high. As a result, the N-channel and P-channel sense amplifier drive signals φN and φP operate, the potential difference between the bit lines BLj and ▲ ▼ is amplified, and the potential of the bit line BLj is V _CC and the bit line ▲.
The potential of ▼ becomes V _SS , and the stored content “1” of the capacitor C _sij is _{continuously output} to the bit line BLj.

Next, the column address selection signal goes high. When the bit lines BLj and ▲ ▼ are selected, the column address signal Yj becomes high level, and the bit lines BLj and ▲
The data of ▼ is transferred to the input / output line I / O and ▲ ▼ through the transfer _FETs Q _j8 and Q _j9 .

Next, after the Ext. ▲ ▼ signal goes high, the selected word line WLi goes low and the _{FET Q sij} turns off. Next, the sense amplifier trigger signal S _N goes low, S _P goes high, and the equalize signal EQ goes high, so that the bit lines BLj and ▲ ▼
And are equalized, and the potential becomes (1/2) V _CC . At this time, the N-channel sense amplifier drive signal φ _N is FETQ
Precharged to (1/2) V _CC −V _THN through _i1 and Q _j2 , and P channel sense amplifier drive signal φ _P is precharged to (1/2) V _CC + | V _THP | through _FET Q _j3 and Q _j4 To be done. Here, V _THN and V _THP are threshold voltages of the N-channel and P-channel FETs, respectively.

Next, when the sense amplifier pull-up signal BH goes high, the N-channel sense amplifier drive signal φ _N changes to _{FETQ j10.}
Is precharged to (1/2) V _CC through. Further, the precharge signal PR becomes high level, the bit line precharge potential generation circuit 10 is connected to the N-channel sense amplifier drive signal φ _N, and the potential of φ _N becomes equal to V _BL . At this time, V _BL is also supplied to the bit line _{BL i} through the _{FET Q j10} . In addition, _{FETQ j5} allows bit line BLj and ▲ ▼
_Are connected to the bit line BLj through _{FETQ j5.}
Also becomes V _BL . Here, in the present invention, the bit line precharge potential generation circuit 10 includes the bit line pair BLj and ▲ which are at high level and low level after reading.
This is not for returning ▼ to the precharge potential, but for compensating so that the potential of the bit line does not deviate from the precharge level after the potentials of the bit line pair BLj and ▲ ▼ are made equal by equalization. .

Therefore, even if the bit line potential fluctuates due to noise in this state, the transistor Q _j10 provided for each sense amplifier section makes the bit line potential and the sense amplifier drive signal the same potential, which is a problem in the conventional device. However, the premature sense operation and the sensitivity deterioration of the sense amplifier can be solved without increasing the chip size. Further, in the conventional DRAM shown in FIG. 6, three MOSFETs Q are provided for each bit line BLj and ▲ ▼ forming a folded bit line pair.
_{Although j5} , Q _j6 and Q _j7 are required, according to the present invention, the bit lines BLj and ▲ forming a folded bit line pair are
It is possible to supply the precharge potential V _BL by the two _MOSFETs Q _j5 and L _j10 to ▼, and the increase in chip size can be minimized.

In the above embodiment, the case where the precharge potential of the P-channel sense amplifier drive signal φ _P is (1/2) V _CC + | V _THP | has been described, but as shown in FIG. Part, a P-channel MOSF that makes the bit line and the P-channel sense amplifier drive signal φ _{P the} same potential
ET (potential setting means) Q _j12 and Q _j13 are provided, and their gates are inverted signals of the sense amplifier pull-up signal BH ▲ ▼
May be set so that the precharge potential of the P-channel sense amplifier drive signal φ _P becomes equal to V _BL .

Also, as shown in FIG. 4, the bit line precharge potential
V _BL generation circuit and P channel sense amplifier drive signal φ _P
And for switching MOSFET (second switching means)
Connect via Q _BP and precharge signal PR to its gate
May be connected so that the precharge potential of the P-channel sense amplifier drive signal φ _P becomes equal to V _BL .

Further, in the above-described embodiment, the case where the N-channel sense amplifier and the P-channel sense amplifier are arranged separately has been described, but they may be arranged adjacent to each other, and the same effect as that of the above-described embodiment is obtained. .

Further, in the above embodiment, the case where the equalize signal EQ, the sense amplifier pull-up signal BH and the precharge signal PR are different signals has been described, but some or all of them may be the same signal. Of course, the same effect as that of the above-mentioned embodiment is obtained.

Further, in the above embodiment, the case where the switching means for connecting the bit line precharge potential generation circuit and the sense amplifier drive signal is the N-channel MOSFET has been described, but other configurations may be used, and the control signal may be changed appropriately. By selecting, the same effect as that of the above embodiment can be obtained.

In the above embodiment, the bit line and the sense amplifier drive signal are set to the same potential in the N channel sense amplifier portion.
Although the case where the channel MOSFET is provided and the bit line precharge potential generating circuit is connected to the N-channel sense amplifier drive signal through the switching means has been described, by appropriately selecting the operation waveform of the sense amplifier pull-up signal. As shown in FIG. 5, a P-channel MOSFET (fifth MOSFET) is provided in the P-channel sense amplifier section so that the bit line precharge potential generation circuit 10 and the P-channel sense amplifier drive signal φ _P are connected. Of course, the same effect as that of the above-described embodiment can be obtained.

〔The invention's effect〕

As described above, according to the dynamic random access memory according to the present invention, a plurality of word lines, a plurality of bit line pairs, and equalizing for each bit line pair are provided.
N channel for amplifying stored information of a MOSFET, a memory cell provided at each intersection of a word line and a bit line, and a memory cell read for the bit line pair provided for each bit line pair In a dynamic random access memory comprising a first sense amplifier composed of first and second MOSFETs and a second sense amplifier composed of third and fourth P-channel MOSFETs. Alternatively, the drain and source of the second MOSFET are respectively connected and the gates thereof are connected to the first signal of the N channel, or the drain and the source are the third or fourth.
The fifth MO of the P-channel, which is connected to the drain and source of the MOSFET and the gate is connected to the second signal.
One SFET is provided in the first or second sense amplifier, and the drive signal of the sense amplifier provided with the fifth MOSFET is supplied to the power supply potential via the first switching means. Since it is configured to be connected to an intermediate potential of the ground potential, there is an effect that a DRAM having a CMOS sense amplifier with a large margin against internal noise and manufacturing process variation can be obtained without increasing the chip size.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bit line pair and a CMOS sense amplifier of a dynamic random access memory according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram showing an operation of the first switching means, and FIG. FIG. 4 is a block diagram showing another embodiment of the invention, FIG. 4 is a block diagram showing still another embodiment of the present invention, FIG. 5 is a block diagram showing still another embodiment of the present invention, and FIG. Showing the configuration of the bit line pair and the CMOS sense amplifier of the dynamic random access memory of FIG. 7, FIG. 7 is an operation waveform diagram showing the operation of FIG. 6, and FIG. 8 is the configuration of the array section of the conventional dynamic random access memory. FIG. 9 and FIG. 9 are diagrams showing a configuration of a bit line pair and an NMOS sense amplifier of another conventional dynamic random access memory. WLi …… word line, BLi, ▲ ▼ …… bit line pair, M _ij
...... Memory cell, Q _j5 …… _Equalizing MOSFET, Q _j1 ……
First MOSFET, Q _j2 ...... Second MOSFET, Q _j3 ...... Third MO
SFET, Q _j4 ...... Fourth MOSFET, Q _j10 , Q _j11 ...... Fifth MOSF
ET, Q _j12 , Q _j13 ... potential setting means, φ _N ... first sense amplifier drive signal, φ _P ... second sense amplifier drive signal, BH ... first signal, ▲ ▼ ... first 2 signal, V _CC
…… Power supply potential, V _SS …… Ground potential, Q _BN …… First switching means, Q _BP …… Second switching means, 10 ……
Bit line precharge potential generation circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (9)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs, an equalizing MOSFET provided for each bit line pair, and a memory cell provided at each intersection of the word line and the bit line, A first sense amplifier formed of N-channel first and second MOSFETs, which is provided for each bit line pair, and which amplifies stored information of the memory cell read to the bit line pair, and P
In a dynamic random access memory including a second sense amplifier including third and fourth MOSFETs of a channel, a drain and a source are respectively connected to a drain and a source of the first or second MOSFET, and a gate is the first. A N-channel fifth MOSFET connected to the signal of, or a P-channel fifth MOSFET whose drain and source are respectively connected to the drain and source of the third or fourth MOSFET and whose gate is connected to the second signal. A dynamic random access memory, characterized in that one is provided in the first or second sense amplifier. 2. A drive signal of a sense amplifier provided with the fifth MOSFET is connected to an intermediate potential between a power supply potential and a ground potential via a first switching means. The dynamic random access memory according to item 1. 3. The potential setting means for setting the drive signal of the sense amplifier, which is not provided with the fifth MOSFET, and the bit line pair to the same potential. Alternatively, the dynamic random access memory according to item 2. 4. The drive signal of the sense amplifier in which the fifth MOSFET is not provided is connected to an intermediate potential between the power supply potential and the ground potential via the second switching means. The dynamic random access memory according to any one of claims 1 to 3. 5. The intermediate potential between the power supply potential and the ground potential is
5. The dynamic random access memory according to claim 2, wherein the potential is equal to the precharge potential of the plurality of bit line pairs. 6. The method according to claim 1, wherein a timing at which the fifth MOSFET is turned on is later than a timing at which the equalizing MOSFET is turned on. Dynamic random access memory. 7. The method according to any one of claims 1 to 6, wherein the timing at which the first switching means is turned on is later than the timing at which the fifth MOSFET is turned on. The described dynamic random access memory. 8. The dynamic random access memory according to claim 2, wherein the first switching means is an N-channel MOSFET. 9. The dynamic random access memory according to claim 4, wherein the second switching means is an N-channel MOSFET.