JPH07107137A - Method and device for communication of multiplex transmission system - Google Patents

Abstract

PURPOSE:To constitute the device so that the system does not conduct a malfunction and the multiplex transmission of high reliability can be conducted, even in the case a fault is generated. CONSTITUTION:A multiple node 10 connected mutually to a multiple bus MB is provided with an ID table 21 for registering data ID of a necessary message, and a receiving buffer 22 for storing the data corresponding to the ID table, and when the message is fetched, whether the data ID exists in the ID table or not, and in the case it exists, the bit of a bit store area 22b of the receiving buffer is changed to a bit for showing that the data is stored, data corresponding to the data ID is stored in the receiving buffer, the bit in the bit store area is changed to the bit for showing that the data is stored, and also, when a CPU 12 reads out the data stored in the receiving buffer, the bit in the bit store area of the receiving buffer is confirmed, and after the data are read out, validity of the data is decided in accordance with the change of the bit in the bit store area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission system for transmitting a message via a multiplex transmission line, and more particularly to a communication method and apparatus of the multiplex transmission system for receiving data.

[0002]

2. Description of the Related Art Conventionally, in this type of multiplex transmission system,
There is one that has a plurality of multiplex transmission devices (hereinafter, referred to as "multiplex nodes") connected to a multiplex transmission path (hereinafter, referred to as "multiplex bus") and performs message transmission between the multiple nodes. The multiplex node is a communication control circuit (hereinafter, referred to as “LSI”) connected to a multiplex bus including a pair of electric wires.
Say. ) And a control circuit (hereinafter referred to as “CPU”).
And an input / output interface (hereinafter referred to as “I / F”) circuit.

The LSI receives the ID table for registering the data ID allocated to the data required by the own node, and the data that follows the received data ID in correspondence with the data ID in the ID table. The reception buffer is provided with a reception flag indicating whether or not data is received and a status bit indicating access prohibition of the CPU for each area.

When the data ID of the message received from the multiplex bus is the same as the registered data ID, the LSI accesses the reception buffer and the data I
When the status bit of the area corresponding to D is set to the high (Hi) state to store the data and the storage of the above data is completed, the status bit of the corresponding area is set to the low (Lo).
Set the status and reception flag to Hi status. This allows
The CPU periodically accesses the reception buffer at a predetermined timing, and when the reception flag is Hi, reads the data, sets the reception flag to the Lo state, and reads the read data. In accordance with this, load devices such as motors and actuators connected via the I / F circuit are controlled.

[0005]

However, in the above-mentioned multiplex transmission system, if the reception flag of the reception buffer is fixed at, for example, Hi due to a failure of the reception flag, the CPU is However, there is a problem in that an erroneous determination is made as if data reception is continuing, an abnormality of the own node cannot be detected, and fail safe control cannot be performed. Further, if the reception flag has been fixed to Hi since the power was turned on, there is a possibility that the undefined data in the reception buffer may be read as new data and may be used continuously. If the status bit of the receive buffer is fixed at Lo, for example, if it is fixed at Lo, the CPU reads the data and the LS
There occurs a situation in which new data is stored in the reception buffer due to I, and in such a case, the CPU cannot detect this situation and the contents of the data may be damaged.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a highly reliable communication method and apparatus for a multiplex transmission system without malfunctioning of the system even when a failure occurs. And

[0007]

In order to achieve the above object, according to the present invention, there are multiple nodes mutually connected to a multiplex bus, and the multiplex node is required among messages transmitted to the multiplex bus. It has an ID table for registering the data ID of the message and a reception buffer for storing the data corresponding to the ID table. When the message is fetched, it is judged whether or not the data ID exists in the ID table. In the receiving method of the multiplex transmission system for storing the data corresponding to the data ID in a predetermined receiving buffer, the multiplex node is a bit indicating that the CPU reads the data stored in the receiving buffer or the LSI stores the data in the receiving buffer. Has a bit storage area to store the received data in a predetermined receiving buffer corresponding to the data ID. When paid, change the bits of the bit storage area in the bit indicating the start storing data,
Regardless of whether the data stored in the reception buffer is read or not, the data corresponding to the data ID is stored in the reception buffer, and the bit in the bit storage area is changed to a bit indicating the end of data storage. To do. Also,
When reading the data stored in the predetermined reception buffer, the bit in the bit storage area corresponding to the predetermined reception buffer is confirmed, and after reading the data, the bits in the bit storage area are re-read. There is provided a communication method of a multiplex transmission system for confirming and determining the validity of the read data according to the confirmation result.

Further, the transmitting-side multiplexing node increments the value of a part of the data for each frame, and at the same time, sets the other part of the data to the inverted data of the part of the data. To send as.

[0009]

When the data of the message stored in the reception buffer is read out and some of the data does not increase for a certain period of time or more, the receiving-side multi-node receives the inverted data of the above-mentioned partial data and the other partial data. When the data are not equal, it is determined that the data is abnormal, the above message is discarded, and the fail safe control is performed.

Therefore, even if a failure occurs in the overwrite receiving buffer, the system does not malfunction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings of FIGS. FIG. 1 is a schematic configuration diagram showing an embodiment of a multiplex transmission system according to the present invention. In the figure, the multiplex nodes 10 to 30 are connected via a multiplex bus MB, and multiplex transmission of a frame-structured message is performed between the multiplex nodes. In an automobile multiplex transmission system, the multiplex nodes include, for example, a front multiplex node,
There are meter multiple nodes, rear multiple nodes, etc., and multiplex transmission of vehicle driving information for each message.

FIG. 2 (a) is a frame of a signal transmitted between the multiple nodes, and the frame is a message start code SOM (Start Of Messa) indicating the start of the message.
ge) and a priority MP indicating the priority of the message
(Message Priorty), an identification code TYPE indicating the type of the frame, an identification code DID (Data ID) indicating the content (function) of the data, a data area DF (Data Field) consisting of 8-byte data, and an error. Check code ER and data end area EOD indicating the end of data
(End Of Data) and ANC (Acknowledgement for Ne
twork Control) area and a message end code EOM (End Of Message) indicating the end of the message. Here, the ANC area is the reception response signal area of all the nodes connected to the network, and this area is divided into a plurality of time slots (1 bit each) as shown in FIG. 2 (b). In addition, each of the above time slots is assigned to each multiplex node of the network. That is, the time slots of the multi-nodes that are always connected to the multi-bus MB are specified and assigned to the ANC area, and the time slots of the multi-nodes that are newly connected to the multi-bus MB such as optional multi-nodes are allocated to the ANC. It is assigned to a specific area.

Therefore, when the multiplex node normally receives the message, it outputs the 1-bit ACK signal to the multiplex bus MB at the position of the time slot assigned to the own node in the ANC area in the message. Thereby, the transmitting multiplex node can know which node normally received the message transmitted by the own node, in other words, whether or not there is any multiplex node that could not normally receive the message.

Next, the configuration of the multi-node will be described. Since the configurations of the multi-nodes 10 to 30 are almost the same, the configuration of the multi-node 10 will be described here as a representative. The multi-node 10 is a multi-bus M including a pair of electric wires.
It is composed of an LSI 11 connected to B, a CPU 12, and an I / F circuit 13. As shown in FIG. 3, the LSI 11 has an ID table 21 for registering a data ID assigned to data required by its own node, and a data ID of a received message in a storage area 21a of the ID table. When the data ID is the data ID, the data following the received data ID is stored in association with the data ID, and the overwrite reception buffer 22 stores the data ID registered in the storage area 21b of the ID table. It has a reception buffer 23 for storing the data following the received data ID.

FIG. 4 is a diagram showing in detail the receive buffer of the LSI 11 according to the present invention. In the figure, an overwrite receiving buffer 22 includes an overwrite receiving buffer area 22a for storing 8-byte data corresponding to the storage area 21a of the ID table, and an LSI 11 and a CPU 1 for each area.
A bit storage area 22b for storing a semaphore bit for arbitrating the second access operation is provided. The reception buffer 23 is a reception buffer area 2 for storing 8-byte data corresponding to the storage area 21b of the ID table.
3a and a reception flag area 23b indicating whether or not data is received are provided for each area.

The bit storage area 22b is provided in the CPU 12
A semaphore indicating that the LSI 11 reads the stored data or the LSI 11 stores the data in the reception buffer 22.
Bits are stored. That is, for example, the LSI 11
When storing data, the LSI 11 stores the Lo level bit in the bit storage area 22b, and when the data storage is completed, the bit is changed to the Hi level bit.

The receiving buffers 22 and 23 both store the data following the received data ID. The difference is that the receiving buffer 22 for overwriting stores the data in the corresponding receiving buffer area 22a for overwriting. The content is rewritten regardless of whether the data (old data) is read or not, but in the reception buffer 23, the content of the corresponding reception buffer area 23a cannot be rewritten unless the corresponding reception flag 23b is cleared. .

The CPU 12 registers the data ID of the message required by its own node in the ID table 21. At this time, the CPU 12 registers the data ID of a message having a high appearance frequency in the storage area 21a of the ID table and the data ID of a message having a low appearance frequency in the storage area 21b of the ID table. In addition, the CPU 12
Reads data from the reception buffer area 22a at periodic timings. Here, for example, when the CPU 12 reads data from the overwrite reception buffer area 22a, the CPU 12 determines whether or not the corresponding bit storage area 22b is at the Hi level. Data is read from the reception buffer area 22a. Immediately after the reading, the CPU 12
Determines whether the bit in the bit storage area 22b has been changed, and if the bit has been changed to the Lo level bit, the content of the data has been corrupted by storing new data. There is a possibility that the read data will be invalidated. If there is no change in the bit of the bit storage area 22b (Hi level),
The load device is controlled according to the read data. It should be noted that when the bit storage area 22b is at the Lo level, the CPU 12 causes the corresponding overwrite receiving buffer area 2 to be overwritten.
It judges that access to 2a is impossible and waits until it becomes Hi level.

Next, the operation of the LSI 11 when an embodiment of the communication method of the multiplex transmission system according to the present invention is used will be described. First, when the LSI 11 receives the message, the LSI 11 compares the data ID of the message with the data ID registered in the ID table 21, and the data ID
To determine if they match.

When there is no matching data ID, the storage of the data corresponding to the received data ID is stopped. If there is a matching data ID in the storage area 21a of the ID table, it corresponds to this area 22a regardless of whether the data (old data) stored in the corresponding overwrite receiving buffer area 22a is read or not. The value of the bit storage area 22b is set to Lo, and the data received this time is sequentially written to the overwrite reception buffer area 22a. When the above writing is completed,
The value of the corresponding bit storage area 22b is set to Hi, and the CPU
12 enables the overwrite reception buffer area 22a to be accessed and transmits an ACK signal indicating confirmation of reception to the multiplex bus MB.

When there is a matching data ID in the storage area 21b of the ID table, the corresponding area 23b
It is determined whether the reception flag of is Hi or Lo. If the reception flag is Lo, the LSI 11 is a CPU
12 has finished reading the data stored in the receive buffer area 23a and determined that new data can be stored.
3a, and the reception flag of the corresponding area 23b is set to Hi. On the other hand, if the reception flag is Hi, the LSI 11
Determines that the reading of the data stored in the reception buffer area 23a by the CPU 12 is not completed, does not write the data to the reception buffer area 23a, and does not transmit the ACK signal.

The LSI 11 sends an interrupt signal to the CPU 12 only when the data is stored in the reception buffer 23 to make a data interrupt request. When the interrupt signal is input, the CPU 12 reads the latest data stored in the reception buffer 23, sets the reception flag of the corresponding area 23b to Lo, and controls the load device according to the read data.

The CPU 12 periodically reads data from the overwrite receiving buffer area 22a at a predetermined timing. That is, the CPU 12 determines whether the bit storage area 22b corresponding to the overwrite reception buffer area 22a for reading data is at the Hi level,
When the area 22b is at the Lo level, it becomes impossible to access the corresponding overwrite receiving buffer area 22a. When the area 22b is at the Hi level, the CPU 12 receives the corresponding overwrite reception buffer area 22a.
Read data from. Immediately after reading the data, the CPU 12 determines whether the bit in the bit storage area 22b has been changed. If the bit in the bit storage area 22b has been changed to the Lo level bit, Since there is a possibility that the contents of the data have been corrupted by the storage of new data, it is judged that the data is abnormal and the fail-safe control is performed. On the other hand, when the bit of the bit storage area 22b is not changed (Hi level), the CPU 12 controls the load device according to the read data.

Therefore, in this embodiment, a message having a high appearance frequency is stored in the overwrite receiving buffer, and new data is written in the overwrite receiving buffer even if it is not read by the CPU each time it is received. The load on the CPU can be reduced. Further, in this embodiment,
Only one semaphore bit indicates that the CPU reads the stored data or the LSI stores the data in the receiving buffer for overwriting, so that the status bit becomes unnecessary and the bit capacity of the receiving buffer can be reduced. it can.

When the communication method of the present embodiment is used for multiplex transmission in an automobile, the data corresponding to the data ID having a high appearance frequency is a cyclic signal output at a certain cycle, such as a vehicle speed signal. A sensor signal of a water temperature sensor or the like corresponds to the data, and data corresponding to a data ID having a low appearance frequency is, for example, an event-driven switch signal or the like.

Next, the operation of the LSI 11 when another embodiment of the communication method of the multiplex transmission system according to the present invention is used will be described. Here, the multi-node 20 is a transmission multi-node, and the LSI of the multi-node 20 is D
It is assumed that the message having the ID 01H is frame-structured and periodically transmitted to the multiplex bus MB, and D1 and D8 of the data area DF at this time are used as check data (see FIG. 2 (a)), and each time it is transmitted. The value of D1 is incremented by 1. For example, in this message, D1 = 12H
Is transmitted, D1 = 13H is transmitted in the next message. At the same time, D8 of the data area DF
Is the inverted data of D1.

As shown in FIG. 4, the multi-node 10 has I
When the ID of 01H is registered in the storage area 21a of the D table, and the LSI 11 receives the message of DID = 01H, first, the ID of 01H is registered.
The semaphore bit of the bit storage area 22b corresponding to the storage area 21a of the D table is set to Lo level. Next, the receive buffer area 2 of the corresponding overwrite receive buffer 22
The data of the message is written in 2a in the order of D1 to D8. When the writing is completed, the semaphore bit in the corresponding bit storage area 22b is set to Hi level.

The CPU 12 periodically reads data from the overwrite receiving buffer area 22a at a predetermined timing. That is, the CPU 12 checks the bit storage area 22b corresponding to DID = 0lH from which data is read, and determines whether the area 22b is at the Hi level. Here, when the area 22b is at the Lo level, it becomes impossible to access the corresponding overwrite receiving buffer area 22a. Then, the CPU 12 monitors the semaphore bit in the area 22b, and if the semaphore bit remains in the Lo level state for a certain period or more (for example, the period at which the multi-node 20 transmits data or more), it is determined to be abnormal. Judges and shifts to fail-safe control. Further, even when the read value of D1 does not increase for a certain period or more, it is determined that the data is abnormal, and the fail safe control is performed. Further, the CPU 12 monitors the read data of D1 and D8, and when (D1 data) ≠ (inverted data of D8), judges that the data is abnormal and discards the received message and shifts to fail-safe control. To do.

Further, the CPU 12 determines that the area 22b is Hi.
In case of the level, the data is read from the corresponding overwrite receiving buffer area 22a. Immediately after reading the data, the CPU 12 causes the bit storage area 22b
If the bit of the bit storage area 22b is changed to the Lo level bit, it is possible that the content of the data has been corrupted by the storage of new data. Therefore, it judges that the data is abnormal and discards the received message and shifts to the fail-safe control. On the other hand, when there is no change in the bit of the bit storage area 22b (Hi level), the CPU 12
Controls the load device according to the read data.

Therefore, in this embodiment, the transmitting multiplex node increments the value of D1 for each frame and at the same time transmits the data of D8 as the inverted data of D1, and the receiving multiplex node at the time of reading the data. To D1
If the value of does not increase for a certain period or more, or (reversed data of D1) ≠ (data of D8), it is determined to be abnormal, the received message is discarded, and fail-safe control is performed. As a result, in this embodiment, DID = 01H
Semaphore bit in area 22b corresponding to
Even if it is fixed to, by monitoring the semaphore bit and the received data, it is possible to detect abnormalities in the data, and also to keep using undefined data, thus constructing a highly reliable multiplex transmission system. be able to.

In this embodiment, a semaphore bit storage area is provided in the overwrite receiving buffer corresponding to the data ID, and the CPU stores the semaphore bit storage area in accordance with the value of the semaphore bit. Although the reading of the data or the storage of the data by the LSI is shown, the present invention can attach a reception flag indicating the reception of the data together with the storage area of the semaphore bit to the reception buffer for overwriting. In this case, CP
U can determine whether the reading of the data stored in the overwrite receiving buffer has already been completed. Further, the LSI stores the data received this time in the corresponding overwrite reception buffer regardless of the value of the reception flag.

Further, in the present embodiment, the message is transmitted while incrementing the value of D1 by 1, but the present invention is not limited to this, and the message can be transmitted while decrementing by 1, for example. . Further, the value of D1 may be increased or decreased by 2 or 10. However, if the data of D1 is alternately transmitted with the values of 00H and 01H, the timing at which the CPU of the receiving multiplex node reads the above data and the above-mentioned 0 by the transmitting multiplex node.
The transmission timing of 0H may be synchronized. In this case, D read by the CPU of the receiving multiplex node
All the data of 1 will be 00H, so the CPU
Has a problem of erroneously determining that the data is abnormal. Therefore, in the present invention, the CPU of the receiving multi-node is
Is periodically reading data at a predetermined timing,
If the value of D1 is set so as to always change and the message is transmitted, the abnormality of the data can be accurately determined.

In the present embodiment, data transmission is performed while changing the value of D1. However, the present invention is not limited to this, and any value of other data (D2 to D7) may be changed. Is also good. Furthermore, in the present embodiment, D8 is used as the inverted data of D1, but the present invention is not limited to this,
Any other data (D2 to D7) other than D1 may be used. However, since the LSI writes D1 first when storing data in the overwrite reception buffer, D1 and D1
It is preferable to combine 8 of them. In addition, D8
Is not necessarily the inverted data of D1 and may be any value that can be specified in combination with D1. For example,
A relationship such as D8 = D1 + 1 may be provided.

The values of D1 and D8 do not have to be 1 byte, and may be, for example, 1 to 7 bits or 9 bits or more. However, if the above value is set to 1 bit, D1
Since the data of and D8 are alternately transmitted as "0" and "1", the above-mentioned problems occur. The above value is 9
If it is set to more than bits, the data area that can actually be used will be reduced. Therefore, the values of D1 and D8 are preferably 2 to 8 bits, and more preferably 4 bits or 8 bits considering the ease of handling by the CPU.

In this embodiment, C of the receiving multi-node is
The PU reads the data stored in the overwrite receiving buffer 22 at a set predetermined timing. However, like the receiving buffer 23, when new data is received, the LSI sends an interrupt signal to the CPU. It is also possible to set to send.

[0036]

As described above, according to the present invention, the multiplex transmission device mutually connected to the multiplex transmission line is provided, and the multiplex transmission device among the messages transmitted to the multiplex transmission line.
It has a registration means for registering a data identifier of a required message and a data storage area for storing data corresponding to the registration means. When a message is fetched, it is judged whether or not the data identifier exists in the registration means, and it exists. in case of,
In a communication method of a multiplex transmission system, which stores data corresponding to the data identifier in a predetermined data storage area,
The multiplex transmission device has a bit storage area for storing a bit indicating reading of data stored in a data storage area or storage of data in the data storage area, and the received data is a predetermined data corresponding to a data identifier. When the data is stored in the storage area, the bit of the bit storage area is changed to a bit indicating the start of data storage, and the data stored in the data storage area corresponds to the data identifier regardless of whether the data is read. Data to be stored in the data storage area, the bit in the bit storage area is changed to a bit indicating the end of data storage, and when the data stored in the predetermined data storage area is read, Check the bit in the bit storage area corresponding to the data storage area, read the data, and then re-set the bit in the bit storage area. And certification, since determining the validity of data read said in response to the check result, even if a failure occurs, without causing the system to malfunction, it is possible to perform a highly reliable multiplex transmission.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a multiplex transmission system according to the present invention.

FIG. 2 is a diagram showing a structure of a frame of a signal transmitted between multiple nodes.

FIG. 3 is a configuration diagram showing a schematic configuration of a multi-node according to the present invention.

FIG. 4 is a diagram showing details of an overwrite receiving buffer shown in FIG.

[Explanation of symbols]

 10, 20, 30 Multiplex transmission device (multiple node) 11 Communication control circuit (LSI) 12 Control circuit (CPU) 13 Input / output interface circuit (I / F circuit) 21 ID table 21a, 21b ID table storage area 22, 23 Reception buffers 22a and 23a Reception buffer area 22b Bit storage area 23b Reception flag MB Multiplexed transmission path (multiplexed bus)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9371-5K H04L 13/00 307 Z

Claims (7)

[Claims] 1. A registration means for registering a data identifier of a necessary message among messages transmitted on a multiplex transmission line, the multiplex transmission device mutually connected to the multiplex transmission line. It has a data storage area for storing data corresponding to the registration means, and when a message is fetched, it is judged whether or not a data identifier exists in the registration means,
If present, in the communication method of the multiplex transmission system for storing the data corresponding to the data identifier in a predetermined data storage area, the multiplex transmission device reads the data stored in the data storage area or the data storage area. Has a bit storage area for storing a bit indicating the storage of data in the storage area, and when storing the received data in a predetermined data storage area corresponding to the data identifier, starts storing the bits in the bit storage area. Indicating that the data stored in the data storage area is read, the data corresponding to the data identifier is stored in the data storage area, and the bit in the bit storage area is set as the data. Change to a bit indicating the end of storage, and when the data stored in the predetermined data storage area is read, After confirming the bit of the bit storage area corresponding to the data storage area and reading the data, the bit of the bit storage area is confirmed again, and the validity of the read data is confirmed according to the confirmation result. A communication method of a multiplex transmission system, characterized by making a judgment. 2. A registration means for registering a data identifier of a required message among messages transmitted to the multiplex transmission line, the multiplex transmission device having mutually connected multiplex transmission lines. It has a data storage area for storing data corresponding to the registration means, and when a message is fetched, it is judged whether or not a data identifier exists in the registration means,
If there is, in the communication method of the multiplex transmission system for storing the data corresponding to the data identifier in a predetermined data storage area, the multiplex transmission device on the transmission side specifies at least a part of the data among the predetermined data. Transmitting after changing, the multiplex transmission device on the receiving side stores the received data in a predetermined data storage area corresponding to the data identifier, regardless of whether or not the data stored in the data storage area is read, A communication method for a multiplex transmission system, wherein an abnormality of data is judged according to a predetermined change of at least a part of the data. 3. A registration means for registering a data identifier of a required message among messages transmitted to the multiplex transmission path, the multiplex transmission equipment having mutually connected multiplex transmission paths. It has a data storage area for storing data corresponding to the registration means, and when a message is fetched, it is judged whether or not a data identifier exists in the registration means,
If there is, in the communication method of the multiplex transmission system for storing the data corresponding to the data identifier in a predetermined data storage area, the multiplex transmission device on the transmission side specifies at least a part of the data among the predetermined data. The multiplexed transmission device on the receiving side has a bit storage area for storing bits indicating reading of data stored in the data storage area or storage of data in the data storage area.
When storing the received data in a predetermined data storage area corresponding to the data identifier, the bit of the bit storage area is changed to a bit indicating the start of data storage, and the data stored in the data storage area is changed. Regardless of whether the data is read or not, the data corresponding to the data identifier is stored in the data storage area, the bit in the bit storage area is changed to a bit indicating the end of data storage, and the data is stored in the predetermined data storage area. When reading the read data, the bit in the bit storage area corresponding to the predetermined data storage area is confirmed, after the data is read, the bit in the bit storage area is confirmed again, and the confirmation result The validity of the read data is determined according to the above, and the data abnormality is detected according to a predetermined change of at least a part of the data. Communication method for multiplex transmission system, characterized in that the cross-sectional. 4. The transmitting-side multiplex transmission apparatus transmits the partial data of the data and a part of the other data in a specific relationship with each other. When reading the data stored in the data storage area, the device compares the part of the data with another part of the data, and determines whether the data is abnormal according to the comparison result. The communication method of the multiplex transmission system according to claim 2 or 3. 5. The transmission-side multiplex transmission device increments the value of the partial data, and at the same time transmits the other partial data as inverted data of the partial data. 4. The communication method of the multiplex transmission system according to 4. 6. The part of the data is at least the first data of the data, and the other part of the data is at least the last data of the data. The communication method of the multiplex transmission system according to claim 4 or 5. 7. A registration means for registering a data identifier of a necessary message among messages transmitted to the multiplex transmission path and mutually connected to the multiplex transmission path, and data corresponding to the registration means are stored. When a message is captured, it is determined whether a data identifier exists in the registration means, and if it exists, multiplex transmission in which data corresponding to the data identifier is stored in a predetermined data storage area In the device, a bit storage area which is provided corresponding to the registration means and stores a bit indicating reading of data stored in the data storage area or storage of data in the data storage area; Changing means for changing the stored bit, and the data identification regardless of whether the data stored in the data storage area is read or not. Storage control means for storing the data corresponding to the child in the data storage area, and the validity of the data read from the data storage area,
A multiplex transmission apparatus comprising: a determination unit that determines according to a bit in the bit storage area.