JPH07106937A - Semiconductor switch - Google Patents

Abstract

PURPOSE:To provide a semiconductor switch with low the insertion loss and low distortions despite its small size and low voltage drive. CONSTITUTION:The pinch-off voltage VPB of a 1st field effect transistor TR stage 10B connected in series to a signal path is set at a potential lower than the pinch-off voltage VPA of a 2nd field effect TR stage 10A connected between the signal path and the ground potential. So that both stage 10A and 10B are not operated in the same operation characteristic. Thus it is possible to turn on only the stage 10B connected in series to the signal path without causing the leakage electric power at the stage 10A connected between the signal path and the ground potential. In such a constitution, the inserting loss and the distortions of a semiconductor switch can be further reduced.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIG. 11) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 2 and 7) Action (FIGS. 3 and 4) Example (FIGS. 1 to 10) (1) Principle of distortion generation (FIG. 1) (2) Configuration of switch circuit (FIGS. 2 to 6) (3) SPDT switch circuit (FIG. 7) (4) Setting of pinch-off voltage V _P (FIGS. 8 to 10) (4-1) Setting of pinch-off voltage V _P obtained from saturation current I _DSS (FIGS. 8 to 10) (4-2) Setting of pinch-off voltage V _P using gate width Wg (FIGS. 8 to 10) (5) Other Examples Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch,
For example, it can be applied to an antenna switch of a digital cellular telephone.

[0003]

2. Description of the Related Art At present, mobile communication businesses such as car phones and mobile phones have been greatly developed. Along with this, the shortage of communication lines has become serious in urban areas. For this reason, various mobile communication systems are about to start up in various countries. Many of these communication systems use the quasi-microwave band on the higher frequency side than the current mobile communication systems.

In portable terminals in these communication systems, semiconductor field effect transistors (FET: field) are used.
effect transistors) are often used to process quasi-microwave signals. Especially when using the quasi-microwave band, various conditions (ie small size,
MMIC (Monolith) using gallium arsenide field effect transistor that can realize low voltage drive and low power consumption
The development of ic Microwave ICs) is becoming important.

Among the microwave signal processing devices using these gallium / arsenic / field effect transistors, one of the important key devices is SPDT (Single Pole Dual Thr).
ough) There is a switch. This SPDT switch is shown in FIG.
Shown in. The SPDT switch 1 is composed of a transmission switch 2 and a reception switch 3. Field effect transistors having the same pinch-off voltage V _P (= 0.5 [V]) are used for the shunt FETs 2A and 3A and the series FETs 2B and 3B that form the two switches 2 and 3, respectively.

The transmission side switch 2 switches whether to transmit the high frequency signal given from the transmission circuit to the terminal P1 to the antenna terminal P2, and the other receiving side switch 3 transmits the high frequency signal received by the antenna. Antenna terminal P
It is switched whether to transmit from 2 to the receiving circuit via the terminal P3. Then, the SPDT (Single Pole Dual Through) configured by the field effect transistor in this way
The power consumption of the switch is essentially very low.

[0007]

However, in the case of a mobile communication mobile terminal, the insertion loss of the switch portion (that is, the shunt FET 2A and the series FET 2B) connecting the transmission terminal and the antenna in this way contributes to the power consumption of the entire mobile terminal. It has a great influence. Therefore, it is necessary to make the insertion loss of the receiving switch 2 as small as possible. Also, since the transmission microwave power may be quite large (for example, about 10 W), the linearity of the transmission characteristic of the reception side switch 2 is compensated (that is, low distortion) is used for mobile communication portable terminals. It is especially important for the SPDT switch to be performed.

For this reason, there has been proposed a method of reducing distortion by connecting two shunt FETs 2A connected in series to the signal path in series or using a dual gate FET.

However, in the case of the former method (P. Bemkopf, M.
Schindler, A.Bertrand, "A HIGH POWER K / Ka-BAND MONOL
ITHIC T / R SWITCH ", IEEE Microwave and Millimeter-Wa
ve Monolithic Circuits Symposium Digest, 1991, pp.15
-18), there is a problem such as an increase in device size due to an increase in the number of FETs and a deterioration in characteristics due to an increase in loss in the FET portion, and the control voltage is also 0 / -10 [V], which is widely applied to mobile communication terminals Was not suitable for.

Similarly, in the case of the latter method (MJ Schindler,
TEKazior, "A High Power 2-18 GHz T / R Switch", 1990
IEEE MTT-S Digest, pp.453-456), which is advantageous in terms of loss compared to the former case, but has a problem of poor linearity.
Further, the insertion loss is increased and the control voltage is 0 / -14 [V], -10 as compared with the case of the single gate FET.
[V] and -7 [V] are large and cannot be said to be suitable for low voltage driving.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a semiconductor switch which is small in size and can realize both low insertion loss and low distortion at the same time by low voltage driving. To do.

[0012]

In order to solve such a problem, in the present invention, a signal path (between P11 and P12) is provided.
A first field-effect transistor stage 10B connected in series with the signal path (between 11 and P12) and the ground potential, the pinch-off voltage V _PA being the pinch-off voltage V _PA in the first field-effect transistor stage 10B. _The semiconductor switch is formed by providing the second field effect transistor stage 10A which is set to a potential higher than _PB .

Further, in the present invention, the first terminal P21
And a first field-effect transistor stage 21B connected in series to a first signal path having a transmission path between the second signal terminal P22 and the second terminal P22, and a pinch-off voltage V connected between the first signal path and the ground potential. _PA is the first field effect transistor stage 21
The second field effect transistor stage 21A, which is set to a higher potential than the pinch-off voltage V _PB at B, and the second signal path having the reception path between the second terminal P22 and the third terminal P23. are connected in series for a third field effect transistor stage 22B to pinch-off voltage V _PB is set higher than the pinch-off voltage V _PB potential at the first field effect transistor stage 21B, the second signal path A semiconductor switch is formed by providing a fourth field effect transistor stage 22A connected between the and the ground potential.

[0014]

The pinch-off voltage V _PB of the first field effect transistor stage 10B connected in series to the signal path is compared with the pinch-off voltage V _{PA of} the second field effect transistor stage 10A connected between the signal path and the ground potential. Are set to a low potential to prevent the first and second field effect transistor stages 10B and 10A from operating due to the same operating characteristics.
As a result, only the first field effect transistor stage 10B connected in series to the signal path is turned on without generating leakage power in the second field effect transistor stage 10A connected between the signal path and the ground potential. be able to. As a result, the insertion loss due to the first field effect transistor stage 10B can be reduced, and the distortion caused by the first and second field effect transistor stages 10B and 10A can be further reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Principle of distortion generation First, the distortion generation mechanism of a switch circuit using an FET will be described. There are two types of distortion: distortion that occurs when the FET is in the ON state and distortion that occurs when the FET is in the OFF state.
There are types.

The former distortion is due to current limitation.
It should be understood that the high-frequency signal current flows when a high frequency signal passes between the drain of the FET and the source is due to the inability to flow more than the saturation current I _DSS, the portion where the current amplitude exceeding the saturation current I _DSS flows Becomes distortion.

On the other hand, the latter strain is caused by the flow of a current that should not flow. This is FE
In which the drain and the high frequency signal voltage applied between the source of the T is due to the leakage power is generated when crossing a pinch-off voltage V _P or breakdown voltage V _BR, the amplitude exceeding these voltages V _P The V _BR The portion to which the voltage is applied (the hatched portion in FIG. 1) becomes the distortion.

Of these two types of distortion, a problem in a switch circuit of a communication terminal driven at a low voltage such as a digital cellular telephone is a distortion when the high frequency signal voltage exceeds the pinch-off voltage V _P. That is, this is the case where the amplitude of the high frequency signal voltage becomes larger than the difference between the pinch-off voltage V _P and the DC gate bias V _BIASS . In this case, a leak current flows through the shunt FET which should be in a non-conducting state, and the signal current flowing through the antenna terminal P2 is distorted.

(2) Configuration of switch circuit In FIG. 2, reference numeral 10 is a switch circuit 10 used in this embodiment.
Indicates. This switch circuit 10 is a series FET 1 connected in series (that is, in series) to a signal line.
A shunt FET 10 in which a pinch-off voltage VPB of 0B is connected (that is, shunt) between the signal line and the ground potential.
It is characterized in that it is set lower than the pinch-off voltage VPA of A.

In the case of this embodiment, the former pinch-off voltage V _PB is set to -1.0 [V] and the latter pinch-off voltage V _PA is set to 0.5 [V]. By thus providing the potential difference between the pinch-off voltages V _PB and V _PA, it is possible to reduce insertion loss and distortion at the same time.

Each FET 10A, 10B at this time
The operating state of will be described with reference to FIG. Switch circuit 10
When the switch of the above turns on (that is, the series FE
T10B is on and the shunt FET 10A
Is in the off state), the series FE in the on state
The drain-source resistance of T10B is small because the pinch-off voltage V _PB is set low. Thereby, from the terminal P11 to the terminal P12 side (or from the terminal P12 to the terminal P
11) It is possible to pass a relatively large signal current I _dB ,
The insertion loss can be kept small.

On the other hand, the series FET 10 in the off state
Since the pinch-off voltage V _{PA of A} is set high, the potential difference between the DC gate bias voltage V _BIASS (V _OFF ) and the pinch-off voltage V _PA is set to a large value. As a result, even when a high-power high-frequency signal is input, the high-frequency signal voltage amplitude does not exceed the pinch-off voltage V _{PA of the} FET, and the distortion can be suppressed to a very small level.

Next, simulation results of insertion loss characteristics when the switch circuit 10 is used are shown in FIGS. In this simulation, the actually measured GaAs type JFET
(Junction FET) data is used. Figure 4
Is the switch circuit 10 of the embodiment (that is, series FET).
FIG. 5 and FIG. 6 show simulation results for the pinch-off voltage V _PB of −10 [V] and the pinch-off voltage V _{PA of the} shunt FET 10A of 0.5 [V].
Are the simulation results of the conventional switch circuit 1, respectively.

FIG. 5 shows the pinch-off voltages V _PA and V _PB.
Shows the simulation result when both are 0.5 [V], and FIG. 6 shows that both pinch-off voltages V _PA and V _PB are -1.0.
The simulation result when [V] is shown is shown. In addition, all FET gate width is 1 [mm], gate length is 0.5 [μ
m]. As can be seen from the figure, in the case of the switch circuit 10 of the embodiment, it is understood that the insertion loss is small and the deterioration of the characteristic curve is small.

Comparing the insertion loss at 1.5 [GHz], for example, the switch circuit 10 of the embodiment is about 0.15 as compared with the switch circuit 1 in which both the pinch-off voltages V _PA and V _PB are 0.5 [V]. It turns out that [dB] is superior.
On the other hand, in terms of insertion loss, the switch circuit 10 of the embodiment is almost the same as that of the switch circuit 1 in which the pinch-off voltages V _PA and V _PB are both -1.0 [V], but the embodiment is still the same in terms of isolation. Is better.

Consider distortion. Series FET1 in the ON state when the switch in the switch circuit is in the ON state
Since the gate width of 0B is sufficiently large, distortion due to current limitation can be ignored. Therefore, the strain intensity due to the voltage limitation generated in the shunt FET 10A in the off state determines the strain intensity of the entire switch. As described above, when the power supply voltage is relatively small, the distortion hardly occurs.

In fact, the FETs that make up the switch circuit 10
Is driven with a control voltage of 1 / -2 [V], the distortion can be suppressed sufficiently when the high frequency signal voltage is smaller than the difference between the DC gate bias and the pinch-off voltage.
In addition, the resistance value of the signal line to which the switch circuit 10 is connected is
FET which is 50 [Ω] and constitutes the switch circuit 10
If the threshold voltage of and the pinch-off voltage are equal,
The maximum high frequency power that can suppress distortion is 64.5
It can be as large as [mW]. On the other hand, in the insertion loss, the maximum high-frequency power of the conventional switch circuit 1 (an example in which the pinch-off voltages V _PB and V _{PA of the} two FETs 1B and 1A are both -1.0 [V]), which is significantly different from the switch circuit 10 of the embodiment. Is about 10 [mW].

As described above, since the switch circuit 10 is composed of the two FETs having different pinch-off voltages, it is small in size and excellent in the distortion characteristic and insertion loss. This makes it possible to reduce the gate width of the series FET 10B among the series FET 10B and the shunt FET 10A. Or shunt FET
The breakdown voltage of 10 A can be reduced.

(3) SPDT Switch Circuit Next, a case where the switch circuit 10 is applied to an SPDT switch circuit used as an antenna switch of a digital cellular telephone will be described. In FIG. 7, reference numeral 20 indicates an SPDT switch circuit using the switch circuit 10 as a whole.

In this way, even when used as the SPDT switch circuit 20, the potential of the pinch-off voltage V _PB of the series FETs 21B and 22B forming the receiving side switch 21 and the transmitting side switch 22 is set to the shunt FET 21A forming the receiving side switch 21. It is set higher than the potential of the pinch-off voltage V _VA . That is, the pinch-off voltage V _PB of the series FETs 21B and 22B is set to 0.5 [V],
Set the pinch-off voltage V _PA of the shunt FET 21A to -1.0.
Set to [V].

Incidentally, the pinch-off voltage V _{PA of the} shunt FET 22A constituting the receiving side switch 22 is the series FET.
It may be set to the same voltage as the pinch-off voltage V _{PB of} 22B (that is, may be set to 0.5 [V]), and like the shunt FET 21A that constitutes the transmission side switch 21.
The potential may be set lower than the pinch-off voltage V _PB of the series FET.

The switching operation of the SPDT switch circuit 20 will be described. First, the case where a high frequency signal modulated by a voice signal is transmitted from an antenna will be described. In this case, a high potential is applied to the gate of the series FET 21B that constitutes the transmission side switch 21 to control it to be in the ON state, and a low potential is applied to the gate of the shunt FET 21A to control it to be in the OFF state. At the same time, switch 2 on the receiving side
A low potential is applied to the gate of the series FET 22B that constitutes the second FET 2 to control it to the off state, and the shunt FET 22
A high potential is applied to A to control the ON state. As a result, the circuit on the receiving side becomes high impedance, and the high frequency signal sent from the transmitting circuit to the signal path is transmitted to the antenna terminal side.

Next, the case where a voice signal is demodulated from a high frequency signal received by an antenna will be described. In this case, contrary to the case of transmission, the series FET 22B of the receiving side switch 22 is controlled to be in the ON state, and the shunt F
Controls the ET22A to the off state. At the same time, the series FET 21B of the transmission side switch 21 is controlled to the off state, and the shunt FET 21A is controlled to the on state. As a result, the circuit on the transmission side becomes high impedance, and the high frequency signal input from the antenna terminal is transmitted to the reception circuit through the signal path.

Since the SPDT switch circuit 20 is constructed by using the switch circuit 10 as a basic element in this way, as in the case of the switch circuit 10, it is small but has low distortion.
It is possible to realize operating characteristics of low voltage driving and low insertion loss.

(4) Setting of pinch-off voltage V _P Here, the series FETs 10B, 21B and 22 that form the switch circuit 10 and the SPDT circuit 20 described above.
B pinch-off voltage V _PB and shunt FETs 10A, 21
A method of setting the pinch-off voltage V _PA of A and 22A will be described. There are two methods for setting the pinch-off voltage V _P , which is based on the saturation current I _DSS flowing between the drain and source of the FET, and based on the gate width Wg of the FET.

(4-1) Setting of Pinch-off Voltage V _P Obtained from Saturation Current I _DSS First, a method of setting the pinch-off voltage V _P of the switch circuit 10 will be described. Pinch-off voltage V _PB of series FET 10B constituting switch circuit 10 and shunt FET
The pinch-off voltage V _{PA of} 10 A is calculated by the following equation.

[Equation 9]

[Equation 10] It should be set so as to satisfy.

_Incidentally , V _{PIDSS in the} equation (9) is the current amplitude I _RF of the high frequency signal passing between the drain and the source and the drain-source.
The saturation current I _DSS between the sources becomes equal (I _RF = I
It is the pinch-off voltage when _DSS ). In addition, V in equation (10)
_RF is the voltage amplitude of the high frequency signal passing between the drain and source, and V _OFF is the off bias voltage.

Next, a method of setting the pinch-off voltage V _P for the SPDT switch circuit 20 will be described. In this case, the pinch-off voltage V _PB of the series FET 21B constituting the transmission side switch 21 is set based on the equation (1), and the shunt FET 21 constituting the transmission side switch 21 is set.
Series FET22 that composes A and the receiving switch 22
The B pinch-off voltages V _PA and V _PB may be set based on equation (10).

This is for the following reason. In general, the FET saturation current I _DSS is the maximum value of the direct current that can flow between the drain and the source at a certain gate bias. Further, even when a high frequency signal is input between the drain and source, the current value of the high frequency signal cannot exceed I _DSS . Therefore, when a high frequency signal having a current amplitude equal to or higher than the saturation current I _DSS is input between the drain and source of the FET, a part of the high frequency signal cannot be transmitted, resulting in a large distortion. Therefore, the condition for suppressing distortion with respect to high-frequency current is
The following formula

[Equation 11] Becomes From this equation, the condition of equation (9) is obtained.

A practical example will be given. Figure 8 shows a gate width of 1 [m
[m] is a pinch-off voltage dependence characteristic of the saturation current I _DSS of the GaAs type JFET. Looking at this figure, the saturation current I
It can be seen that _DSS changes almost linearly with the pinch-off voltage V _P. This results in a saturation current I _DSS
Is the expression

[Equation 12] Can be represented by Here, A and B are device-specific constants, respectively, and Wg is the FET gate width.

FIG. 9 shows a GaAs JFET
It is the input voltage dependency of the third-order high-frequency distortion generated when a high-frequency signal passes through the FET in the ON state (Vg = 1 [V]). As can be seen from this figure, when a high frequency signal having a current amplitude equal to that of the saturation current I _DSS is input, the magnitude of about -46 [dBm] is a sufficiently small level distortion for the switch. Therefore, it can be said that the distortion can be suppressed to a sufficiently small level when a high frequency signal having an amplitude less than the saturation current is input. That is, the condition for suppressing the strain generated from the FET in the ON state to be small is expressed by the equation (11).

By substituting the equation (12) into the equation (11) and summarizing the pinch-off voltage V _P , the following equation is obtained.

[Equation 13] Becomes On the contrary, if the equation (13) is satisfied, the distortion generated from the FET in the ON state can be suppressed sufficiently small. The condition of equation (13) is considered to be a modification of equation (9) when equation (12) is assumed.

Next, the distortion generated from the FET in the off state will be considered. FIG. 10 shows the input voltage dependency of the third-order high-frequency distortion generated from the FET in the off state. From this figure, it can be seen that the distortion increases rapidly at a certain input voltage. When high-frequency voltage V _RF is applied between the source and drain of the FET - - off the drain of the state of the FET gate, the gate - half the voltage of the high-frequency voltage V _RF is between the source (V _RF /
2) will be applied. As a result, this voltage (V
_RF / 2) is superimposed on the DC bias Vg (DC) in the off state.

This high frequency voltage V _RF and DC bias Vg (D
When the gate bias in which C) is superimposed exceeds the pinch-off voltage V _P , the FET is no longer in the pinch-off state,
Leakage power is generated between the drain and the source. This causes a large amount of distortion, which is the cause of the rapid increase in distortion in FIG. Also, from the figure, if the input power is less than the power that causes the sudden distortion increase, the intercept point of the third harmonic distortion is calculated to be about 50 [dBm]. In the case of, it can be said that the strain can be suppressed to a sufficiently small level. This condition is nothing but formula (10).

The switch circuit 1 is designed to satisfy this condition.
By configuring 0, when the switch of the switch circuit 10 is turned on (that is, the series FET 10B is turned on,
Distortion generated when the shunt FET 10A is turned off (strain generated in the series FET 10B and shunt FET)
It can be seen that the sum of the strain generated at 10 A) can be suppressed to a sufficiently small value.

(4-2) Setting of Pinch-off Voltage V _P Using Gate Width Wg Next, a method of setting the pinch-off voltage V _P of the switch circuit 10 will be described. Pinch-off voltage V _PB of series FET 10B constituting switch circuit 10 and shunt FET
The pinch-off voltage V _{PA of} 10 A is calculated by the following equation.

[Equation 14]

[Equation 15] It should be set so as to satisfy. Here, equation (15) becomes (1
It is the same as the expression 0). Incidentally, I _{RF in the} equation (6) is the current amplitude (mA) of the high-frequency signal passing between the drain and the source, and Wg is the gate width (mm). V _ON is an on bias voltage.

In the case of the SPDT switch circuit 20, the same setting may be made. That is, the pinch-off voltage V _PB of the series FET 21B forming the switch 21 on the transmission side is (6)
The pinch-off voltages V _PA and V _PB of the shunt FET 21A that constitutes the transmission side switch 21 and the series FET 22B that constitutes the reception side switch 22 may be set based on the equation (15), respectively.

This is for the following reason. As can be seen from FIG. 8 which shows the dependency of the saturation current I _DSS of the GaAs JFET having the gate width Wg of 1 mm on the pinch-off voltage, the saturation current I _DSS changes almost linearly with respect to the pinch-off voltage V _P. In general, the saturation current I _DSS is the gate width Wg
In proportion to, and it is proportional to the Vg -V _P. Considering this, the saturation current I _DSS is

[Equation 16] It can be expressed as.

Further, the FET in the ON state (Vg = 1 [V])
As can be seen from FIG. 9 which shows the input power dependence characteristic of the third-order high frequency distortion generated when the high frequency signal passes through, the input voltage of about −46 when the high frequency signal having the current amplitude equal to the magnitude of the saturation current I _DSS is input. It can be seen that the third harmonic distortion of [dBm] is generated. The magnitude of -46 [dBm] is a sufficiently low level distortion for a switch. Therefore, it can be said that the distortion can be suppressed to a sufficiently small level when a high frequency signal having an amplitude less than the saturation current is input. That is, the condition for suppressing the distortion generated from the FET in the ON state is
The following formula

[Equation 17] Becomes

By substituting the equation (16) into the equation (17) and summing up the pinch-off voltage V _P , the inverse of the equation (6) is obtained.
On the contrary, if the equation (16) is satisfied, the distortion generated from the FET in the ON state can be suppressed to a sufficiently small level. The distortion generated from the FET in the off-state is the same as the case described in the previous section, so the description thereof will be omitted.

In any case, if the switch circuit 10 is constructed so as to satisfy these conditions, the switch circuit 10
When turning on the switch (that is, series FET)
The distortion (the sum of the distortion generated in the series FET 10B and the distortion generated in the shunt FET 10A) that occurs when 10B is turned on and the shunt FET 10A is turned off can be suppressed sufficiently small.

(5) Other Embodiments In the above embodiment, the switch circuit 10 and the S
In any case of the PDT switch circuit 20, the FET at the shunt position and the FE at the series position with respect to the signal line
The case where each T is configured by a single-gate FET has been described, but the present invention is not limited to this, and a dual-gate FET or an FE having three or more gates is used.
It can be widely applied when it is configured by T.

In the above-described embodiment, in both the switch circuit 10 and the SPDT switch circuit 20, one FET is connected to the signal line at the shunt position and one FET is connected to the series position. However, the present invention is not limited to this, and a plurality of stages of FETs may be connected to each. in this case,
The distortion characteristics can be further improved as compared with the case where each of them is configured by one-stage connection.

Further, in the above-mentioned embodiments, the case where the FET connected to the series position and the FET connected to the shunt position with respect to the signal line are respectively constituted by JFETs has been described. The present invention is not limited to this, and it may be configured by a MESFET (Metal Semiconductor FET).

Further, in the above-mentioned embodiments, the case where each field effect transistor is formed on the semi-insulating GaAs substrate has been described, but the present invention is not limited to this, and each field effect transistor is formed on another compound semiconductor substrate. It can also be applied to the case of forming.

Further, in the above-mentioned embodiment, each FET is
However, the present invention is not limited to this, and the gates of the FETs may be driven by control voltages having other values.

Further, although the antenna switching switch for the digital cellular telephone has been described in the above embodiment, the present invention is not limited to this, and the mobile communication portable terminal such as a cordless telephone or the portable television receiver, etc. It can be applied to various devices that require low insertion loss and low distortion characteristics while being compact and driven at low voltage.

[0059]

As described above, according to the present invention, the second field effect transistor in which the pinch-off voltage of the first field effect transistor stage connected in series to the signal path is connected between the signal path and the ground potential. A second potential connected between the signal path and ground potential is set by setting the potential lower than the pinch-off voltage of the stage to prevent the first and second field effect transistor stages from operating due to the same operating characteristics. It is possible to easily realize a semiconductor switch capable of turning on only the first field effect transistor connected in series to the signal path without generating leakage power in the field effect transistor. As a result, the insertion loss and distortion of the semiconductor switch can be made much smaller than in the conventional case.

[Brief description of drawings]

FIG. 1 is a characteristic curve diagram showing the principle of strain generation in an FET.

FIG. 2 is a connection diagram showing an embodiment of a switch circuit according to the present invention.

FIG. 3 is a characteristic curve diagram for explaining a difference in current characteristics due to a difference in pinch-off voltage.

FIG. 4 is a characteristic curve diagram showing an insertion loss characteristic generated when the switch circuit of the embodiment is used.

FIG. 5 is a characteristic curve diagram showing insertion loss characteristics that occur when a conventional switch circuit is used.

FIG. 6 is a characteristic curve diagram showing insertion loss characteristics that occur when a conventional switch circuit is used.

FIG. 7 is a connection diagram showing an SPDT switch circuit according to an embodiment.

FIG. 8 is a characteristic curve diagram showing a pinch-off voltage dependence characteristic of a saturation current.

FIG. 9 is a characteristic curve diagram showing the input power dependence of the third harmonic distortion of the FET in the ON state.

FIG. 10 is a characteristic curve diagram showing the input power dependency of the third harmonic distortion of the FET in the off state.

FIG. 11 is a connection diagram showing a conventionally used SPDT switch circuit.

[Explanation of symbols]

1, 20 ... SPDT switch circuit, 2, 21 ... Input side switch, 3, 22 ... Output side switch, 10 ... Switch circuit, 2A, 3A, 10A ... Shunt FET,
2B, 3B, 10B ... Series FET, V _PA , V _PB ...
… Pinch off voltage.

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[Procedure amendment]

[Submission date] January 24, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

(2) Configuration of switch circuit In FIG. 2, reference numeral 10 is a switch circuit 10 used in this embodiment.
Indicates. This switch circuit 10 is a series FET 1 connected in series (that is, in series) to a signal line.
The pinch-off voltage _{V PB} of 0B the signal line between the ground potential shunt FET10 connected (i.e., shunt)
It is characterized in that it is set lower than the pinch-off voltage V _{PA of} A.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0027

[Correction method] Change

[Correction content]

Consider distortion. Series FET1 in the ON state when the switch in the switch circuit is in the ON state
Since the gate width of 0B is sufficiently large, distortion due to current limitation can be ignored. Therefore, the strain intensity due to the voltage limitation generated in the shunt FET 10A in the off state determines the strain intensity of the entire switch.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

As described above, even when used as the SPDT switch circuit 20, the transmission side switch 21 is constituted by the pinch-off voltages V _PA and V _PB of the shunt FET 21A and the series FET 22B constituting the transmission side switch 21 and the reception side switch 22. It is set higher than the potential of the pinch-off voltage V _PB of the series FET 21B. That is, the pinch-off voltage V of the FET 21A and the FET 22B
_PA, the _{V PB} is set to 0.5 [V] to set the pinch-off voltage _{V PB} of FET21B to -1.0 [V].

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Incidentally, the pinch-off voltage V _PA of the shunt FET 22A constituting the receiving side switch 22 is a series FE.
The voltage may be set to the same voltage as the pinch-off voltage V _{PB of} T22B (that is, may be set to 0.5 [V]), or set to the same potential as the pinch-off voltage V _PB of the series FET 21B constituting the transmission side switch 21. You may.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

(4) Setting of the pinch-off voltage V _P Here, the pinch-off voltage V _PB of the series FETs 10B and 21B forming the switch circuit 10 and the SPDT circuit 20 described above and the shunt FETs 10A, 21A and 2 are set.
A method of setting the pinch-off voltages V _PA and V _PB of 2B will be described. There are two methods of setting the pinch-off voltage V _{P, one} of which is based on the saturation current I _DSS flowing between the drain and the source of the FET, and the other of which is based on the gate width Wg of the FET.

Claims (11)

[Claims] 1. A first field effect transistor stage connected in series to a signal path, and a pinch-off voltage connected between the signal path and a ground potential, wherein a pinch-off voltage is higher than a pinch-off voltage in the first field-effect transistor stage. And a second field effect transistor stage set to a high potential. 2. A first field effect transistor stage connected in series to a first signal path having a transmission path between the first terminal and the second terminal, the first signal path and ground potential. A second field effect transistor stage connected between the second field effect transistor stage and the second field effect transistor stage, the pinch off voltage of which is set to a higher potential than the pinch off voltage of the first field effect transistor stage; A third field-effect transistor stage connected in series to a second signal path having a receiving path as a receiving path and having a pinch-off voltage set to a higher potential than the pinch-off voltage in the first field-effect transistor stage. A semiconductor switch comprising a fourth field effect transistor stage connected between the second signal path and ground potential. 3. A first field effect transistor stage connected in series to the signal path, and a second field effect transistor stage connected between the signal path and ground potential. Effect transistor stage pinch-off voltage V
_P1, to the value of the pinch-off voltage V _PIDSS when the saturation current I _DSS flowing between current amplitude I _RF and the drain and source of the high-frequency signal passing between the drain and source of the field effect transistor are equal, the following equation [Equation 1] And the pinch-off voltage V _P2 of the second field effect transistor stage is given by the voltage amplitude V _RF of the high frequency signal passing between the drain and source of the field effect transistor and the off bias voltage V _OFF. The following equation [Formula 2] A semiconductor switch characterized by satisfying the above conditions. 4. A first field effect transistor stage connected in series to a first signal path having a transmission path between the first terminal and the second terminal, the first signal path and ground potential. A second field effect transistor stage connected in between; and a third field effect transistor stage connected in series to a second signal path having a receiving path between the second terminal and the third terminal. A fourth field effect transistor stage connected between the second signal path and ground potential, the pinch-off voltage V of the first field effect transistor stage.
_P1, to the value of the pinch-off voltage V _PIDSS when the saturation current I _DSS flowing between current amplitude I _RF and the drain and source of the high-frequency signal passing between the drain and source of the field effect transistor are equal, the following equation [Equation 3] And the pinch-off voltage V _P2 of the second and third field-effect transistor stages is determined by the voltage amplitude V _RF of the high-frequency signal passing between the drain and source of the field-effect transistor and the off-bias voltage V _OFF . The following equation given by A semiconductor switch characterized by satisfying the above conditions. 5. A first field effect transistor stage connected in series to the signal path, and a second field effect transistor stage connected between the signal path and ground potential. Effect transistor stage pinch-off voltage V
_P1 is the current amplitude I _RF of the high frequency signal passing between the drain and source of the field effect transistor and the gate width Wg
And the on-bias voltage V _ON , given by And the pinch-off voltage V _P2 of the second field effect transistor stage is given by the voltage amplitude V _RF of the high frequency signal passing between the drain and source of the field effect transistor and the off bias voltage V _OFF. The following formula [Equation 6] A semiconductor switch characterized by satisfying the above conditions. 6. A first field effect transistor stage connected in series to a first signal path having a transmission path between the first terminal and the second terminal, the first signal path and ground potential. A second field effect transistor stage connected in between; and a third field effect transistor stage connected in series to a second signal path having a receiving path between the second terminal and the third terminal. A fourth field effect transistor stage connected between the second signal path and ground potential, the pinch-off voltage V of the first field effect transistor stage.
_P1 is the current amplitude I _RF of the high frequency signal passing between the drain and source of the field effect transistor and the gate width Wg
And the on-bias voltage V _ON , given by And the pinch-off voltage V _P2 of the second and third field-effect transistor stages is determined by the voltage amplitude V _RF of the high-frequency signal passing between the drain and source of the field-effect transistor and the off-bias voltage V _OFF . The following equation given by A semiconductor switch characterized by satisfying the above conditions. 7. The field effect transistor stage is formed by a single gate field effect transistor, claim 1, claim 2, claim 3, claim 4, claim 5.
Alternatively, the semiconductor switch according to claim 6. 8. The field effect transistor stage according to claim 1, claim 2, claim 3, claim 4, claim 5 or claim 6, wherein the field effect transistor stage comprises a multi-gate field effect transistor. Semiconductor switch. 9. The field effect transistor stage comprises a series connection of two or more field effect transistors, claim 1, claim 2, claim 3, claim 4, claim 5, or claim 9. Item 7. The semiconductor switch according to item 6. 10. The field effect transistor stage is formed by a junction field effect transistor, claim 1, claim 2, claim 3, claim 4, claim 5 or claim 10. 6. The semiconductor switch according to item 6. 11. The field effect transistor stage comprises a metal-
It is formed by a semiconductor field effect transistor, claim 1, claim 2, claim 3, claim 4, characterized in that.
The semiconductor switch according to claim 5 or 6.